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[PATCH v2 00/14] OpenRISC SMP Support

Started by	Stafford Horne <shorne@gmail.com>
First post	2017-09-10 08:50 +0200
Last post	2017-09-10 09:00 +0200
Articles	20 on this page of 23 — 4 participants

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  [PATCH v2 00/14] OpenRISC SMP Support Stafford Horne <shorne@gmail.com> - 2017-09-10 08:50 +0200
    [PATCH v2 10/14] openrisc: add cacheflush support to fix icache aliasing Stafford Horne <shorne@gmail.com> - 2017-09-10 09:00 +0200
    [PATCH v2 11/14] openrisc: add simple_smp dts and defconfig for simulators Stafford Horne <shorne@gmail.com> - 2017-09-10 09:00 +0200
    [PATCH v2 09/14] openrisc: sleep instead of spin on secondary wait Stafford Horne <shorne@gmail.com> - 2017-09-10 09:00 +0200
    [PATCH v2 13/14] openrisc: enable LOCKDEP_SUPPORT and irqflags tracing Stafford Horne <shorne@gmail.com> - 2017-09-10 09:00 +0200
    [PATCH v2 03/14] openrisc: add 1 and 2 byte cmpxchg support Stafford Horne <shorne@gmail.com> - 2017-09-10 09:00 +0200
    [PATCH v2 02/14] openrisc: define CPU_BIG_ENDIAN as true Stafford Horne <shorne@gmail.com> - 2017-09-10 09:00 +0200
    [PATCH v2 12/14] openrisc: support framepointers and STACKTRACE_SUPPORT Stafford Horne <shorne@gmail.com> - 2017-09-10 09:00 +0200
    [PATCH v2 08/14] openrisc: fix initial preempt state for secondary cpu tasks Stafford Horne <shorne@gmail.com> - 2017-09-10 09:00 +0200
    [PATCH v2 01/14] openrisc: use shadow registers to save regs on exception Stafford Horne <shorne@gmail.com> - 2017-09-10 09:00 +0200
    [PATCH v2 04/14] openrisc: use qspinlocks and qrwlocks Stafford Horne <shorne@gmail.com> - 2017-09-10 09:00 +0200
    [PATCH v2 05/14] dt-bindings: add openrisc to vendor prefixes list Stafford Horne <shorne@gmail.com> - 2017-09-10 09:00 +0200
      Re: [PATCH v2 05/14] dt-bindings: add openrisc to vendor prefixes  list Andreas Färber <afaerber@suse.de> - 2017-09-10 13:20 +0200
      Re: [PATCH v2 05/14] dt-bindings: add openrisc to vendor prefixes  list Rob Herring <robh@kernel.org> - 2017-09-18 22:40 +0200
    [PATCH v2 06/14] irqchip: add initial support for ompic Stafford Horne <shorne@gmail.com> - 2017-09-10 09:00 +0200
      Re: [PATCH v2 06/14] irqchip: add initial support for ompic Marc Zyngier <marc.zyngier@arm.com> - 2017-09-13 19:30 +0200
        Re: [PATCH v2 06/14] irqchip: add initial support for ompic Stafford Horne <shorne@gmail.com> - 2017-09-14 09:00 +0200
          Re: [PATCH v2 06/14] irqchip: add initial support for ompic Marc Zyngier <marc.zyngier@arm.com> - 2017-09-14 20:40 +0200
          Re: [PATCH v2 06/14] irqchip: add initial support for ompic Rob Herring <robh@kernel.org> - 2017-09-18 22:40 +0200
            Re: [PATCH v2 06/14] irqchip: add initial support for ompic Stafford Horne <shorne@gmail.com> - 2017-09-19 14:20 +0200
      Re: [PATCH v2 06/14] irqchip: add initial support for ompic Rob Herring <robh@kernel.org> - 2017-09-18 22:50 +0200
        Re: [PATCH v2 06/14] irqchip: add initial support for ompic Stafford Horne <shorne@gmail.com> - 2017-09-19 14:20 +0200
    [PATCH v2 14/14] openrisc: add tick timer multicore sync logic Stafford Horne <shorne@gmail.com> - 2017-09-10 09:00 +0200

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#1729919 — [PATCH v2 00/14] OpenRISC SMP Support

From	Stafford Horne <shorne@gmail.com>
Date	2017-09-10 08:50 +0200
Subject	[PATCH v2 00/14] OpenRISC SMP Support
Message-ID	<uo4e5-8k3-7@gated-at.bofh.it>

Hello Again,

This series adds SMP support for OpenRISC.  The OpenRISC multicore platform
and SMP linux support is based on the work that Stefan Kristiansson did
around 2012 implemented in Verilog and run on FPGAs.  I have been working
to upstream this work. I have additionally tested this on QEMU, which I
patched for OpenRISC multicore support, as well as FPGA.

I have documented the architecture in the OpenRISC 1.2 specification
proposal available here:
  https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-rev0.pdf

The QEMU patches are still under review but are available here for testers
and anyone interested:
  https://github.com/stffrdhrn/qemu.git openrisc-smp-v1

This series contains a bit of a mix of patches to get everything working.
 o First the "use shadow registers" and "define CPU_BIG_ENDIAN as true" get
   the architecture ready for SMP.
 o The "add 1 and 2 byte cmpxchg support" and "use qspinlocks and qrwlocks"
   add the SMP locking infrastructure as needed.  Using the qspinlocks and
   qrwlocks as suggested by Peter Z while reviewing the original spinlocks
   implementation.
 o The "support for ompic" adds a new irqchip device which is used for IPI
   communication to support SMP.  (Perhaps this patch should go via another
   route but included here for completeness - confirmed this is ok)
 o The "initial SMP support" adds smp.c and makes changes to all of the
   necessary data-structures to be per-cpu.
 o The remaining patches are bug fixes and debug helpers which I wanted
   to keep separate from the "initial SMP support" in order to allow them
   to be reviewed on their own. This includes:
    - add cacheflush support to fix icache aliasing
    - fix initial preempt state for secondary cpu tasks
    - sleep instead of spin on secondary wait
    - support framepointers and STACKTRACE_SUPPORT
    - enable LOCKDEP_SUPPORT and irqflags tracing
    - timer sync: Add tick timer sync logic

--

Changes since v1
  - refactor of timer headers to not require extern openrisc_timer_init()
    in smp.c
  - check for power management unit when sleeping on secondary cpu wait
  - fixed cpuinfo to print online CPUs only
  - cleanups for the ompic suggested by Marc Zyngier and Mark Rutland
    > don't say size is arbitrary, it's 8 bytes per CPU
    > validate register size vs cpus
    > add validations for all initialization failures
    > use percpu for percpu ipi ops
    > remove SMP and OF #ifdefs
    > document details about OpenRISC implied barriers
    > use vendor prefix openrisc,
    > removed #interrupt-cells as this will not be a parent
    > added some architecture documentation into the source
  - enforce shadow register usage for SMP as suggested by Geert
  - DTS updates suggested by Mark Rutland
    > Add and use vendor prefix openrisc, for ompic
    > Use stdout-path

-Stafford



Jan Henrik Weinstock (1):
  openrisc: add cacheflush support to fix icache aliasing

Stafford Horne (9):
  openrisc: define CPU_BIG_ENDIAN as true
  openrisc: add 1 and 2 byte cmpxchg support
  openrisc: use qspinlocks and qrwlocks
  dt-bindings: add openrisc to vendor prefixes list
  openrisc: fix initial preempt state for secondary cpu tasks
  openrisc: sleep instead of spin on secondary wait
  openrisc: support framepointers and STACKTRACE_SUPPORT
  openrisc: enable LOCKDEP_SUPPORT and irqflags tracing
  openrisc: add tick timer multicore sync logic

Stefan Kristiansson (4):
  openrisc: use shadow registers to save regs on exception
  irqchip: add initial support for ompic
  openrisc: initial SMP support
  openrisc: add simple_smp dts and defconfig for simulators

 .../interrupt-controller/openrisc,ompic.txt        |  19 ++
 .../devicetree/bindings/vendor-prefixes.txt        |   1 +
 arch/openrisc/Kconfig                              |  52 ++++-
 arch/openrisc/boot/dts/simple_smp.dts              |  58 +++++
 arch/openrisc/configs/simple_smp_defconfig         |  66 ++++++
 arch/openrisc/include/asm/Kbuild                   |   5 +-
 arch/openrisc/include/asm/cacheflush.h             |  96 ++++++++
 arch/openrisc/include/asm/cmpxchg.h                | 147 +++++++++---
 arch/openrisc/include/asm/cpuinfo.h                |   7 +-
 arch/openrisc/include/asm/mmu_context.h            |   2 +-
 arch/openrisc/include/asm/pgtable.h                |  18 +-
 arch/openrisc/include/asm/serial.h                 |   2 +-
 arch/openrisc/include/asm/smp.h                    |  26 +++
 arch/openrisc/include/asm/spinlock.h               |  12 +-
 arch/openrisc/include/asm/spinlock_types.h         |   7 +
 arch/openrisc/include/asm/spr_defs.h               |  14 ++
 arch/openrisc/include/asm/thread_info.h            |   2 +-
 arch/openrisc/include/asm/time.h                   |  23 ++
 arch/openrisc/include/asm/tlbflush.h               |  25 +-
 arch/openrisc/include/asm/unwinder.h               |  20 ++
 arch/openrisc/kernel/Makefile                      |   4 +-
 arch/openrisc/kernel/dma.c                         |  14 +-
 arch/openrisc/kernel/entry.S                       |  74 +++++-
 arch/openrisc/kernel/head.S                        | 239 ++++++++++++++++---
 arch/openrisc/kernel/setup.c                       | 165 ++++++++-----
 arch/openrisc/kernel/smp.c                         | 259 +++++++++++++++++++++
 arch/openrisc/kernel/stacktrace.c                  |  86 +++++++
 arch/openrisc/kernel/sync-timer.c                  | 120 ++++++++++
 arch/openrisc/kernel/time.c                        |  66 ++++--
 arch/openrisc/kernel/traps.c                       |  54 +----
 arch/openrisc/kernel/unwinder.c                    | 105 +++++++++
 arch/openrisc/lib/delay.c                          |   2 +-
 arch/openrisc/mm/Makefile                          |   2 +-
 arch/openrisc/mm/cache.c                           |  61 +++++
 arch/openrisc/mm/fault.c                           |   4 +-
 arch/openrisc/mm/init.c                            |   2 +-
 arch/openrisc/mm/tlb.c                             |  16 +-
 drivers/irqchip/Kconfig                            |   3 +
 drivers/irqchip/Makefile                           |   1 +
 drivers/irqchip/irq-ompic.c                        | 205 ++++++++++++++++
 40 files changed, 1850 insertions(+), 234 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt
 create mode 100644 arch/openrisc/boot/dts/simple_smp.dts
 create mode 100644 arch/openrisc/configs/simple_smp_defconfig
 create mode 100644 arch/openrisc/include/asm/cacheflush.h
 create mode 100644 arch/openrisc/include/asm/smp.h
 create mode 100644 arch/openrisc/include/asm/spinlock_types.h
 create mode 100644 arch/openrisc/include/asm/time.h
 create mode 100644 arch/openrisc/include/asm/unwinder.h
 create mode 100644 arch/openrisc/kernel/smp.c
 create mode 100644 arch/openrisc/kernel/stacktrace.c
 create mode 100644 arch/openrisc/kernel/sync-timer.c
 create mode 100644 arch/openrisc/kernel/unwinder.c
 create mode 100644 arch/openrisc/mm/cache.c
 create mode 100644 drivers/irqchip/irq-ompic.c

-- 
2.13.5

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#1729920 — [PATCH v2 10/14] openrisc: add cacheflush support to fix icache aliasing

From	Stafford Horne <shorne@gmail.com>
Date	2017-09-10 09:00 +0200
Subject	[PATCH v2 10/14] openrisc: add cacheflush support to fix icache aliasing
Message-ID	<uo4nL-8oU-1@gated-at.bofh.it>
In reply to	#1729919

From: Jan Henrik Weinstock <jan.weinstock@ice.rwth-aachen.de>

On OpenRISC the icache does not snoop data stores.  This can cause
aliasing as reported by Jan. This patch fixes the issue to ensure icache
is properly synchronized when code is written to memory.  It supports both
SMP and UP flushing.

This supports dcache flush as well for architectures that do not support
write-through caches; most OpenRISC implementations do implement
write-through cache however. Dcache flushes are done only on a single
core as OpenRISC dcaches all support snooping of bus stores.

Signed-off-by: Jan Henrik Weinstock <jan.weinstock@ice.rwth-aachen.de>
[shorne@gmail.com: Squashed patches and wrote commit message]
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 arch/openrisc/Kconfig                  | 11 ++++
 arch/openrisc/include/asm/Kbuild       |  1 -
 arch/openrisc/include/asm/cacheflush.h | 96 ++++++++++++++++++++++++++++++++++
 arch/openrisc/include/asm/pgtable.h    | 16 +++---
 arch/openrisc/kernel/smp.c             | 15 ++++++
 arch/openrisc/mm/Makefile              |  2 +-
 arch/openrisc/mm/cache.c               | 61 +++++++++++++++++++++
 7 files changed, 194 insertions(+), 8 deletions(-)
 create mode 100644 arch/openrisc/include/asm/cacheflush.h
 create mode 100644 arch/openrisc/mm/cache.c

diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index 2b3898ede888..bfff04ae7f7d 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -77,6 +77,17 @@ config OR1K_1200
 
 endchoice
 
+config DCACHE_WRITETHROUGH
+	bool "Have write through data caches"
+	default n
+	help
+	  Select this if your implementation features write through data caches.
+	  Selecting 'N' here will allow the kernel to force flushing of data
+	  caches at relevant times. Most OpenRISC implementations support write-
+	  through data caches.
+
+	  If unsure say N here
+
 config OPENRISC_BUILTIN_DTB
         string "Builtin DTB"
         default ""
diff --git a/arch/openrisc/include/asm/Kbuild b/arch/openrisc/include/asm/Kbuild
index 5f066780d870..6eb16719549e 100644
--- a/arch/openrisc/include/asm/Kbuild
+++ b/arch/openrisc/include/asm/Kbuild
@@ -1,7 +1,6 @@
 generic-y += barrier.h
 generic-y += bug.h
 generic-y += bugs.h
-generic-y += cacheflush.h
 generic-y += checksum.h
 generic-y += clkdev.h
 generic-y += current.h
diff --git a/arch/openrisc/include/asm/cacheflush.h b/arch/openrisc/include/asm/cacheflush.h
new file mode 100644
index 000000000000..70f46fd7a074
--- /dev/null
+++ b/arch/openrisc/include/asm/cacheflush.h
@@ -0,0 +1,96 @@
+/*
+ * OpenRISC Linux
+ *
+ * Linux architectural port borrowing liberally from similar works of
+ * others.  All original copyrights apply as per the original source
+ * declaration.
+ *
+ * OpenRISC implementation:
+ * Copyright (C) Jan Henrik Weinstock <jan.weinstock@rwth-aachen.de>
+ * et al.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __ASM_CACHEFLUSH_H
+#define __ASM_CACHEFLUSH_H
+
+#include <linux/mm.h>
+
+/*
+ * Helper function for flushing or invalidating entire pages from data
+ * and instruction caches. SMP needs a little extra work, since we need
+ * to flush the pages on all cpus.
+ */
+extern void local_dcache_page_flush(struct page *page);
+extern void local_icache_page_inv(struct page *page);
+
+/*
+ * Data cache flushing always happen on the local cpu. Instruction cache
+ * invalidations need to be broadcasted to all other cpu in the system in
+ * case of SMP configurations.
+ */
+#ifndef CONFIG_SMP
+#define dcache_page_flush(page)      local_dcache_page_flush(page)
+#define icache_page_inv(page)        local_icache_page_inv(page)
+#else  /* CONFIG_SMP */
+#define dcache_page_flush(page)      local_dcache_page_flush(page)
+#define icache_page_inv(page)        smp_icache_page_inv(page)
+extern void smp_icache_page_inv(struct page *page);
+#endif /* CONFIG_SMP */
+
+/*
+ * Synchronizes caches. Whenever a cpu writes executable code to memory, this
+ * should be called to make sure the processor sees the newly written code.
+ */
+static inline void sync_icache_dcache(struct page *page)
+{
+	if (!IS_ENABLED(CONFIG_DCACHE_WRITETHROUGH))
+		dcache_page_flush(page);
+	icache_page_inv(page);
+}
+
+/*
+ * Pages with this bit set need not be flushed/invalidated, since
+ * they have not changed since last flush. New pages start with
+ * PG_arch_1 not set and are therefore dirty by default.
+ */
+#define PG_dc_clean                  PG_arch_1
+
+#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
+static inline void flush_dcache_page(struct page *page)
+{
+	clear_bit(PG_dc_clean, &page->flags);
+}
+
+/*
+ * Other interfaces are not required since we do not have virtually
+ * indexed or tagged caches. So we can use the default here.
+ */
+#define flush_cache_all()				do { } while (0)
+#define flush_cache_mm(mm)				do { } while (0)
+#define flush_cache_dup_mm(mm)				do { } while (0)
+#define flush_cache_range(vma, start, end)		do { } while (0)
+#define flush_cache_page(vma, vmaddr, pfn)		do { } while (0)
+#define flush_dcache_mmap_lock(mapping)			do { } while (0)
+#define flush_dcache_mmap_unlock(mapping)		do { } while (0)
+#define flush_icache_range(start, end)			do { } while (0)
+#define flush_icache_page(vma, pg)			do { } while (0)
+#define flush_icache_user_range(vma, pg, adr, len)	do { } while (0)
+#define flush_cache_vmap(start, end)			do { } while (0)
+#define flush_cache_vunmap(start, end)			do { } while (0)
+
+#define copy_to_user_page(vma, page, vaddr, dst, src, len)           \
+	do {                                                         \
+		memcpy(dst, src, len);                               \
+		if (vma->vm_flags & VM_EXEC)                         \
+			sync_icache_dcache(page);                    \
+	} while (0)
+
+#define copy_from_user_page(vma, page, vaddr, dst, src, len)         \
+	memcpy(dst, src, len)
+
+#endif /* __ASM_CACHEFLUSH_H */
diff --git a/arch/openrisc/include/asm/pgtable.h b/arch/openrisc/include/asm/pgtable.h
index 47eae2f78d2d..471821e4e810 100644
--- a/arch/openrisc/include/asm/pgtable.h
+++ b/arch/openrisc/include/asm/pgtable.h
@@ -414,15 +414,19 @@ static inline void pmd_set(pmd_t *pmdp, pte_t *ptep)
 
 extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* defined in head.S */
 
-/*
- * or32 doesn't have any external MMU info: the kernel page
- * tables contain all the necessary information.
- *
- * Actually I am not sure on what this could be used for.
- */
+static inline void update_tlb(struct vm_area_struct *vma,
+	unsigned long address, pte_t *pte)
+{
+}
+
+extern void update_cache(struct vm_area_struct *vma,
+	unsigned long address, pte_t *pte);
+
 static inline void update_mmu_cache(struct vm_area_struct *vma,
 	unsigned long address, pte_t *pte)
 {
+	update_tlb(vma, address, pte);
+	update_cache(vma, address, pte);
 }
 
 /* __PHX__ FIXME, SWAP, this probably doesn't work */
diff --git a/arch/openrisc/kernel/smp.c b/arch/openrisc/kernel/smp.c
index 685b4934fa39..4763b8b9161e 100644
--- a/arch/openrisc/kernel/smp.c
+++ b/arch/openrisc/kernel/smp.c
@@ -18,6 +18,7 @@
 #include <asm/cpuinfo.h>
 #include <asm/mmu_context.h>
 #include <asm/tlbflush.h>
+#include <asm/cacheflush.h>
 #include <asm/time.h>
 
 static void (*smp_cross_call)(const struct cpumask *, unsigned int);
@@ -239,3 +240,17 @@ void flush_tlb_range(struct vm_area_struct *vma,
 {
 	on_each_cpu(ipi_flush_tlb_all, NULL, 1);
 }
+
+/* Instruction cache invalidate - performed on each cpu */
+static void ipi_icache_page_inv(void *arg)
+{
+	struct page *page = arg;
+
+	local_icache_page_inv(page);
+}
+
+void smp_icache_page_inv(struct page *page)
+{
+	on_each_cpu(ipi_icache_page_inv, page, 1);
+}
+EXPORT_SYMBOL(smp_icache_page_inv);
diff --git a/arch/openrisc/mm/Makefile b/arch/openrisc/mm/Makefile
index 324ba2634529..a31b2a42e966 100644
--- a/arch/openrisc/mm/Makefile
+++ b/arch/openrisc/mm/Makefile
@@ -2,4 +2,4 @@
 # Makefile for the linux openrisc-specific parts of the memory manager.
 #
 
-obj-y	:= fault.o tlb.o init.o ioremap.o
+obj-y	:= fault.o cache.o tlb.o init.o ioremap.o
diff --git a/arch/openrisc/mm/cache.c b/arch/openrisc/mm/cache.c
new file mode 100644
index 000000000000..b747bf1fc1b6
--- /dev/null
+++ b/arch/openrisc/mm/cache.c
@@ -0,0 +1,61 @@
+/*
+ * OpenRISC cache.c
+ *
+ * Linux architectural port borrowing liberally from similar works of
+ * others.  All original copyrights apply as per the original source
+ * declaration.
+ *
+ * Modifications for the OpenRISC architecture:
+ * Copyright (C) 2015 Jan Henrik Weinstock <jan.weinstock@rwth-aachen.de>
+ *
+ *      This program is free software; you can redistribute it and/or
+ *      modify it under the terms of the GNU General Public License
+ *      as published by the Free Software Foundation; either version
+ *      2 of the License, or (at your option) any later version.
+ */
+
+#include <asm/spr.h>
+#include <asm/spr_defs.h>
+#include <asm/cache.h>
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
+
+static void cache_loop(struct page *page, const unsigned int reg)
+{
+	unsigned long paddr = page_to_pfn(page) << PAGE_SHIFT;
+	unsigned long line = paddr & ~(L1_CACHE_BYTES - 1);
+
+	while (line < paddr + PAGE_SIZE) {
+		mtspr(reg, line);
+		line += L1_CACHE_BYTES;
+	}
+}
+
+void local_dcache_page_flush(struct page *page)
+{
+	cache_loop(page, SPR_DCBFR);
+}
+EXPORT_SYMBOL(local_dcache_page_flush);
+
+void local_icache_page_inv(struct page *page)
+{
+	cache_loop(page, SPR_ICBIR);
+}
+EXPORT_SYMBOL(local_icache_page_inv);
+
+void update_cache(struct vm_area_struct *vma, unsigned long address,
+	pte_t *pte)
+{
+	unsigned long pfn = pte_val(*pte) >> PAGE_SHIFT;
+	struct page *page = pfn_to_page(pfn);
+	int dirty = !test_and_set_bit(PG_dc_clean, &page->flags);
+
+	/*
+	 * Since icaches do not snoop for updated data on OpenRISC, we
+	 * must write back and invalidate any dirty pages manually. We
+	 * can skip data pages, since they will not end up in icaches.
+	 */
+	if ((vma->vm_flags & VM_EXEC) && dirty)
+		sync_icache_dcache(page);
+}
+
-- 
2.13.5

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#1729921 — [PATCH v2 11/14] openrisc: add simple_smp dts and defconfig for simulators

From	Stafford Horne <shorne@gmail.com>
Date	2017-09-10 09:00 +0200
Subject	[PATCH v2 11/14] openrisc: add simple_smp dts and defconfig for simulators
Message-ID	<uo4nM-8oU-5@gated-at.bofh.it>
In reply to	#1729919

From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>

Simple enough to be compatible with simulation environments,
such as verilated systems, QEMU and other targets supporting OpenRISC
SMP.  This also supports our base FPGA SoC's if the cpu frequency is
upped to 50Mhz.

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
[shorne@gmail.com: Added defconfig]
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
Changes since v1
 - Use openrisc, prefix for ompic
 - Add stdout-path
 - Remove @interrupt cells

 arch/openrisc/boot/dts/simple_smp.dts      | 58 ++++++++++++++++++++++++++
 arch/openrisc/configs/simple_smp_defconfig | 66 ++++++++++++++++++++++++++++++
 2 files changed, 124 insertions(+)
 create mode 100644 arch/openrisc/boot/dts/simple_smp.dts
 create mode 100644 arch/openrisc/configs/simple_smp_defconfig

diff --git a/arch/openrisc/boot/dts/simple_smp.dts b/arch/openrisc/boot/dts/simple_smp.dts
new file mode 100644
index 000000000000..2d367f23c976
--- /dev/null
+++ b/arch/openrisc/boot/dts/simple_smp.dts
@@ -0,0 +1,58 @@
+/dts-v1/;
+/ {
+	compatible = "opencores,or1ksim";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&pic>;
+
+	chosen {
+		bootargs = "console=uart,mmio,0x90000000,115200";
+		stdout-path = &serial0;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x00000000 0x02000000>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		cpu@0 {
+			compatible = "opencores,or1200-rtlsvn481";
+			reg = <0>;
+			clock-frequency = <20000000>;
+		};
+		cpu@1 {
+			compatible = "opencores,or1200-rtlsvn481";
+			reg = <1>;
+			clock-frequency = <20000000>;
+		};
+	};
+
+	ompic: ompic {
+		compatible = "openrisc,ompic";
+		reg = <0x98000000 16>;
+		interrupt-controller;
+		interrupts = <1>;
+	};
+
+	/*
+	 * OR1K PIC is built into CPU and accessed via special purpose
+	 * registers.  It is not addressable and, hence, has no 'reg'
+	 * property.
+	 */
+	pic: pic {
+		compatible = "opencores,or1k-pic-level";
+		#interrupt-cells = <1>;
+		interrupt-controller;
+	};
+
+	serial0: serial@90000000 {
+		compatible = "opencores,uart16550-rtlsvn105", "ns16550a";
+		reg = <0x90000000 0x100>;
+		interrupts = <2>;
+		clock-frequency = <20000000>;
+	};
+
+};
diff --git a/arch/openrisc/configs/simple_smp_defconfig b/arch/openrisc/configs/simple_smp_defconfig
new file mode 100644
index 000000000000..b6e3c7e158e7
--- /dev/null
+++ b/arch/openrisc/configs/simple_smp_defconfig
@@ -0,0 +1,66 @@
+CONFIG_CROSS_COMPILE="or1k-linux-"
+CONFIG_LOCALVERSION="-simple-smp"
+CONFIG_NO_HZ=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_RD_GZIP is not set
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_XZ is not set
+# CONFIG_RD_LZO is not set
+# CONFIG_RD_LZ4 is not set
+CONFIG_EXPERT=y
+# CONFIG_KALLSYMS is not set
+# CONFIG_EPOLL is not set
+# CONFIG_TIMERFD is not set
+# CONFIG_EVENTFD is not set
+# CONFIG_AIO is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLOB=y
+CONFIG_MODULES=y
+# CONFIG_BLOCK is not set
+CONFIG_OPENRISC_BUILTIN_DTB="simple_smp"
+CONFIG_SMP=y
+CONFIG_HZ_100=y
+CONFIG_OPENRISC_HAVE_SHADOW_GPRS=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+CONFIG_TCP_CONG_ADVANCED=y
+# CONFIG_TCP_CONG_BIC is not set
+# CONFIG_TCP_CONG_CUBIC is not set
+# CONFIG_TCP_CONG_WESTWOOD is not set
+# CONFIG_TCP_CONG_HTCP is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FW_LOADER is not set
+CONFIG_NETDEVICES=y
+CONFIG_ETHOC=y
+CONFIG_MICREL_PHY=y
+# CONFIG_WLAN is not set
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_TMPFS=y
+CONFIG_NFS_FS=y
+CONFIG_XZ_DEC=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+# CONFIG_RCU_TRACE is not set
-- 
2.13.5

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#1729922 — [PATCH v2 09/14] openrisc: sleep instead of spin on secondary wait

From	Stafford Horne <shorne@gmail.com>
Date	2017-09-10 09:00 +0200
Subject	[PATCH v2 09/14] openrisc: sleep instead of spin on secondary wait
Message-ID	<uo4nM-8oU-9@gated-at.bofh.it>
In reply to	#1729919

Currently we do a spin on secondary cpus when waiting to boot.  This
theoretically causes issues with power consumption and does cause issues
with qemu cycle burning (it starves cpu 0 from actually being able to
boot.)

This change puts each secondary cpu to sleep if they have a power
management unit, then signals them to wake via IPI when its time to boot.
If the cpus have no power management unit they will loop as before.

Note: The wakeup IPI requires a special interrupt handler as on secondary
cpu's the interrupt infrastructure is not yet established.  This
interrupt handler is set and reset by updating SPR_EVBAR.

Signed-off-by: Stafford Horne <shorne@gmail.com>
---

Changes since v1
 - Check if power management exists before sleeping

 arch/openrisc/kernel/head.S | 51 +++++++++++++++++++++++++++++++++++++++++++--
 arch/openrisc/kernel/smp.c  |  5 +++++
 2 files changed, 54 insertions(+), 2 deletions(-)

diff --git a/arch/openrisc/kernel/head.S b/arch/openrisc/kernel/head.S
index a9972dc103f8..fb02b2a1d6f2 100644
--- a/arch/openrisc/kernel/head.S
+++ b/arch/openrisc/kernel/head.S
@@ -712,9 +712,45 @@ _flush_tlb:
 
 #ifdef CONFIG_SMP
 secondary_wait:
+	/* Doze the cpu until we are asked to run */
+	/* If we dont have power management skip doze */
+	l.mfspr r25,r0,SPR_UPR
+	l.andi  r25,r25,SPR_UPR_PMP
+	l.sfeq  r25,r0
+	l.bf	secondary_check_release
+	 l.nop
+
+	/* Setup special secondary exception handler */
+	LOAD_SYMBOL_2_GPR(r3, _secondary_evbar)
+	tophys(r25,r3)
+	l.mtspr	r0,r25,SPR_EVBAR
+
+	/* Enable Interrupts */
+	l.mfspr	r25,r0,SPR_SR
+	l.ori	r25,r25,SPR_SR_IEE
+	l.mtspr	r0,r25,SPR_SR
+
+	/* Unmask interrupts interrupts */
+	l.mfspr r25,r0,SPR_PICMR
+	l.ori   r25,r25,0xffff
+	l.mtspr	r0,r25,SPR_PICMR
+
+	/* Doze */
+	l.mfspr r25,r0,SPR_PMR
+	LOAD_SYMBOL_2_GPR(r3, SPR_PMR_DME)
+	l.or    r25,r25,r3
+	l.mtspr r0,r25,SPR_PMR
+
+	/* Wakeup - Restore exception handler */
+	l.mtspr	r0,r0,SPR_EVBAR
+
+secondary_check_release:
+	/*
+	 * Check if we actually got the release signal, if not go-back to
+	 * sleep.
+	 */
 	l.mfspr	r25,r0,SPR_COREID
-	l.movhi	r3,hi(secondary_release)
-	l.ori	r3,r3,lo(secondary_release)
+	LOAD_SYMBOL_2_GPR(r3, secondary_release)
 	tophys(r4, r3)
 	l.lwz	r3,0(r4)
 	l.sfeq	r25,r3
@@ -1663,6 +1699,17 @@ ENTRY(_early_uart_init)
 	l.jr	r9
 	l.nop
 
+	.align	0x1000
+	.global _secondary_evbar
+_secondary_evbar:
+
+	.space 0x800
+	/* Just disable interrupts and Return */
+	l.ori	r3,r0,SPR_SR_SM
+	l.mtspr	r0,r3,SPR_ESR_BASE
+	l.rfe
+
+
 	.section .rodata
 _string_unhandled_exception:
 	.string "\n\rRunarunaround: Unhandled exception 0x\0"
diff --git a/arch/openrisc/kernel/smp.c b/arch/openrisc/kernel/smp.c
index 154c94a0cfbc..685b4934fa39 100644
--- a/arch/openrisc/kernel/smp.c
+++ b/arch/openrisc/kernel/smp.c
@@ -26,6 +26,7 @@ unsigned long secondary_release = -1;
 struct thread_info *secondary_thread_info;
 
 enum ipi_msg_type {
+	IPI_WAKEUP,
 	IPI_RESCHEDULE,
 	IPI_CALL_FUNC,
 	IPI_CALL_FUNC_SINGLE,
@@ -42,6 +43,7 @@ static void boot_secondary(unsigned int cpu, struct task_struct *idle)
 	spin_lock(&boot_lock);
 
 	secondary_release = cpu;
+	smp_cross_call(cpumask_of(cpu), IPI_WAKEUP);
 
 	/*
 	 * now the secondary core is starting up let it run its
@@ -140,6 +142,9 @@ void handle_IPI(unsigned int ipi_msg)
 	unsigned int cpu = smp_processor_id();
 
 	switch (ipi_msg) {
+	case IPI_WAKEUP:
+		break;
+
 	case IPI_RESCHEDULE:
 		scheduler_ipi();
 		break;
-- 
2.13.5

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#1729923 — [PATCH v2 13/14] openrisc: enable LOCKDEP_SUPPORT and irqflags tracing

From	Stafford Horne <shorne@gmail.com>
Date	2017-09-10 09:00 +0200
Subject	[PATCH v2 13/14] openrisc: enable LOCKDEP_SUPPORT and irqflags tracing
Message-ID	<uo4nM-8oU-15@gated-at.bofh.it>
In reply to	#1729919

Lockdep is needed for proving the spinlocks and rwlocks work fine on our
platform.  It also requires calling the trace_hardirqs_off() and
trace_hardirqs_on() pair of routines when entering and exiting an
interrupt.

For OpenRISC the interrupt stack frame does not support frame pointers,
so to call trace_hardirqs_on() and trace_hardirqs_off() here the macro's
build up a stack frame each time.

There is one necessary small change in _sys_call_handler to move
interrupt enabling later so they can get re-enabled during syscall
restart. This was done to fix lockdep warnings that are now possible due
to this
patch.

Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 arch/openrisc/Kconfig        |  3 ++
 arch/openrisc/kernel/entry.S | 74 ++++++++++++++++++++++++++++++++++++++++++--
 2 files changed, 74 insertions(+), 3 deletions(-)

diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index 399f55e82dcb..f8cfb3ba9e89 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -64,6 +64,9 @@ config GENERIC_CSUM
 config STACKTRACE_SUPPORT
 	def_bool y
 
+config LOCKDEP_SUPPORT
+	def_bool  y
+
 source "init/Kconfig"
 
 source "kernel/Kconfig.freezer"
diff --git a/arch/openrisc/kernel/entry.S b/arch/openrisc/kernel/entry.S
index 1b7160c79646..690d55272ba6 100644
--- a/arch/openrisc/kernel/entry.S
+++ b/arch/openrisc/kernel/entry.S
@@ -42,6 +42,61 @@
 
 /* =========================================================[ macros ]=== */
 
+#ifdef CONFIG_TRACE_IRQFLAGS
+/*
+ * Trace irq on/off creating a stack frame.
+ */
+#define TRACE_IRQS_OP(trace_op)					\
+	l.sw 	-8(r1),r2	/* store frame pointer */		;\
+	l.sw	-4(r1),r9	/* store return address */		;\
+	l.addi	r2,r1,0		/* move sp to fp */			;\
+	l.jal	trace_op						;\
+	 l.addi	r1,r1,-8						;\
+	l.ori	r1,r2,0		/* restore sp */			;\
+	l.lwz	r9,-4(r1)	/* restore return address */		;\
+	l.lwz	r2,-8(r1)	/* restore fp */			;\
+/*
+ * Trace irq on/off and save registers we need that would otherwise be
+ * clobbered.
+ */
+#define TRACE_IRQS_SAVE(t1,trace_op)					\
+	l.sw	-12(r1),t1	/* save extra reg */			;\
+	l.sw 	-8(r1),r2	/* store frame pointer */		;\
+	l.sw	-4(r1),r9	/* store return address */		;\
+	l.addi	r2,r1,0		/* move sp to fp */			;\
+	l.jal	trace_op						;\
+	 l.addi	r1,r1,-12						;\
+	l.ori	r1,r2,0		/* restore sp */			;\
+	l.lwz	r9,-4(r1)	/* restore return address */		;\
+	l.lwz	r2,-8(r1)	/* restore fp */			;\
+	l.lwz	t1,-12(r1)	/* restore extra reg */
+
+#define TRACE_IRQS_OFF	TRACE_IRQS_OP(trace_hardirqs_off)
+#define TRACE_IRQS_ON	TRACE_IRQS_OP(trace_hardirqs_on)
+#define TRACE_IRQS_ON_SYSCALL						\
+	TRACE_IRQS_SAVE(r10,trace_hardirqs_on)				;\
+	l.lwz	r3,PT_GPR3(r1)						;\
+	l.lwz	r4,PT_GPR4(r1)						;\
+	l.lwz	r5,PT_GPR5(r1)						;\
+	l.lwz	r6,PT_GPR6(r1)						;\
+	l.lwz	r7,PT_GPR7(r1)						;\
+	l.lwz	r8,PT_GPR8(r1)						;\
+	l.lwz	r11,PT_GPR11(r1)
+#define TRACE_IRQS_OFF_ENTRY						\
+	l.lwz	r5,PT_SR(r1)						;\
+	l.andi	r3,r5,(SPR_SR_IEE|SPR_SR_TEE)				;\
+	l.sfeq	r5,r0		/* skip trace if irqs were already off */;\
+	l.bf	1f							;\
+	 l.nop								;\
+	TRACE_IRQS_SAVE(r4,trace_hardirqs_off)				;\
+1:
+#else
+#define TRACE_IRQS_OFF
+#define TRACE_IRQS_ON
+#define TRACE_IRQS_OFF_ENTRY
+#define TRACE_IRQS_ON_SYSCALL
+#endif
+
 /*
  * We need to disable interrupts at beginning of RESTORE_ALL
  * since interrupt might come in after we've loaded EPC return address
@@ -124,6 +179,7 @@ handler:							;\
 	/* r30 already save */					;\
 /*        l.sw    PT_GPR30(r1),r30*/					;\
 	l.sw    PT_GPR31(r1),r31					;\
+	TRACE_IRQS_OFF_ENTRY						;\
 	/* Store -1 in orig_gpr11 for non-syscall exceptions */	;\
 	l.addi	r30,r0,-1					;\
 	l.sw	PT_ORIG_GPR11(r1),r30
@@ -557,9 +613,6 @@ _string_syscall_return:
 	.align 4
 
 ENTRY(_sys_call_handler)
-	/* syscalls run with interrupts enabled */
-	ENABLE_INTERRUPTS(r29)		// enable interrupts, r29 is temp
-
 	/* r1, EPCR, ESR a already saved */
 	l.sw	PT_GPR2(r1),r2
 	/* r3-r8 must be saved because syscall restart relies
@@ -597,6 +650,10 @@ ENTRY(_sys_call_handler)
 /*	l.sw    PT_GPR30(r1),r30 */
 
 _syscall_check_trace_enter:
+	/* syscalls run with interrupts enabled */
+	TRACE_IRQS_ON_SYSCALL
+	ENABLE_INTERRUPTS(r29)		// enable interrupts, r29 is temp
+
 	/* If TIF_SYSCALL_TRACE is set, then we want to do syscall tracing */
 	l.lwz	r30,TI_FLAGS(r10)
 	l.andi	r30,r30,_TIF_SYSCALL_TRACE
@@ -657,6 +714,7 @@ _syscall_check_trace_leave:
 _syscall_check_work:
 	/* Here we need to disable interrupts */
 	DISABLE_INTERRUPTS(r27,r29)
+	TRACE_IRQS_OFF
 	l.lwz	r30,TI_FLAGS(r10)
 	l.andi	r30,r30,_TIF_WORK_MASK
 	l.sfne	r30,r0
@@ -871,6 +929,7 @@ UNHANDLED_EXCEPTION(_vector_0x1f00,0x1f00)
 
 _resume_userspace:
 	DISABLE_INTERRUPTS(r3,r4)
+	TRACE_IRQS_OFF
 	l.lwz	r4,TI_FLAGS(r10)
 	l.andi	r13,r4,_TIF_WORK_MASK
 	l.sfeqi	r13,0
@@ -909,6 +968,15 @@ _work_pending:
 	 l.lwz	r8,PT_GPR8(r1)
 
 _restore_all:
+#ifdef CONFIG_TRACE_IRQFLAGS
+	l.lwz	r4,PT_SR(r1)
+	l.andi	r3,r4,(SPR_SR_IEE|SPR_SR_TEE)
+	l.sfeq	r3,r0		/* skip trace if irqs were off */
+	l.bf	skip_hardirqs_on
+	 l.nop
+	TRACE_IRQS_ON
+skip_hardirqs_on:
+#endif
 	RESTORE_ALL
 	/* This returns to userspace code */
 
-- 
2.13.5

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#1729924 — [PATCH v2 03/14] openrisc: add 1 and 2 byte cmpxchg support

From	Stafford Horne <shorne@gmail.com>
Date	2017-09-10 09:00 +0200
Subject	[PATCH v2 03/14] openrisc: add 1 and 2 byte cmpxchg support
Message-ID	<uo4nM-8oU-13@gated-at.bofh.it>
In reply to	#1729919

OpenRISC only supports hardware instructions that perform 4 byte atomic
operations.  For enabling qrwlocks for upcoming SMP support 1 and 2 byte
implementations are needed.  To do this we leverage the 4 byte atomic
operations and shift/mask the 1 and 2 byte areas as needed.

This heavily borrows ideas and routines from sh and mips, which do
something similar.

Cc: Peter Zijlstra <peterz@infradead.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 arch/openrisc/include/asm/cmpxchg.h | 147 ++++++++++++++++++++++++++++--------
 1 file changed, 115 insertions(+), 32 deletions(-)

diff --git a/arch/openrisc/include/asm/cmpxchg.h b/arch/openrisc/include/asm/cmpxchg.h
index f0a5d8b844d6..d29f7db53906 100644
--- a/arch/openrisc/include/asm/cmpxchg.h
+++ b/arch/openrisc/include/asm/cmpxchg.h
@@ -1,32 +1,29 @@
 /*
+ * 1,2 and 4 byte cmpxchg and xchg implementations for OpenRISC.
+ *
  * Copyright (C) 2014 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
+ * Copyright (C) 2017 Stafford Horne <shorne@gmail.com>
  *
  * This file is licensed under the terms of the GNU General Public License
  * version 2.  This program is licensed "as is" without any warranty of any
  * kind, whether express or implied.
+ *
+ * Note:
+ * The portable implementations of 1 and 2 byte xchg and cmpxchg using a 4
+ * byte cmpxchg is sourced heavily from the sh and mips implementations.
  */
 
 #ifndef __ASM_OPENRISC_CMPXCHG_H
 #define __ASM_OPENRISC_CMPXCHG_H
 
 #include  <linux/types.h>
-
-/*
- * This function doesn't exist, so you'll get a linker error
- * if something tries to do an invalid cmpxchg().
- */
-extern void __cmpxchg_called_with_bad_pointer(void);
+#include  <linux/bitops.h>
 
 #define __HAVE_ARCH_CMPXCHG 1
 
-static inline unsigned long
-__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
+static inline unsigned long cmpxchg_u32(volatile void *ptr,
+		unsigned long old, unsigned long new)
 {
-	if (size != 4) {
-		__cmpxchg_called_with_bad_pointer();
-		return old;
-	}
-
 	__asm__ __volatile__(
 		"1:	l.lwa %0, 0(%1)		\n"
 		"	l.sfeq %0, %2		\n"
@@ -43,6 +40,97 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
 	return old;
 }
 
+static inline unsigned long xchg_u32(volatile void *ptr,
+		unsigned long val)
+{
+	__asm__ __volatile__(
+		"1:	l.lwa %0, 0(%1)		\n"
+		"	l.swa 0(%1), %2		\n"
+		"	l.bnf 1b		\n"
+		"	 l.nop			\n"
+		: "=&r"(val)
+		: "r"(ptr), "r"(val)
+		: "cc", "memory");
+
+	return val;
+}
+
+static inline u32 cmpxchg_small(volatile void *ptr, u32 old, u32 new,
+				int size)
+{
+	int off = (unsigned long)ptr % sizeof(u32);
+	volatile u32 *p = ptr - off;
+#ifdef __BIG_ENDIAN
+	int bitoff = (sizeof(u32) - size - off) * BITS_PER_BYTE;
+#else
+	int bitoff = off * BITS_PER_BYTE;
+#endif
+	u32 bitmask = ((0x1 << size * BITS_PER_BYTE) - 1) << bitoff;
+	u32 load32, old32, new32;
+	u32 ret;
+
+	load32 = READ_ONCE(*p);
+
+	while (true) {
+		ret = (load32 & bitmask) >> bitoff;
+		if (old != ret)
+			return ret;
+
+		old32 = (load32 & ~bitmask) | (old << bitoff);
+		new32 = (load32 & ~bitmask) | (new << bitoff);
+
+		/* Do 32 bit cmpxchg */
+		load32 = cmpxchg_u32(p, old32, new32);
+		if (load32 == old32)
+			return old;
+	}
+}
+
+/* xchg */
+
+static inline u32 xchg_small(volatile void *ptr, u32 x, int size)
+{
+	int off = (unsigned long)ptr % sizeof(u32);
+	volatile u32 *p = ptr - off;
+#ifdef __BIG_ENDIAN
+	int bitoff = (sizeof(u32) - size - off) * BITS_PER_BYTE;
+#else
+	int bitoff = off * BITS_PER_BYTE;
+#endif
+	u32 bitmask = ((0x1 << size * BITS_PER_BYTE) - 1) << bitoff;
+	u32 oldv, newv;
+	u32 ret;
+
+	do {
+		oldv = READ_ONCE(*p);
+		ret = (oldv & bitmask) >> bitoff;
+		newv = (oldv & ~bitmask) | (x << bitoff);
+	} while (cmpxchg_u32(p, oldv, newv) != oldv);
+
+	return ret;
+}
+
+/*
+ * This function doesn't exist, so you'll get a linker error
+ * if something tries to do an invalid cmpxchg().
+ */
+extern unsigned long __cmpxchg_called_with_bad_pointer(void)
+	__compiletime_error("Bad argument size for cmpxchg");
+
+static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
+		unsigned long new, int size)
+{
+	switch (size) {
+	case 1:
+	case 2:
+		return cmpxchg_small(ptr, old, new, size);
+	case 4:
+		return cmpxchg_u32(ptr, old, new);
+	default:
+		return __cmpxchg_called_with_bad_pointer();
+	}
+}
+
 #define cmpxchg(ptr, o, n)						\
 	({								\
 		(__typeof__(*(ptr))) __cmpxchg((ptr),			\
@@ -55,32 +143,27 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
  * This function doesn't exist, so you'll get a linker error if
  * something tries to do an invalidly-sized xchg().
  */
-extern void __xchg_called_with_bad_pointer(void);
+extern unsigned long __xchg_called_with_bad_pointer(void)
+	__compiletime_error("Bad argument size for xchg");
 
-static inline unsigned long __xchg(unsigned long val, volatile void *ptr,
-				   int size)
+static inline unsigned long __xchg(volatile void *ptr, unsigned long with,
+		int size)
 {
-	if (size != 4) {
-		__xchg_called_with_bad_pointer();
-		return val;
+	switch (size) {
+	case 1:
+	case 2:
+		return xchg_small(ptr, with, size);
+	case 4:
+		return xchg_u32(ptr, with);
+	default:
+		return __xchg_called_with_bad_pointer();
 	}
-
-	__asm__ __volatile__(
-		"1:	l.lwa %0, 0(%1)		\n"
-		"	l.swa 0(%1), %2		\n"
-		"	l.bnf 1b		\n"
-		"	 l.nop			\n"
-		: "=&r"(val)
-		: "r"(ptr), "r"(val)
-		: "cc", "memory");
-
-	return val;
 }
 
 #define xchg(ptr, with) 						\
 	({								\
-		(__typeof__(*(ptr))) __xchg((unsigned long)(with),	\
-					    (ptr),			\
+		(__typeof__(*(ptr))) __xchg((ptr),			\
+					    (unsigned long)(with),	\
 					    sizeof(*(ptr)));		\
 	})
 
-- 
2.13.5

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#1729926 — [PATCH v2 02/14] openrisc: define CPU_BIG_ENDIAN as true

From	Stafford Horne <shorne@gmail.com>
Date	2017-09-10 09:00 +0200
Subject	[PATCH v2 02/14] openrisc: define CPU_BIG_ENDIAN as true
Message-ID	<uo4nM-8oU-23@gated-at.bofh.it>
In reply to	#1729919

While working on SMP for OpenRISC I found this is needed for qrwlocks to
work correctly.  OpenRISC is big endian so this should have been here
already.

Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 arch/openrisc/Kconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index ee34d94f7aa2..356dd67a86ea 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -29,6 +29,9 @@ config OPENRISC
 	select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
 	select NO_BOOTMEM
 
+config CPU_BIG_ENDIAN
+	def_bool y
+
 config MMU
 	def_bool y
 
-- 
2.13.5

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#1729927 — [PATCH v2 12/14] openrisc: support framepointers and STACKTRACE_SUPPORT

From	Stafford Horne <shorne@gmail.com>
Date	2017-09-10 09:00 +0200
Subject	[PATCH v2 12/14] openrisc: support framepointers and STACKTRACE_SUPPORT
Message-ID	<uo4nM-8oU-29@gated-at.bofh.it>
In reply to	#1729919

For lockdep support a reliable stack trace mechanism is needed.  This
patch adds support in OpenRISC for the stacktrace framework, implemented
by a simple unwinder api.  The unwinder api supports both framepointer
and basic stack tracing.

The unwinder is now used to replace the stack_dump() implementation as
well. The new traces are inline with other architectures trace format:

 Call trace:
 [<c0004448>] show_stack+0x3c/0x58
 [<c031c940>] dump_stack+0xa8/0xe4
 [<c0008104>] __cpu_up+0x64/0x130
 [<c000d268>] bringup_cpu+0x3c/0x178
 [<c000d038>] cpuhp_invoke_callback+0xa8/0x1fc
 [<c000d680>] cpuhp_up_callbacks+0x44/0x14c
 [<c000e400>] cpu_up+0x14c/0x1bc
 [<c041da60>] smp_init+0x104/0x15c
 [<c033843c>] ? kernel_init+0x0/0x140
 [<c0415e04>] kernel_init_freeable+0xbc/0x25c
 [<c033843c>] ? kernel_init+0x0/0x140
 [<c0338458>] kernel_init+0x1c/0x140
 [<c003a174>] ? schedule_tail+0x18/0xa0
 [<c0006b80>] ret_from_fork+0x1c/0x9c

Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 arch/openrisc/Kconfig                |   4 ++
 arch/openrisc/include/asm/unwinder.h |  20 +++++++
 arch/openrisc/kernel/Makefile        |   3 +-
 arch/openrisc/kernel/stacktrace.c    |  86 ++++++++++++++++++++++++++++
 arch/openrisc/kernel/traps.c         |  54 +++---------------
 arch/openrisc/kernel/unwinder.c      | 105 +++++++++++++++++++++++++++++++++++
 6 files changed, 224 insertions(+), 48 deletions(-)
 create mode 100644 arch/openrisc/include/asm/unwinder.h
 create mode 100644 arch/openrisc/kernel/stacktrace.c
 create mode 100644 arch/openrisc/kernel/unwinder.c

diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index bfff04ae7f7d..399f55e82dcb 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -33,6 +33,7 @@ config OPENRISC
 	select ARCH_USE_QUEUED_SPINLOCKS
 	select ARCH_USE_QUEUED_RWLOCKS
 	select OMPIC if SMP
+	select ARCH_WANT_FRAME_POINTERS
 
 config CPU_BIG_ENDIAN
 	def_bool y
@@ -60,6 +61,9 @@ config TRACE_IRQFLAGS_SUPPORT
 config GENERIC_CSUM
         def_bool y
 
+config STACKTRACE_SUPPORT
+	def_bool y
+
 source "init/Kconfig"
 
 source "kernel/Kconfig.freezer"
diff --git a/arch/openrisc/include/asm/unwinder.h b/arch/openrisc/include/asm/unwinder.h
new file mode 100644
index 000000000000..165ec6f02ab8
--- /dev/null
+++ b/arch/openrisc/include/asm/unwinder.h
@@ -0,0 +1,20 @@
+/*
+ * OpenRISC unwinder.h
+ *
+ * Architecture API for unwinding stacks.
+ *
+ * Copyright (C) 2017 Stafford Horne <shorne@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifndef __ASM_OPENRISC_UNWINDER_H
+#define __ASM_OPENRISC_UNWINDER_H
+
+void unwind_stack(void *data, unsigned long *stack,
+		  void (*trace)(void *data, unsigned long addr,
+				int reliable));
+
+#endif /* __ASM_OPENRISC_UNWINDER_H */
diff --git a/arch/openrisc/kernel/Makefile b/arch/openrisc/kernel/Makefile
index 7d94643c878d..b4b51a07016a 100644
--- a/arch/openrisc/kernel/Makefile
+++ b/arch/openrisc/kernel/Makefile
@@ -6,9 +6,10 @@ extra-y	:= head.o vmlinux.lds
 
 obj-y	:= setup.o or32_ksyms.o process.o dma.o \
 	   traps.o time.o irq.o entry.o ptrace.o signal.o \
-	   sys_call_table.o
+	   sys_call_table.o unwinder.o
 
 obj-$(CONFIG_SMP)		+= smp.o
+obj-$(CONFIG_STACKTRACE)	+= stacktrace.o
 obj-$(CONFIG_MODULES)		+= module.o
 obj-$(CONFIG_OF)		+= prom.o
 
diff --git a/arch/openrisc/kernel/stacktrace.c b/arch/openrisc/kernel/stacktrace.c
new file mode 100644
index 000000000000..43f140a28bc7
--- /dev/null
+++ b/arch/openrisc/kernel/stacktrace.c
@@ -0,0 +1,86 @@
+/*
+ * Stack trace utility for OpenRISC
+ *
+ * Copyright (C) 2017 Stafford Horne <shorne@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ *
+ * Losely based on work from sh and powerpc.
+ */
+
+#include <linux/export.h>
+#include <linux/sched.h>
+#include <linux/sched/debug.h>
+#include <linux/stacktrace.h>
+
+#include <asm/processor.h>
+#include <asm/unwinder.h>
+
+/*
+ * Save stack-backtrace addresses into a stack_trace buffer.
+ */
+static void
+save_stack_address(void *data, unsigned long addr, int reliable)
+{
+	struct stack_trace *trace = data;
+
+	if (!reliable)
+		return;
+
+	if (trace->skip > 0) {
+		trace->skip--;
+		return;
+	}
+
+	if (trace->nr_entries < trace->max_entries)
+		trace->entries[trace->nr_entries++] = addr;
+}
+
+void save_stack_trace(struct stack_trace *trace)
+{
+	unwind_stack(trace, (unsigned long *) &trace, save_stack_address);
+}
+EXPORT_SYMBOL_GPL(save_stack_trace);
+
+static void
+save_stack_address_nosched(void *data, unsigned long addr, int reliable)
+{
+	struct stack_trace *trace = (struct stack_trace *)data;
+
+	if (!reliable)
+		return;
+
+	if (in_sched_functions(addr))
+		return;
+
+	if (trace->skip > 0) {
+		trace->skip--;
+		return;
+	}
+
+	if (trace->nr_entries < trace->max_entries)
+		trace->entries[trace->nr_entries++] = addr;
+}
+
+void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
+{
+	unsigned long *sp = NULL;
+
+	if (tsk == current)
+		sp = (unsigned long *) &sp;
+	else
+		sp = (unsigned long *) KSTK_ESP(tsk);
+
+	unwind_stack(trace, sp, save_stack_address_nosched);
+}
+EXPORT_SYMBOL_GPL(save_stack_trace_tsk);
+
+void
+save_stack_trace_regs(struct pt_regs *regs, struct stack_trace *trace)
+{
+	unwind_stack(trace, (unsigned long *) regs->sp,
+		     save_stack_address_nosched);
+}
+EXPORT_SYMBOL_GPL(save_stack_trace_regs);
diff --git a/arch/openrisc/kernel/traps.c b/arch/openrisc/kernel/traps.c
index 803e9e756f77..4085d72fa5ae 100644
--- a/arch/openrisc/kernel/traps.c
+++ b/arch/openrisc/kernel/traps.c
@@ -38,6 +38,7 @@
 #include <asm/segment.h>
 #include <asm/io.h>
 #include <asm/pgtable.h>
+#include <asm/unwinder.h>
 
 extern char _etext, _stext;
 
@@ -45,61 +46,20 @@ int kstack_depth_to_print = 0x180;
 int lwa_flag;
 unsigned long __user *lwa_addr;
 
-static inline int valid_stack_ptr(struct thread_info *tinfo, void *p)
+void print_trace(void *data, unsigned long addr, int reliable)
 {
-	return p > (void *)tinfo && p < (void *)tinfo + THREAD_SIZE - 3;
-}
-
-void show_trace(struct task_struct *task, unsigned long *stack)
-{
-	struct thread_info *context;
-	unsigned long addr;
-
-	context = (struct thread_info *)
-	    ((unsigned long)stack & (~(THREAD_SIZE - 1)));
-
-	while (valid_stack_ptr(context, stack)) {
-		addr = *stack++;
-		if (__kernel_text_address(addr)) {
-			printk(" [<%08lx>]", addr);
-			print_symbol(" %s", addr);
-			printk("\n");
-		}
-	}
-	printk(" =======================\n");
+	pr_emerg("[<%p>] %s%pS\n", (void *) addr, reliable ? "" : "? ",
+	       (void *) addr);
 }
 
 /* displays a short stack trace */
 void show_stack(struct task_struct *task, unsigned long *esp)
 {
-	unsigned long addr, *stack;
-	int i;
-
 	if (esp == NULL)
 		esp = (unsigned long *)&esp;
 
-	stack = esp;
-
-	printk("Stack dump [0x%08lx]:\n", (unsigned long)esp);
-	for (i = 0; i < kstack_depth_to_print; i++) {
-		if (kstack_end(stack))
-			break;
-		if (__get_user(addr, stack)) {
-			/* This message matches "failing address" marked
-			   s390 in ksymoops, so lines containing it will
-			   not be filtered out by ksymoops.  */
-			printk("Failing address 0x%lx\n", (unsigned long)stack);
-			break;
-		}
-		stack++;
-
-		printk("sp + %02d: 0x%08lx\n", i * 4, addr);
-	}
-	printk("\n");
-
-	show_trace(task, esp);
-
-	return;
+	pr_emerg("Call trace:\n");
+	unwind_stack(NULL, esp, print_trace);
 }
 
 void show_trace_task(struct task_struct *tsk)
@@ -115,7 +75,7 @@ void show_registers(struct pt_regs *regs)
 	int in_kernel = 1;
 	unsigned long esp;
 
-	esp = (unsigned long)(&regs->sp);
+	esp = (unsigned long)(regs->sp);
 	if (user_mode(regs))
 		in_kernel = 0;
 
diff --git a/arch/openrisc/kernel/unwinder.c b/arch/openrisc/kernel/unwinder.c
new file mode 100644
index 000000000000..8ae15c2c1845
--- /dev/null
+++ b/arch/openrisc/kernel/unwinder.c
@@ -0,0 +1,105 @@
+/*
+ * OpenRISC unwinder.c
+ *
+ * Reusable arch specific api for unwinding stacks.
+ *
+ * Copyright (C) 2017 Stafford Horne <shorne@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/sched/task_stack.h>
+#include <linux/kernel.h>
+
+#include <asm/unwinder.h>
+
+#ifdef CONFIG_FRAME_POINTER
+struct or1k_frameinfo {
+	unsigned long *fp;
+	unsigned long ra;
+	unsigned long top;
+};
+
+/*
+ * Verify a frameinfo structure.  The return address should be a valid text
+ * address.  The frame pointer may be null if its the last frame, otherwise
+ * the frame pointer should point to a location in the stack after the the
+ * top of the next frame up.
+ */
+static inline int or1k_frameinfo_valid(struct or1k_frameinfo *frameinfo)
+{
+	return (frameinfo->fp == NULL ||
+		(!kstack_end(frameinfo->fp) &&
+		 frameinfo->fp > &frameinfo->top)) &&
+	       __kernel_text_address(frameinfo->ra);
+}
+
+/*
+ * Create a stack trace doing scanning which is frame pointer aware. We can
+ * get reliable stack traces by matching the previously found frame
+ * pointer with the top of the stack address every time we find a valid
+ * or1k_frameinfo.
+ *
+ * Ideally the stack parameter will be passed as FP, but it can not be
+ * guaranteed.  Therefore we scan each address looking for the first sign
+ * of a return address.
+ *
+ * The OpenRISC stack frame looks something like the following.  The
+ * location SP is held in r1 and location FP is held in r2 when frame pointers
+ * enabled.
+ *
+ * SP   -> (top of stack)
+ *      -  (callee saved registers)
+ *      -  (local variables)
+ * FP-8 -> previous FP             \
+ * FP-4 -> return address          |- or1k_frameinfo
+ * FP   -> (previous top of stack) /
+ */
+void unwind_stack(void *data, unsigned long *stack,
+		  void (*trace)(void *data, unsigned long addr, int reliable))
+{
+	unsigned long *next_fp = NULL;
+	struct or1k_frameinfo *frameinfo = NULL;
+	int reliable = 0;
+
+	while (!kstack_end(stack)) {
+		frameinfo = container_of(stack,
+					 struct or1k_frameinfo,
+					 top);
+
+		if (__kernel_text_address(frameinfo->ra)) {
+			if (or1k_frameinfo_valid(frameinfo) &&
+			    (next_fp == NULL ||
+			     next_fp == &frameinfo->top)) {
+				reliable = 1;
+				next_fp = frameinfo->fp;
+			} else
+				reliable = 0;
+
+			trace(data, frameinfo->ra, reliable);
+		}
+		stack++;
+	}
+}
+
+#else /* CONFIG_FRAME_POINTER */
+
+/*
+ * Create a stack trace by doing a simple scan treating all text addresses
+ * as return addresses.
+ */
+void unwind_stack(void *data, unsigned long *stack,
+		   void (*trace)(void *data, unsigned long addr, int reliable))
+{
+	unsigned long addr;
+
+	while (!kstack_end(stack)) {
+		addr = *stack++;
+		if (__kernel_text_address(addr))
+			trace(data, addr, 0);
+	}
+}
+#endif /* CONFIG_FRAME_POINTER */
+
-- 
2.13.5

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#1729928 — [PATCH v2 08/14] openrisc: fix initial preempt state for secondary cpu tasks

From	Stafford Horne <shorne@gmail.com>
Date	2017-09-10 09:00 +0200
Subject	[PATCH v2 08/14] openrisc: fix initial preempt state for secondary cpu tasks
Message-ID	<uo4nM-8oU-27@gated-at.bofh.it>
In reply to	#1729919

During SMP testing we were getting the below warning after booting the
secondary cpu:

[    0.060000] BUG: scheduling while atomic: swapper/1/0/0x00000000

This change follows similar patterns from other architectures to start
the schduler with preempt disabled.

Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 arch/openrisc/include/asm/thread_info.h | 2 +-
 arch/openrisc/kernel/smp.c              | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/openrisc/include/asm/thread_info.h b/arch/openrisc/include/asm/thread_info.h
index 6e619a79a401..c229aa6bb502 100644
--- a/arch/openrisc/include/asm/thread_info.h
+++ b/arch/openrisc/include/asm/thread_info.h
@@ -74,7 +74,7 @@ struct thread_info {
 	.task		= &tsk,				\
 	.flags		= 0,				\
 	.cpu		= 0,				\
-	.preempt_count	= 1,				\
+	.preempt_count	= INIT_PREEMPT_COUNT,		\
 	.addr_limit	= KERNEL_DS,			\
 	.ksp            = 0,                            \
 }
diff --git a/arch/openrisc/kernel/smp.c b/arch/openrisc/kernel/smp.c
index fd724123229a..154c94a0cfbc 100644
--- a/arch/openrisc/kernel/smp.c
+++ b/arch/openrisc/kernel/smp.c
@@ -128,6 +128,7 @@ asmlinkage __init void secondary_start_kernel(void)
 
 	local_irq_enable();
 
+	preempt_disable();
 	/*
 	 * OK, it's off to the idle thread for us
 	 */
-- 
2.13.5

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#1729929 — [PATCH v2 01/14] openrisc: use shadow registers to save regs on exception

From	Stafford Horne <shorne@gmail.com>
Date	2017-09-10 09:00 +0200
Subject	[PATCH v2 01/14] openrisc: use shadow registers to save regs on exception
Message-ID	<uo4nM-8oU-33@gated-at.bofh.it>
In reply to	#1729919

From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>

Previously, the area between 0x0-0x100 have been used as a "scratch"
memory area to temporarily store regs during exception entry. In a
multi-core environment, this will not work.

This change is to use shadow registers for nested context.

Currently only the "critical" temp load/stores are covered, the
EMERGENCY_PRINT ones are left as is (when they are used, it's game over
anyway), they need to be handled as well in the future.

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---

Changes since v1
 - Added SMP checks in Kconfig

 arch/openrisc/Kconfig       | 11 ++++++
 arch/openrisc/kernel/head.S | 95 ++++++++++++++++++++++++++++++++-------------
 2 files changed, 80 insertions(+), 26 deletions(-)

diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index 1e95920b0737..ee34d94f7aa2 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -121,6 +121,17 @@ config OPENRISC_NO_SPR_SR_DSX
 	  Say N here if you know that your OpenRISC processor has
 	  SPR_SR_DSX bit implemented. Say Y if you are unsure.
 
+config OPENRISC_HAVE_SHADOW_GPRS
+	bool "Support for shadow gpr files" if !SMP
+	default y if SMP
+	help
+	  Say Y here if your OpenRISC processor features shadowed
+	  register files. They will in such case be used as a
+	  scratch reg storage on exception entry.
+
+	  On SMP systems, this feature is mandatory.
+	  On a unicore system it's safe to say N here if you are unsure.
+
 config CMDLINE
         string "Default kernel command string"
         default ""
diff --git a/arch/openrisc/kernel/head.S b/arch/openrisc/kernel/head.S
index 1e87913576e3..1e49895408f4 100644
--- a/arch/openrisc/kernel/head.S
+++ b/arch/openrisc/kernel/head.S
@@ -49,9 +49,31 @@
 
 /* ============================================[ tmp store locations ]=== */
 
+#define SPR_SHADOW_GPR(x)	((x) + SPR_GPR_BASE + 32)
+
 /*
  * emergency_print temporary stores
  */
+#ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS
+#define EMERGENCY_PRINT_STORE_GPR4	l.mtspr r0,r4,SPR_SHADOW_GPR(14)
+#define EMERGENCY_PRINT_LOAD_GPR4	l.mfspr r4,r0,SPR_SHADOW_GPR(14)
+
+#define EMERGENCY_PRINT_STORE_GPR5	l.mtspr r0,r5,SPR_SHADOW_GPR(15)
+#define EMERGENCY_PRINT_LOAD_GPR5	l.mfspr r5,r0,SPR_SHADOW_GPR(15)
+
+#define EMERGENCY_PRINT_STORE_GPR6	l.mtspr r0,r6,SPR_SHADOW_GPR(16)
+#define EMERGENCY_PRINT_LOAD_GPR6	l.mfspr r6,r0,SPR_SHADOW_GPR(16)
+
+#define EMERGENCY_PRINT_STORE_GPR7	l.mtspr r0,r7,SPR_SHADOW_GPR(7)
+#define EMERGENCY_PRINT_LOAD_GPR7	l.mfspr r7,r0,SPR_SHADOW_GPR(7)
+
+#define EMERGENCY_PRINT_STORE_GPR8	l.mtspr r0,r8,SPR_SHADOW_GPR(8)
+#define EMERGENCY_PRINT_LOAD_GPR8	l.mfspr r8,r0,SPR_SHADOW_GPR(8)
+
+#define EMERGENCY_PRINT_STORE_GPR9	l.mtspr r0,r9,SPR_SHADOW_GPR(9)
+#define EMERGENCY_PRINT_LOAD_GPR9	l.mfspr r9,r0,SPR_SHADOW_GPR(9)
+
+#else /* !CONFIG_OPENRISC_HAVE_SHADOW_GPRS */
 #define EMERGENCY_PRINT_STORE_GPR4	l.sw    0x20(r0),r4
 #define EMERGENCY_PRINT_LOAD_GPR4	l.lwz   r4,0x20(r0)
 
@@ -70,13 +92,28 @@
 #define EMERGENCY_PRINT_STORE_GPR9	l.sw    0x34(r0),r9
 #define EMERGENCY_PRINT_LOAD_GPR9	l.lwz   r9,0x34(r0)
 
+#endif
 
 /*
  * TLB miss handlers temorary stores
  */
-#define EXCEPTION_STORE_GPR9		l.sw    0x10(r0),r9
-#define EXCEPTION_LOAD_GPR9		l.lwz   r9,0x10(r0)
+#ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS
+#define EXCEPTION_STORE_GPR2		l.mtspr r0,r2,SPR_SHADOW_GPR(2)
+#define EXCEPTION_LOAD_GPR2		l.mfspr r2,r0,SPR_SHADOW_GPR(2)
+
+#define EXCEPTION_STORE_GPR3		l.mtspr r0,r3,SPR_SHADOW_GPR(3)
+#define EXCEPTION_LOAD_GPR3		l.mfspr r3,r0,SPR_SHADOW_GPR(3)
 
+#define EXCEPTION_STORE_GPR4		l.mtspr r0,r4,SPR_SHADOW_GPR(4)
+#define EXCEPTION_LOAD_GPR4		l.mfspr r4,r0,SPR_SHADOW_GPR(4)
+
+#define EXCEPTION_STORE_GPR5		l.mtspr r0,r5,SPR_SHADOW_GPR(5)
+#define EXCEPTION_LOAD_GPR5		l.mfspr r5,r0,SPR_SHADOW_GPR(5)
+
+#define EXCEPTION_STORE_GPR6		l.mtspr r0,r6,SPR_SHADOW_GPR(6)
+#define EXCEPTION_LOAD_GPR6		l.mfspr r6,r0,SPR_SHADOW_GPR(6)
+
+#else /* !CONFIG_OPENRISC_HAVE_SHADOW_GPRS */
 #define EXCEPTION_STORE_GPR2		l.sw    0x64(r0),r2
 #define EXCEPTION_LOAD_GPR2		l.lwz   r2,0x64(r0)
 
@@ -92,26 +129,32 @@
 #define EXCEPTION_STORE_GPR6		l.sw    0x74(r0),r6
 #define EXCEPTION_LOAD_GPR6		l.lwz   r6,0x74(r0)
 
+#endif
 
 /*
  * EXCEPTION_HANDLE temporary stores
  */
 
+#ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS
+#define EXCEPTION_T_STORE_GPR30		l.mtspr r0,r30,SPR_SHADOW_GPR(30)
+#define EXCEPTION_T_LOAD_GPR30(reg)	l.mfspr reg,r0,SPR_SHADOW_GPR(30)
+
+#define EXCEPTION_T_STORE_GPR10		l.mtspr r0,r10,SPR_SHADOW_GPR(10)
+#define EXCEPTION_T_LOAD_GPR10(reg)	l.mfspr reg,r0,SPR_SHADOW_GPR(10)
+
+#define EXCEPTION_T_STORE_SP		l.mtspr r0,r1,SPR_SHADOW_GPR(1)
+#define EXCEPTION_T_LOAD_SP(reg)	l.mfspr reg,r0,SPR_SHADOW_GPR(1)
+
+#else /* !CONFIG_OPENRISC_HAVE_SHADOW_GPRS */
 #define EXCEPTION_T_STORE_GPR30		l.sw    0x78(r0),r30
 #define EXCEPTION_T_LOAD_GPR30(reg)	l.lwz   reg,0x78(r0)
 
 #define EXCEPTION_T_STORE_GPR10		l.sw    0x7c(r0),r10
 #define EXCEPTION_T_LOAD_GPR10(reg)	l.lwz   reg,0x7c(r0)
 
-#define EXCEPTION_T_STORE_SP		l.sw	0x80(r0),r1
+#define EXCEPTION_T_STORE_SP		l.sw    0x80(r0),r1
 #define EXCEPTION_T_LOAD_SP(reg)	l.lwz   reg,0x80(r0)
-
-/*
- * For UNHANLDED_EXCEPTION
- */
-
-#define EXCEPTION_T_STORE_GPR31		l.sw    0x84(r0),r31
-#define EXCEPTION_T_LOAD_GPR31(reg)	l.lwz   reg,0x84(r0)
+#endif
 
 /* =========================================================[ macros ]=== */
 
@@ -226,7 +269,7 @@
  *
  */
 #define UNHANDLED_EXCEPTION(handler)				\
-	EXCEPTION_T_STORE_GPR31					;\
+	EXCEPTION_T_STORE_GPR30					;\
 	EXCEPTION_T_STORE_GPR10					;\
 	EXCEPTION_T_STORE_SP					;\
 	/* temporary store r3, r9 into r1, r10 */		;\
@@ -255,35 +298,35 @@
 	/* r1: KSP, r10: current, r31: __pa(KSP) */		;\
 	/* r12:	temp, syscall indicator, r13 temp */		;\
 	l.addi  r1,r1,-(INT_FRAME_SIZE)				;\
-	/* r1 is KSP, r31 is __pa(KSP) */			;\
-	tophys  (r31,r1)					;\
-	l.sw    PT_GPR12(r31),r12					;\
+	/* r1 is KSP, r30 is __pa(KSP) */			;\
+	tophys  (r30,r1)					;\
+	l.sw    PT_GPR12(r30),r12					;\
 	l.mfspr r12,r0,SPR_EPCR_BASE				;\
-	l.sw    PT_PC(r31),r12					;\
+	l.sw    PT_PC(r30),r12					;\
 	l.mfspr r12,r0,SPR_ESR_BASE				;\
-	l.sw    PT_SR(r31),r12					;\
+	l.sw    PT_SR(r30),r12					;\
 	/* save r31 */						;\
-	EXCEPTION_T_LOAD_GPR31(r12)				;\
-	l.sw	PT_GPR31(r31),r12					;\
+	EXCEPTION_T_LOAD_GPR30(r12)				;\
+	l.sw	PT_GPR30(r30),r12					;\
 	/* save r10 as was prior to exception */		;\
 	EXCEPTION_T_LOAD_GPR10(r12)				;\
-	l.sw	PT_GPR10(r31),r12					;\
+	l.sw	PT_GPR10(r30),r12					;\
 	/* save PT_SP as was prior to exception */			;\
 	EXCEPTION_T_LOAD_SP(r12)				;\
-	l.sw	PT_SP(r31),r12					;\
-	l.sw    PT_GPR13(r31),r13					;\
+	l.sw	PT_SP(r30),r12					;\
+	l.sw    PT_GPR13(r30),r13					;\
 	/* --> */						;\
 	/* save exception r4, set r4 = EA */			;\
-	l.sw	PT_GPR4(r31),r4					;\
+	l.sw	PT_GPR4(r30),r4					;\
 	l.mfspr r4,r0,SPR_EEAR_BASE				;\
 	/* r12 == 1 if we come from syscall */			;\
 	CLEAR_GPR(r12)						;\
 	/* ----- play a MMU trick ----- */			;\
-	l.ori	r31,r0,(EXCEPTION_SR)				;\
-	l.mtspr	r0,r31,SPR_ESR_BASE				;\
+	l.ori	r30,r0,(EXCEPTION_SR)				;\
+	l.mtspr	r0,r30,SPR_ESR_BASE				;\
 	/* r31:	EA address of handler */			;\
-	LOAD_SYMBOL_2_GPR(r31,handler)				;\
-	l.mtspr r0,r31,SPR_EPCR_BASE				;\
+	LOAD_SYMBOL_2_GPR(r30,handler)				;\
+	l.mtspr r0,r30,SPR_EPCR_BASE				;\
 	l.rfe
 
 /* =====================================================[ exceptions] === */
-- 
2.13.5

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#1729930 — [PATCH v2 04/14] openrisc: use qspinlocks and qrwlocks

From	Stafford Horne <shorne@gmail.com>
Date	2017-09-10 09:00 +0200
Subject	[PATCH v2 04/14] openrisc: use qspinlocks and qrwlocks
Message-ID	<uo4nM-8oU-31@gated-at.bofh.it>
In reply to	#1729919

Enable OpenRISC to use qspinlocks and qrwlocks for upcoming SMP support.

Signed-off-by: Stafford Horne <shorne@gmail.com>
---
 arch/openrisc/Kconfig                      |  2 ++
 arch/openrisc/include/asm/Kbuild           |  4 ++++
 arch/openrisc/include/asm/spinlock.h       | 12 +++++++++++-
 arch/openrisc/include/asm/spinlock_types.h |  7 +++++++
 4 files changed, 24 insertions(+), 1 deletion(-)
 create mode 100644 arch/openrisc/include/asm/spinlock_types.h

diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index 356dd67a86ea..b49acda5e8f4 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -28,6 +28,8 @@ config OPENRISC
 	select OR1K_PIC
 	select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
 	select NO_BOOTMEM
+	select ARCH_USE_QUEUED_SPINLOCKS
+	select ARCH_USE_QUEUED_RWLOCKS
 
 config CPU_BIG_ENDIAN
 	def_bool y
diff --git a/arch/openrisc/include/asm/Kbuild b/arch/openrisc/include/asm/Kbuild
index 5bea416a7792..5f066780d870 100644
--- a/arch/openrisc/include/asm/Kbuild
+++ b/arch/openrisc/include/asm/Kbuild
@@ -28,6 +28,10 @@ generic-y += module.h
 generic-y += pci.h
 generic-y += percpu.h
 generic-y += preempt.h
+generic-y += qspinlock_types.h
+generic-y += qspinlock.h
+generic-y += qrwlock_types.h
+generic-y += qrwlock.h
 generic-y += sections.h
 generic-y += segment.h
 generic-y += string.h
diff --git a/arch/openrisc/include/asm/spinlock.h b/arch/openrisc/include/asm/spinlock.h
index fd00a3a24123..9b761e0e22c3 100644
--- a/arch/openrisc/include/asm/spinlock.h
+++ b/arch/openrisc/include/asm/spinlock.h
@@ -19,6 +19,16 @@
 #ifndef __ASM_OPENRISC_SPINLOCK_H
 #define __ASM_OPENRISC_SPINLOCK_H
 
-#error "or32 doesn't do SMP yet"
+#include <asm/qspinlock.h>
+
+#include <asm/qrwlock.h>
+
+#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
+#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
+
+#define arch_spin_relax(lock)	cpu_relax()
+#define arch_read_relax(lock)	cpu_relax()
+#define arch_write_relax(lock)	cpu_relax()
+
 
 #endif
diff --git a/arch/openrisc/include/asm/spinlock_types.h b/arch/openrisc/include/asm/spinlock_types.h
new file mode 100644
index 000000000000..7c6fb1208c88
--- /dev/null
+++ b/arch/openrisc/include/asm/spinlock_types.h
@@ -0,0 +1,7 @@
+#ifndef _ASM_OPENRISC_SPINLOCK_TYPES_H
+#define _ASM_OPENRISC_SPINLOCK_TYPES_H
+
+#include <asm/qspinlock_types.h>
+#include <asm/qrwlock_types.h>
+
+#endif /* _ASM_OPENRISC_SPINLOCK_TYPES_H */
-- 
2.13.5

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#1729931 — [PATCH v2 05/14] dt-bindings: add openrisc to vendor prefixes list

From	Stafford Horne <shorne@gmail.com>
Date	2017-09-10 09:00 +0200
Subject	[PATCH v2 05/14] dt-bindings: add openrisc to vendor prefixes list
Message-ID	<uo4nN-8oU-35@gated-at.bofh.it>
In reply to	#1729919

Add OpenRISC.io to vendor prefixes.  This is reserved for softcores
developed by the OpenRISC community.  The OpenRISC community has
separated from OpenCores.org requiring a new prefix.

Signed-off-by: Stafford Horne <shorne@gmail.com>
---

Changes since v1
 - New patch

 Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index daf465bef758..0025aa7c3745 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -241,6 +241,7 @@ onion	Onion Corporation
 onnn	ON Semiconductor Corp.
 ontat	On Tat Industrial Company
 opencores	OpenCores.org
+openrisc	OpenRISC.io
 option	Option NV
 ORCL	Oracle Corporation
 ortustech	Ortus Technology Co., Ltd.
-- 
2.13.5

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#1729957 — Re: [PATCH v2 05/14] dt-bindings: add openrisc to vendor prefixes list

From	Andreas Färber <afaerber@suse.de>
Date	2017-09-10 13:20 +0200
Subject	Re: [PATCH v2 05/14] dt-bindings: add openrisc to vendor prefixes list
Message-ID	<uo8ro-2Wb-5@gated-at.bofh.it>
In reply to	#1729931

Am 10.09.2017 um 08:49 schrieb Stafford Horne:
> Add OpenRISC.io to vendor prefixes.  This is reserved for softcores
> developed by the OpenRISC community.  The OpenRISC community has
> separated from OpenCores.org requiring a new prefix.
> 
> Signed-off-by: Stafford Horne <shorne@gmail.com>

Reviewed-by: Andreas Färber <afaerber@suse.de>

Regards,
Andreas

-- 
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)

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#1734461 — Re: [PATCH v2 05/14] dt-bindings: add openrisc to vendor prefixes list

From	Rob Herring <robh@kernel.org>
Date	2017-09-18 22:40 +0200
Subject	Re: [PATCH v2 05/14] dt-bindings: add openrisc to vendor prefixes list
Message-ID	<uraZH-2S2-9@gated-at.bofh.it>
In reply to	#1729931

On Sun, Sep 10, 2017 at 03:49:17PM +0900, Stafford Horne wrote:
> Add OpenRISC.io to vendor prefixes.  This is reserved for softcores
> developed by the OpenRISC community.  The OpenRISC community has
> separated from OpenCores.org requiring a new prefix.
> 
> Signed-off-by: Stafford Horne <shorne@gmail.com>
> ---
> 
> Changes since v1
>  - New patch
> 
>  Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Rob Herring <robh@kernel.org>

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#1729932 — [PATCH v2 06/14] irqchip: add initial support for ompic

From	Stafford Horne <shorne@gmail.com>
Date	2017-09-10 09:00 +0200
Subject	[PATCH v2 06/14] irqchip: add initial support for ompic
Message-ID	<uo4nN-8oU-37@gated-at.bofh.it>
In reply to	#1729919

From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>

IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as
described in the Multicore support section of the OpenRISC 1.2
proposed architecture specification:

  https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-rev0.pdf

Each OpenRISC core contains a full interrupt controller which is used in
the SMP architecture for interrupt balancing.  This IPI device, the
ompic, is the only external device required for enabling SMP on
OpenRISC.

Pending ops are stored in a memory bit mask which can allow multiple
pending operations to be set and serviced at a time. This is mostly
borrowed from the alpha IPI implementation.

Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
[shorne@gmail.com: converted ops to bitmask, wrote commit message]
Signed-off-by: Stafford Horne <shorne@gmail.com>
---

Changes since v1
 - Added openrisc, prefix
 - Clarified 8 bytes per cpu
 - Removed #interrupt-cells as this will not be an irq parent
 - Changed ops to be percpu
 - Added DTS and intialization failure validations

 .../interrupt-controller/openrisc,ompic.txt        |  19 ++
 arch/openrisc/Kconfig                              |   1 +
 drivers/irqchip/Kconfig                            |   3 +
 drivers/irqchip/Makefile                           |   1 +
 drivers/irqchip/irq-ompic.c                        | 205 +++++++++++++++++++++
 5 files changed, 229 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt
 create mode 100644 drivers/irqchip/irq-ompic.c

diff --git a/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt b/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt
new file mode 100644
index 000000000000..346e6042d62f
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt
@@ -0,0 +1,19 @@
+Open Multi-Processor Interrupt Controller
+
+Required properties:
+
+- compatible : This should be "openrisc,ompic"
+- reg : Specifies base physical address and size of the register space. The
+  size is based on the number of cores the controller has been configured
+  to handle, this should be set to 8 bytes per cpu core.
+- interrupt-controller : Identifies the node as an interrupt controller
+- interrupts : Specifies the interrupt line to which the ompic is wired.
+
+Example:
+
+ompic: ompic {
+	compatible = "openrisc,ompic";
+	reg = <0x98000000 16>;
+	interrupt-controller;
+	interrupts = <1>;
+};
diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
index b49acda5e8f4..34eb4e90f56c 100644
--- a/arch/openrisc/Kconfig
+++ b/arch/openrisc/Kconfig
@@ -30,6 +30,7 @@ config OPENRISC
 	select NO_BOOTMEM
 	select ARCH_USE_QUEUED_SPINLOCKS
 	select ARCH_USE_QUEUED_RWLOCKS
+	select OMPIC if SMP
 
 config CPU_BIG_ENDIAN
 	def_bool y
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index f1fd5f44d1d4..0e4c96c90b86 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -145,6 +145,9 @@ config CLPS711X_IRQCHIP
 	select SPARSE_IRQ
 	default y
 
+config OMPIC
+	bool
+
 config OR1K_PIC
 	bool
 	select IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index e88d856cc09c..123047d7a20d 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_DW_APB_ICTL)		+= irq-dw-apb-ictl.o
 obj-$(CONFIG_METAG)			+= irq-metag-ext.o
 obj-$(CONFIG_METAG_PERFCOUNTER_IRQS)	+= irq-metag.o
 obj-$(CONFIG_CLPS711X_IRQCHIP)		+= irq-clps711x.o
+obj-$(CONFIG_OMPIC)			+= irq-ompic.o
 obj-$(CONFIG_OR1K_PIC)			+= irq-or1k-pic.o
 obj-$(CONFIG_ORION_IRQCHIP)		+= irq-orion.o
 obj-$(CONFIG_OMAP_IRQCHIP)		+= irq-omap-intc.o
diff --git a/drivers/irqchip/irq-ompic.c b/drivers/irqchip/irq-ompic.c
new file mode 100644
index 000000000000..cd2616b6639b
--- /dev/null
+++ b/drivers/irqchip/irq-ompic.c
@@ -0,0 +1,205 @@
+/*
+ * Open Multi-Processor Interrupt Controller driver
+ *
+ * Copyright (C) 2014 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
+ * Copyright (C) 2017 Stafford Horne <shorne@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ *
+ * The ompic device handles IPI communication because cores in mulicore
+ * OpenRISC systems.
+ *
+ * Registers
+ *
+ * For each CPU the ompic has 2 registers. The control register for sending
+ * and acking IPIs and the status register for receiving IPIs. The register
+ * layouts are as follows:
+ *
+ *  Control register
+ *  +---------+---------+----------+---------+
+ *  | 31      | 30      | 29 .. 16 | 15 .. 0 |
+ *  ----------+---------+----------+----------
+ *  | IRQ ACK | IRQ GEN | DST CORE | DATA    |
+ *  +---------+---------+----------+---------+
+ *
+ *  Status register
+ *  +----------+-------------+----------+---------+
+ *  | 31       | 30          | 29 .. 16 | 15 .. 0 |
+ *  -----------+-------------+----------+---------+
+ *  | Reserved | IRQ Pending | SRC CORE | DATA    |
+ *  +----------+-------------+----------+---------+
+ *
+ * Architecture
+ *
+ * - The ompic generates a level interrupt to the CPU PIC when a message is
+ *   ready.  Messages are delivered via the memory bus.
+ * - The ompic does not have any interrupt input lines.
+ * - The ompic is wired to the same irq line on each core.
+ * - Devices are wired to the same irq line on each core.
+ *
+ *   +---------+                         +---------+
+ *   | CPU     |                         | CPU     |
+ *   |  Core 0 |<==\ (memory access) /==>|  Core 1 |
+ *   |  [ PIC ]|   |                 |   |  [ PIC ]|
+ *   +----^-^--+   |                 |   +----^-^--+
+ *        | |      v                 v        | |
+ *   <====|=|=================================|=|==> (memory bus)
+ *        | |      ^                  ^       | |
+ *  (ipi  | +------|---------+--------|-------|-+ (device irq)
+ *   irq  |        |         |        |       |
+ *  core0)| +------|---------|--------|-------+ (ipi irq core1)
+ *        | |      |         |        |
+ *   +----o-o-+    |    +--------+    |
+ *   | ompic  |<===/    | Device |<===/
+ *   |  IPI   |         +--------+
+ *   +--------+*
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/interrupt.h>
+#include <linux/smp.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+
+#include <linux/irqchip.h>
+
+#define OMPIC_CPUBYTES		8
+#define OMPIC_CTRL(cpu)		(0x0 + (cpu * OMPIC_CPUBYTES))
+#define OMPIC_STAT(cpu)		(0x4 + (cpu * OMPIC_CPUBYTES))
+
+#define OMPIC_CTRL_IRQ_ACK	(1 << 31)
+#define OMPIC_CTRL_IRQ_GEN	(1 << 30)
+#define OMPIC_CTRL_DST(cpu)	(((cpu) & 0x3fff) << 16)
+
+#define OMPIC_STAT_IRQ_PENDING	(1 << 30)
+
+#define OMPIC_DATA(x)		((x) & 0xffff)
+
+DEFINE_PER_CPU(unsigned long, ops);
+
+static void __iomem *ompic_base;
+
+static inline u32 ompic_readreg(void __iomem *base, loff_t offset)
+{
+	return ioread32be(base + offset);
+}
+
+static void ompic_writereg(void __iomem *base, loff_t offset, u32 data)
+{
+	iowrite32be(data, base + offset);
+}
+
+void ompic_raise_softirq(const struct cpumask *mask, unsigned int ipi_msg)
+{
+	unsigned int dst_cpu;
+	unsigned int src_cpu = smp_processor_id();
+
+	for_each_cpu(dst_cpu, mask) {
+		set_bit(ipi_msg, &per_cpu(ops, dst_cpu));
+
+		/*
+		 * On OpenRISC the atomic set_bit() call implies a memory
+		 * barrier.  Otherwise we would need: smp_wmb(); paired
+		 * with the read in ompic_ipi_handler.
+		 */
+
+		ompic_writereg(ompic_base, OMPIC_CTRL(src_cpu),
+			       OMPIC_CTRL_IRQ_GEN |
+			       OMPIC_CTRL_DST(dst_cpu) |
+			       OMPIC_DATA(1));
+	}
+}
+
+irqreturn_t ompic_ipi_handler(int irq, void *dev_id)
+{
+	unsigned int cpu = smp_processor_id();
+	unsigned long *pending_ops = &per_cpu(ops, cpu);
+	unsigned long ops;
+
+	ompic_writereg(ompic_base, OMPIC_CTRL(cpu), OMPIC_CTRL_IRQ_ACK);
+	while ((ops = xchg(pending_ops, 0)) != 0) {
+
+		/*
+		 * On OpenRISC the atomic xchg() call implies a memory
+		 * barrier.  Otherwise we may need an smp_rmb(); paired
+		 * with the write in ompic_raise_softirq.
+		 */
+
+		do {
+			unsigned long ipi_msg;
+
+			ipi_msg = __ffs(ops);
+			ops &= ~(1UL << ipi_msg);
+
+			handle_IPI(ipi_msg);
+		} while (ops);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static struct irqaction ompi_ipi_irqaction = {
+	.handler =      ompic_ipi_handler,
+	.flags =        IRQF_PERCPU,
+	.name =         "ompic_ipi",
+};
+
+int __init ompic_of_init(struct device_node *node, struct device_node *parent)
+{
+	struct resource res;
+	int irq;
+	int ret;
+
+	/* Validate the DT */
+	if (ompic_base) {
+		pr_err("ompic: duplicate ompic's are not supported");
+		return -EEXIST;
+	}
+
+	if (of_address_to_resource(node, 0, &res)) {
+		pr_err("ompic: reg property requires an address and size");
+		return -EINVAL;
+	}
+
+	if (resource_size(&res) < (num_possible_cpus() * OMPIC_CPUBYTES)) {
+		pr_err("ompic: reg size, currently %d must be at least %d",
+			resource_size(&res),
+			(num_possible_cpus() * OMPIC_CPUBYTES));
+		return -EINVAL;
+	}
+
+	/* Setup the device */
+	ompic_base = ioremap(res.start, resource_size(&res));
+	if (IS_ERR(ompic_base)) {
+		pr_err("ompic: unable to map registers");
+		return PTR_ERR(ompic_base);
+	}
+
+	irq = irq_of_parse_and_map(node, 0);
+	if (irq <= 0) {
+		pr_err("ompic: unable to parse device irq");
+		ret = -EINVAL;
+		goto out_unmap;
+	}
+
+	ret = setup_irq(irq, &ompi_ipi_irqaction);
+	if (ret)
+		goto out_irq_disp;
+
+	set_smp_cross_call(ompic_raise_softirq);
+
+	return 0;
+
+out_irq_disp:
+	irq_dispose_mapping(irq);
+out_unmap:
+	iounmap(ompic_base);
+	ompic_base = NULL;
+	return ret;
+}
+IRQCHIP_DECLARE(ompic, "openrisc,ompic", ompic_of_init);
-- 
2.13.5

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#1731741 — Re: [PATCH v2 06/14] irqchip: add initial support for ompic

From	Marc Zyngier <marc.zyngier@arm.com>
Date	2017-09-13 19:30 +0200
Subject	Re: [PATCH v2 06/14] irqchip: add initial support for ompic
Message-ID	<upjE6-1RR-21@gated-at.bofh.it>
In reply to	#1729932

On Sun, Sep 10 2017 at  3:49:18 pm BST, Stafford Horne <shorne@gmail.com> wrote:
> From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
>
> IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as
> described in the Multicore support section of the OpenRISC 1.2
> proposed architecture specification:
>
>   https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-rev0.pdf
>
> Each OpenRISC core contains a full interrupt controller which is used in
> the SMP architecture for interrupt balancing.  This IPI device, the
> ompic, is the only external device required for enabling SMP on
> OpenRISC.
>
> Pending ops are stored in a memory bit mask which can allow multiple
> pending operations to be set and serviced at a time. This is mostly
> borrowed from the alpha IPI implementation.
>
> Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> [shorne@gmail.com: converted ops to bitmask, wrote commit message]
> Signed-off-by: Stafford Horne <shorne@gmail.com>
> ---
>
> Changes since v1
>  - Added openrisc, prefix
>  - Clarified 8 bytes per cpu
>  - Removed #interrupt-cells as this will not be an irq parent
>  - Changed ops to be percpu
>  - Added DTS and intialization failure validations
>
>  .../interrupt-controller/openrisc,ompic.txt        |  19 ++
>  arch/openrisc/Kconfig                              |   1 +
>  drivers/irqchip/Kconfig                            |   3 +
>  drivers/irqchip/Makefile                           |   1 +
>  drivers/irqchip/irq-ompic.c                        | 205 +++++++++++++++++++++
>  5 files changed, 229 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt
>  create mode 100644 drivers/irqchip/irq-ompic.c
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt b/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt
> new file mode 100644
> index 000000000000..346e6042d62f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt
> @@ -0,0 +1,19 @@
> +Open Multi-Processor Interrupt Controller
> +
> +Required properties:
> +
> +- compatible : This should be "openrisc,ompic"
> +- reg : Specifies base physical address and size of the register space. The
> +  size is based on the number of cores the controller has been configured
> +  to handle, this should be set to 8 bytes per cpu core.
> +- interrupt-controller : Identifies the node as an interrupt controller
> +- interrupts : Specifies the interrupt line to which the ompic is wired.
> +
> +Example:
> +
> +ompic: ompic {
> +	compatible = "openrisc,ompic";
> +	reg = <0x98000000 16>;
> +	interrupt-controller;
> +	interrupts = <1>;
> +};
> diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
> index b49acda5e8f4..34eb4e90f56c 100644
> --- a/arch/openrisc/Kconfig
> +++ b/arch/openrisc/Kconfig
> @@ -30,6 +30,7 @@ config OPENRISC
>  	select NO_BOOTMEM
>  	select ARCH_USE_QUEUED_SPINLOCKS
>  	select ARCH_USE_QUEUED_RWLOCKS
> +	select OMPIC if SMP
>  
>  config CPU_BIG_ENDIAN
>  	def_bool y
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index f1fd5f44d1d4..0e4c96c90b86 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -145,6 +145,9 @@ config CLPS711X_IRQCHIP
>  	select SPARSE_IRQ
>  	default y
>  
> +config OMPIC
> +	bool
> +
>  config OR1K_PIC
>  	bool
>  	select IRQ_DOMAIN
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index e88d856cc09c..123047d7a20d 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -17,6 +17,7 @@ obj-$(CONFIG_DW_APB_ICTL)		+= irq-dw-apb-ictl.o
>  obj-$(CONFIG_METAG)			+= irq-metag-ext.o
>  obj-$(CONFIG_METAG_PERFCOUNTER_IRQS)	+= irq-metag.o
>  obj-$(CONFIG_CLPS711X_IRQCHIP)		+= irq-clps711x.o
> +obj-$(CONFIG_OMPIC)			+= irq-ompic.o
>  obj-$(CONFIG_OR1K_PIC)			+= irq-or1k-pic.o
>  obj-$(CONFIG_ORION_IRQCHIP)		+= irq-orion.o
>  obj-$(CONFIG_OMAP_IRQCHIP)		+= irq-omap-intc.o
> diff --git a/drivers/irqchip/irq-ompic.c b/drivers/irqchip/irq-ompic.c
> new file mode 100644
> index 000000000000..cd2616b6639b
> --- /dev/null
> +++ b/drivers/irqchip/irq-ompic.c
> @@ -0,0 +1,205 @@
> +/*
> + * Open Multi-Processor Interrupt Controller driver
> + *
> + * Copyright (C) 2014 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> + * Copyright (C) 2017 Stafford Horne <shorne@gmail.com>
> + *
> + * This file is licensed under the terms of the GNU General Public License
> + * version 2.  This program is licensed "as is" without any warranty of any
> + * kind, whether express or implied.
> + *
> + * The ompic device handles IPI communication because cores in mulicore
> + * OpenRISC systems.

Should the above read "between cores"?

> + *
> + * Registers
> + *
> + * For each CPU the ompic has 2 registers. The control register for sending
> + * and acking IPIs and the status register for receiving IPIs. The register
> + * layouts are as follows:
> + *
> + *  Control register
> + *  +---------+---------+----------+---------+
> + *  | 31      | 30      | 29 .. 16 | 15 .. 0 |
> + *  ----------+---------+----------+----------
> + *  | IRQ ACK | IRQ GEN | DST CORE | DATA    |
> + *  +---------+---------+----------+---------+
> + *
> + *  Status register
> + *  +----------+-------------+----------+---------+
> + *  | 31       | 30          | 29 .. 16 | 15 .. 0 |
> + *  -----------+-------------+----------+---------+
> + *  | Reserved | IRQ Pending | SRC CORE | DATA    |
> + *  +----------+-------------+----------+---------+
> + *
> + * Architecture
> + *
> + * - The ompic generates a level interrupt to the CPU PIC when a message is
> + *   ready.  Messages are delivered via the memory bus.
> + * - The ompic does not have any interrupt input lines.
> + * - The ompic is wired to the same irq line on each core.
> + * - Devices are wired to the same irq line on each core.
> + *
> + *   +---------+                         +---------+
> + *   | CPU     |                         | CPU     |
> + *   |  Core 0 |<==\ (memory access) /==>|  Core 1 |
> + *   |  [ PIC ]|   |                 |   |  [ PIC ]|
> + *   +----^-^--+   |                 |   +----^-^--+
> + *        | |      v                 v        | |
> + *   <====|=|=================================|=|==> (memory bus)
> + *        | |      ^                  ^       | |
> + *  (ipi  | +------|---------+--------|-------|-+ (device irq)
> + *   irq  |        |         |        |       |
> + *  core0)| +------|---------|--------|-------+ (ipi irq core1)
> + *        | |      |         |        |
> + *   +----o-o-+    |    +--------+    |
> + *   | ompic  |<===/    | Device |<===/
> + *   |  IPI   |         +--------+
> + *   +--------+*
> + *
> + */
> +
> +#include <linux/io.h>
> +#include <linux/ioport.h>
> +#include <linux/interrupt.h>
> +#include <linux/smp.h>
> +#include <linux/of.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_address.h>
> +
> +#include <linux/irqchip.h>
> +
> +#define OMPIC_CPUBYTES		8
> +#define OMPIC_CTRL(cpu)		(0x0 + (cpu * OMPIC_CPUBYTES))
> +#define OMPIC_STAT(cpu)		(0x4 + (cpu * OMPIC_CPUBYTES))
> +
> +#define OMPIC_CTRL_IRQ_ACK	(1 << 31)
> +#define OMPIC_CTRL_IRQ_GEN	(1 << 30)
> +#define OMPIC_CTRL_DST(cpu)	(((cpu) & 0x3fff) << 16)
> +
> +#define OMPIC_STAT_IRQ_PENDING	(1 << 30)
> +
> +#define OMPIC_DATA(x)		((x) & 0xffff)
> +
> +DEFINE_PER_CPU(unsigned long, ops);
> +
> +static void __iomem *ompic_base;
> +
> +static inline u32 ompic_readreg(void __iomem *base, loff_t offset)
> +{
> +	return ioread32be(base + offset);
> +}
> +
> +static void ompic_writereg(void __iomem *base, loff_t offset, u32 data)
> +{
> +	iowrite32be(data, base + offset);
> +}
> +
> +void ompic_raise_softirq(const struct cpumask *mask, unsigned int ipi_msg)

Please make this static.

> +{
> +	unsigned int dst_cpu;
> +	unsigned int src_cpu = smp_processor_id();
> +
> +	for_each_cpu(dst_cpu, mask) {
> +		set_bit(ipi_msg, &per_cpu(ops, dst_cpu));
> +
> +		/*
> +		 * On OpenRISC the atomic set_bit() call implies a memory
> +		 * barrier.  Otherwise we would need: smp_wmb(); paired
> +		 * with the read in ompic_ipi_handler.
> +		 */

One last question on this, because the architecture document is terribly
unclear: If you have CPU0 doing an atomic operation A0, CPU1 seeing A0
and doeing another atomic A1 (the set_bit above) followed by an IPI to
CPU2, is CPU2 *guaranteed* to observe both A0 *and* A1? Because that's
required by the IPI semantics, and you wouldn't see that kind of issue
with only two CPUs.

> +
> +		ompic_writereg(ompic_base, OMPIC_CTRL(src_cpu),
> +			       OMPIC_CTRL_IRQ_GEN |
> +			       OMPIC_CTRL_DST(dst_cpu) |
> +			       OMPIC_DATA(1));
> +	}
> +}
> +
> +irqreturn_t ompic_ipi_handler(int irq, void *dev_id)

This should be static.

> +{
> +	unsigned int cpu = smp_processor_id();
> +	unsigned long *pending_ops = &per_cpu(ops, cpu);
> +	unsigned long ops;
> +
> +	ompic_writereg(ompic_base, OMPIC_CTRL(cpu), OMPIC_CTRL_IRQ_ACK);
> +	while ((ops = xchg(pending_ops, 0)) != 0) {
> +
> +		/*
> +		 * On OpenRISC the atomic xchg() call implies a memory
> +		 * barrier.  Otherwise we may need an smp_rmb(); paired
> +		 * with the write in ompic_raise_softirq.
> +		 */
> +
> +		do {
> +			unsigned long ipi_msg;
> +
> +			ipi_msg = __ffs(ops);
> +			ops &= ~(1UL << ipi_msg);
> +
> +			handle_IPI(ipi_msg);
> +		} while (ops);
> +	}
> +
> +	return IRQ_HANDLED;
> +}
> +
> +static struct irqaction ompi_ipi_irqaction = {
> +	.handler =      ompic_ipi_handler,
> +	.flags =        IRQF_PERCPU,
> +	.name =         "ompic_ipi",
> +};
> +
> +int __init ompic_of_init(struct device_node *node, struct device_node *parent)

static again.

> +{
> +	struct resource res;
> +	int irq;
> +	int ret;
> +
> +	/* Validate the DT */
> +	if (ompic_base) {
> +		pr_err("ompic: duplicate ompic's are not supported");
> +		return -EEXIST;
> +	}
> +
> +	if (of_address_to_resource(node, 0, &res)) {
> +		pr_err("ompic: reg property requires an address and size");
> +		return -EINVAL;
> +	}
> +
> +	if (resource_size(&res) < (num_possible_cpus() * OMPIC_CPUBYTES)) {
> +		pr_err("ompic: reg size, currently %d must be at least %d",
> +			resource_size(&res),
> +			(num_possible_cpus() * OMPIC_CPUBYTES));
> +		return -EINVAL;
> +	}
> +
> +	/* Setup the device */
> +	ompic_base = ioremap(res.start, resource_size(&res));
> +	if (IS_ERR(ompic_base)) {
> +		pr_err("ompic: unable to map registers");
> +		return PTR_ERR(ompic_base);
> +	}
> +
> +	irq = irq_of_parse_and_map(node, 0);
> +	if (irq <= 0) {
> +		pr_err("ompic: unable to parse device irq");
> +		ret = -EINVAL;
> +		goto out_unmap;
> +	}
> +
> +	ret = setup_irq(irq, &ompi_ipi_irqaction);
> +	if (ret)
> +		goto out_irq_disp;
> +
> +	set_smp_cross_call(ompic_raise_softirq);
> +
> +	return 0;
> +
> +out_irq_disp:
> +	irq_dispose_mapping(irq);
> +out_unmap:
> +	iounmap(ompic_base);
> +	ompic_base = NULL;
> +	return ret;
> +}
> +IRQCHIP_DECLARE(ompic, "openrisc,ompic", ompic_of_init);

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny.

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#1732071 — Re: [PATCH v2 06/14] irqchip: add initial support for ompic

From	Stafford Horne <shorne@gmail.com>
Date	2017-09-14 09:00 +0200
Subject	Re: [PATCH v2 06/14] irqchip: add initial support for ompic
Message-ID	<upwhX-1Dp-3@gated-at.bofh.it>
In reply to	#1731741

On Wed, Sep 13, 2017 at 06:21:39PM +0100, Marc Zyngier wrote:
> On Sun, Sep 10 2017 at  3:49:18 pm BST, Stafford Horne <shorne@gmail.com> wrote:
> > From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> >
> > IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as
> > described in the Multicore support section of the OpenRISC 1.2
> > proposed architecture specification:
> >
> >   https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-rev0.pdf
> >
> > Each OpenRISC core contains a full interrupt controller which is used in
> > the SMP architecture for interrupt balancing.  This IPI device, the
> > ompic, is the only external device required for enabling SMP on
> > OpenRISC.
> >
> > Pending ops are stored in a memory bit mask which can allow multiple
> > pending operations to be set and serviced at a time. This is mostly
> > borrowed from the alpha IPI implementation.
> >
> > Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> > [shorne@gmail.com: converted ops to bitmask, wrote commit message]
> > Signed-off-by: Stafford Horne <shorne@gmail.com>
> > ---
> >
> > Changes since v1
> >  - Added openrisc, prefix
> >  - Clarified 8 bytes per cpu
> >  - Removed #interrupt-cells as this will not be an irq parent
> >  - Changed ops to be percpu
> >  - Added DTS and intialization failure validations
> >
> >  .../interrupt-controller/openrisc,ompic.txt        |  19 ++
> >  arch/openrisc/Kconfig                              |   1 +
> >  drivers/irqchip/Kconfig                            |   3 +
> >  drivers/irqchip/Makefile                           |   1 +
> >  drivers/irqchip/irq-ompic.c                        | 205 +++++++++++++++++++++
> >  5 files changed, 229 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt
> >  create mode 100644 drivers/irqchip/irq-ompic.c
> >
> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt b/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt
> > new file mode 100644
> > index 000000000000..346e6042d62f
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt
> > @@ -0,0 +1,19 @@
> > +Open Multi-Processor Interrupt Controller
> > +
> > +Required properties:
> > +
> > +- compatible : This should be "openrisc,ompic"
> > +- reg : Specifies base physical address and size of the register space. The
> > +  size is based on the number of cores the controller has been configured
> > +  to handle, this should be set to 8 bytes per cpu core.
> > +- interrupt-controller : Identifies the node as an interrupt controller
> > +- interrupts : Specifies the interrupt line to which the ompic is wired.
> > +
> > +Example:
> > +
> > +ompic: ompic {
> > +	compatible = "openrisc,ompic";
> > +	reg = <0x98000000 16>;
> > +	interrupt-controller;
> > +	interrupts = <1>;
> > +};
> > diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
> > index b49acda5e8f4..34eb4e90f56c 100644
> > --- a/arch/openrisc/Kconfig
> > +++ b/arch/openrisc/Kconfig
> > @@ -30,6 +30,7 @@ config OPENRISC
> >  	select NO_BOOTMEM
> >  	select ARCH_USE_QUEUED_SPINLOCKS
> >  	select ARCH_USE_QUEUED_RWLOCKS
> > +	select OMPIC if SMP
> >  
> >  config CPU_BIG_ENDIAN
> >  	def_bool y
> > diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> > index f1fd5f44d1d4..0e4c96c90b86 100644
> > --- a/drivers/irqchip/Kconfig
> > +++ b/drivers/irqchip/Kconfig
> > @@ -145,6 +145,9 @@ config CLPS711X_IRQCHIP
> >  	select SPARSE_IRQ
> >  	default y
> >  
> > +config OMPIC
> > +	bool
> > +
> >  config OR1K_PIC
> >  	bool
> >  	select IRQ_DOMAIN
> > diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> > index e88d856cc09c..123047d7a20d 100644
> > --- a/drivers/irqchip/Makefile
> > +++ b/drivers/irqchip/Makefile
> > @@ -17,6 +17,7 @@ obj-$(CONFIG_DW_APB_ICTL)		+= irq-dw-apb-ictl.o
> >  obj-$(CONFIG_METAG)			+= irq-metag-ext.o
> >  obj-$(CONFIG_METAG_PERFCOUNTER_IRQS)	+= irq-metag.o
> >  obj-$(CONFIG_CLPS711X_IRQCHIP)		+= irq-clps711x.o
> > +obj-$(CONFIG_OMPIC)			+= irq-ompic.o
> >  obj-$(CONFIG_OR1K_PIC)			+= irq-or1k-pic.o
> >  obj-$(CONFIG_ORION_IRQCHIP)		+= irq-orion.o
> >  obj-$(CONFIG_OMAP_IRQCHIP)		+= irq-omap-intc.o
> > diff --git a/drivers/irqchip/irq-ompic.c b/drivers/irqchip/irq-ompic.c
> > new file mode 100644
> > index 000000000000..cd2616b6639b
> > --- /dev/null
> > +++ b/drivers/irqchip/irq-ompic.c
> > @@ -0,0 +1,205 @@
> > +/*
> > + * Open Multi-Processor Interrupt Controller driver
> > + *
> > + * Copyright (C) 2014 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> > + * Copyright (C) 2017 Stafford Horne <shorne@gmail.com>
> > + *
> > + * This file is licensed under the terms of the GNU General Public License
> > + * version 2.  This program is licensed "as is" without any warranty of any
> > + * kind, whether express or implied.
> > + *
> > + * The ompic device handles IPI communication because cores in mulicore
> > + * OpenRISC systems.
> 
> Should the above read "between cores"?

Yes, it should be, I am bad with these kind of typos.

> > + *
> > + * Registers
> > + *
> > + * For each CPU the ompic has 2 registers. The control register for sending
> > + * and acking IPIs and the status register for receiving IPIs. The register
> > + * layouts are as follows:
> > + *
> > + *  Control register
> > + *  +---------+---------+----------+---------+
> > + *  | 31      | 30      | 29 .. 16 | 15 .. 0 |
> > + *  ----------+---------+----------+----------
> > + *  | IRQ ACK | IRQ GEN | DST CORE | DATA    |
> > + *  +---------+---------+----------+---------+
> > + *
> > + *  Status register
> > + *  +----------+-------------+----------+---------+
> > + *  | 31       | 30          | 29 .. 16 | 15 .. 0 |
> > + *  -----------+-------------+----------+---------+
> > + *  | Reserved | IRQ Pending | SRC CORE | DATA    |
> > + *  +----------+-------------+----------+---------+
> > + *
> > + * Architecture
> > + *
> > + * - The ompic generates a level interrupt to the CPU PIC when a message is
> > + *   ready.  Messages are delivered via the memory bus.
> > + * - The ompic does not have any interrupt input lines.
> > + * - The ompic is wired to the same irq line on each core.
> > + * - Devices are wired to the same irq line on each core.
> > + *
> > + *   +---------+                         +---------+
> > + *   | CPU     |                         | CPU     |
> > + *   |  Core 0 |<==\ (memory access) /==>|  Core 1 |
> > + *   |  [ PIC ]|   |                 |   |  [ PIC ]|
> > + *   +----^-^--+   |                 |   +----^-^--+
> > + *        | |      v                 v        | |
> > + *   <====|=|=================================|=|==> (memory bus)
> > + *        | |      ^                  ^       | |
> > + *  (ipi  | +------|---------+--------|-------|-+ (device irq)
> > + *   irq  |        |         |        |       |
> > + *  core0)| +------|---------|--------|-------+ (ipi irq core1)
> > + *        | |      |         |        |
> > + *   +----o-o-+    |    +--------+    |
> > + *   | ompic  |<===/    | Device |<===/
> > + *   |  IPI   |         +--------+
> > + *   +--------+*
> > + *
> > + */
> > +
> > +#include <linux/io.h>
> > +#include <linux/ioport.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/smp.h>
> > +#include <linux/of.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/of_address.h>
> > +
> > +#include <linux/irqchip.h>
> > +
> > +#define OMPIC_CPUBYTES		8
> > +#define OMPIC_CTRL(cpu)		(0x0 + (cpu * OMPIC_CPUBYTES))
> > +#define OMPIC_STAT(cpu)		(0x4 + (cpu * OMPIC_CPUBYTES))
> > +
> > +#define OMPIC_CTRL_IRQ_ACK	(1 << 31)
> > +#define OMPIC_CTRL_IRQ_GEN	(1 << 30)
> > +#define OMPIC_CTRL_DST(cpu)	(((cpu) & 0x3fff) << 16)
> > +
> > +#define OMPIC_STAT_IRQ_PENDING	(1 << 30)
> > +
> > +#define OMPIC_DATA(x)		((x) & 0xffff)
> > +
> > +DEFINE_PER_CPU(unsigned long, ops);
> > +
> > +static void __iomem *ompic_base;
> > +
> > +static inline u32 ompic_readreg(void __iomem *base, loff_t offset)
> > +{
> > +	return ioread32be(base + offset);
> > +}
> > +
> > +static void ompic_writereg(void __iomem *base, loff_t offset, u32 data)
> > +{
> > +	iowrite32be(data, base + offset);
> > +}
> > +
> > +void ompic_raise_softirq(const struct cpumask *mask, unsigned int ipi_msg)
> 
> Please make this static.

OK

> > +{
> > +	unsigned int dst_cpu;
> > +	unsigned int src_cpu = smp_processor_id();
> > +
> > +	for_each_cpu(dst_cpu, mask) {
> > +		set_bit(ipi_msg, &per_cpu(ops, dst_cpu));
> > +
> > +		/*
> > +		 * On OpenRISC the atomic set_bit() call implies a memory
> > +		 * barrier.  Otherwise we would need: smp_wmb(); paired
> > +		 * with the read in ompic_ipi_handler.
> > +		 */
> 
> One last question on this, because the architecture document is terribly
> unclear: If you have CPU0 doing an atomic operation A0, CPU1 seeing A0
> and doeing another atomic A1 (the set_bit above) followed by an IPI to
> CPU2, is CPU2 *guaranteed* to observe both A0 *and* A1? Because that's
> required by the IPI semantics, and you wouldn't see that kind of issue
> with only two CPUs.

Could you suggest an architecture document that makes this case clear?

I believe this will not be a problem, but:
  1. If this needs to be clear in the architecture document I can propose
     changes.
  2. To be clear is this the scenario you mean..

CASE1 - A0 and A1 are to different locations?
  A0 - writes to some unrelated global location?

CPU0                       CPU1                     CPU2
 A0:atomic store (global)
                           A1:set_bit (ops[CPU2])
                           IPI
                                                    read (A0,A1)


OR

CASE2 - A0 and A1 are to the same location.
  A0 - writes to the same location as A1

CPU0                       CPU1                     CPU2
 A0:set_bit (ops[CPU2])
                           A1:set_bit (ops[CPU2])
                           IPI
                                                    read (A0,A1)
 IPI


OR - something else?

In both cases CPU2 would be able to see the results of both atomic
operations.  All, cpus in the OpenRISC system snoop for memory writes to
enable cash coherency, so each CPU would see each write once it is synced
to memory (there is a single memory bus).  This is not limited to atomic
operations, but the atomic operations provide a syncrhonization point
accross all CPUs.

> > +
> > +		ompic_writereg(ompic_base, OMPIC_CTRL(src_cpu),
> > +			       OMPIC_CTRL_IRQ_GEN |
> > +			       OMPIC_CTRL_DST(dst_cpu) |
> > +			       OMPIC_DATA(1));
> > +	}
> > +}
> > +
> > +irqreturn_t ompic_ipi_handler(int irq, void *dev_id)
> 
> This should be static.

OK

> > +{
> > +	unsigned int cpu = smp_processor_id();
> > +	unsigned long *pending_ops = &per_cpu(ops, cpu);
> > +	unsigned long ops;
> > +
> > +	ompic_writereg(ompic_base, OMPIC_CTRL(cpu), OMPIC_CTRL_IRQ_ACK);
> > +	while ((ops = xchg(pending_ops, 0)) != 0) {
> > +
> > +		/*
> > +		 * On OpenRISC the atomic xchg() call implies a memory
> > +		 * barrier.  Otherwise we may need an smp_rmb(); paired
> > +		 * with the write in ompic_raise_softirq.
> > +		 */
> > +
> > +		do {
> > +			unsigned long ipi_msg;
> > +
> > +			ipi_msg = __ffs(ops);
> > +			ops &= ~(1UL << ipi_msg);
> > +
> > +			handle_IPI(ipi_msg);
> > +		} while (ops);
> > +	}
> > +
> > +	return IRQ_HANDLED;
> > +}
> > +
> > +static struct irqaction ompi_ipi_irqaction = {
> > +	.handler =      ompic_ipi_handler,
> > +	.flags =        IRQF_PERCPU,
> > +	.name =         "ompic_ipi",
> > +};
> > +
> > +int __init ompic_of_init(struct device_node *node, struct device_node *parent)
> 
> static again.

OK

> > +{
> > +	struct resource res;
> > +	int irq;
> > +	int ret;
> > +
> > +	/* Validate the DT */
> > +	if (ompic_base) {
> > +		pr_err("ompic: duplicate ompic's are not supported");
> > +		return -EEXIST;
> > +	}
> > +
> > +	if (of_address_to_resource(node, 0, &res)) {
> > +		pr_err("ompic: reg property requires an address and size");
> > +		return -EINVAL;
> > +	}
> > +
> > +	if (resource_size(&res) < (num_possible_cpus() * OMPIC_CPUBYTES)) {
> > +		pr_err("ompic: reg size, currently %d must be at least %d",
> > +			resource_size(&res),
> > +			(num_possible_cpus() * OMPIC_CPUBYTES));
> > +		return -EINVAL;
> > +	}
> > +
> > +	/* Setup the device */
> > +	ompic_base = ioremap(res.start, resource_size(&res));
> > +	if (IS_ERR(ompic_base)) {
> > +		pr_err("ompic: unable to map registers");
> > +		return PTR_ERR(ompic_base);
> > +	}
> > +
> > +	irq = irq_of_parse_and_map(node, 0);
> > +	if (irq <= 0) {
> > +		pr_err("ompic: unable to parse device irq");
> > +		ret = -EINVAL;
> > +		goto out_unmap;
> > +	}
> > +
> > +	ret = setup_irq(irq, &ompi_ipi_irqaction);
> > +	if (ret)
> > +		goto out_irq_disp;
> > +
> > +	set_smp_cross_call(ompic_raise_softirq);
> > +
> > +	return 0;
> > +
> > +out_irq_disp:
> > +	irq_dispose_mapping(irq);
> > +out_unmap:
> > +	iounmap(ompic_base);
> > +	ompic_base = NULL;
> > +	return ret;
> > +}
> > +IRQCHIP_DECLARE(ompic, "openrisc,ompic", ompic_of_init);
>

Thanks for your time!

 -Stafford

ps: Frank Zappa rocks :)

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#1732498 — Re: [PATCH v2 06/14] irqchip: add initial support for ompic

From	Marc Zyngier <marc.zyngier@arm.com>
Date	2017-09-14 20:40 +0200
Subject	Re: [PATCH v2 06/14] irqchip: add initial support for ompic
Message-ID	<upHdn-aN-1@gated-at.bofh.it>
In reply to	#1732071

On Thu, Sep 14 2017 at  3:54:02 pm BST, Stafford Horne <shorne@gmail.com> wrote:
> On Wed, Sep 13, 2017 at 06:21:39PM +0100, Marc Zyngier wrote:

[...]

>> > +{
>> > +	unsigned int dst_cpu;
>> > +	unsigned int src_cpu = smp_processor_id();
>> > +
>> > +	for_each_cpu(dst_cpu, mask) {
>> > +		set_bit(ipi_msg, &per_cpu(ops, dst_cpu));
>> > +
>> > +		/*
>> > +		 * On OpenRISC the atomic set_bit() call implies a memory
>> > +		 * barrier.  Otherwise we would need: smp_wmb(); paired
>> > +		 * with the read in ompic_ipi_handler.
>> > +		 */
>> 
>> One last question on this, because the architecture document is terribly
>> unclear: If you have CPU0 doing an atomic operation A0, CPU1 seeing A0
>> and doeing another atomic A1 (the set_bit above) followed by an IPI to
>> CPU2, is CPU2 *guaranteed* to observe both A0 *and* A1? Because that's
>> required by the IPI semantics, and you wouldn't see that kind of issue
>> with only two CPUs.
>
> Could you suggest an architecture document that makes this case clear?
>
> I believe this will not be a problem, but:
>   1. If this needs to be clear in the architecture document I can propose
>      changes.
>   2. To be clear is this the scenario you mean..
>
> CASE1 - A0 and A1 are to different locations?
>   A0 - writes to some unrelated global location?
>
> CPU0                       CPU1                     CPU2
>  A0:atomic store (global)
>                            A1:set_bit (ops[CPU2])
>                            IPI
>                                                     read (A0,A1)
>
>
> OR
>
> CASE2 - A0 and A1 are to the same location.
>   A0 - writes to the same location as A1
>
> CPU0                       CPU1                     CPU2
>  A0:set_bit (ops[CPU2])
>                            A1:set_bit (ops[CPU2])
>                            IPI
>                                                     read (A0,A1)
>  IPI

I think this covers both cases I had in mind.

>
>
> OR - something else?
>
> In both cases CPU2 would be able to see the results of both atomic
> operations.  All, cpus in the OpenRISC system snoop for memory writes to
> enable cash coherency, so each CPU would see each write once it is synced
> to memory (there is a single memory bus).  This is not limited to atomic
> operations, but the atomic operations provide a syncrhonization point
> accross all CPUs.

OK. It would be good if the architecture document had something about
transitivity of writes on SMP (maybe it has, I only went through it
pretty quickly). But overall, the above will work correctly.

> ps: Frank Zappa rocks :)

His music certainly does! ;-)

Thanks,

        M.
-- 
Jazz is not dead. It just smells funny.

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#1734460 — Re: [PATCH v2 06/14] irqchip: add initial support for ompic

From	Rob Herring <robh@kernel.org>
Date	2017-09-18 22:40 +0200
Subject	Re: [PATCH v2 06/14] irqchip: add initial support for ompic
Message-ID	<uraZH-2S2-7@gated-at.bofh.it>
In reply to	#1732071

On Thu, Sep 14, 2017 at 03:54:02PM +0900, Stafford Horne wrote:
> On Wed, Sep 13, 2017 at 06:21:39PM +0100, Marc Zyngier wrote:
> > On Sun, Sep 10 2017 at  3:49:18 pm BST, Stafford Horne <shorne@gmail.com> wrote:
> > > From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> > >
> > > IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as
> > > described in the Multicore support section of the OpenRISC 1.2
> > > proposed architecture specification:
> > >
> > >   https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-rev0.pdf
> > >
> > > Each OpenRISC core contains a full interrupt controller which is used in
> > > the SMP architecture for interrupt balancing.  This IPI device, the
> > > ompic, is the only external device required for enabling SMP on
> > > OpenRISC.
> > >
> > > Pending ops are stored in a memory bit mask which can allow multiple
> > > pending operations to be set and serviced at a time. This is mostly
> > > borrowed from the alpha IPI implementation.
> > >
> > > Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> > > [shorne@gmail.com: converted ops to bitmask, wrote commit message]
> > > Signed-off-by: Stafford Horne <shorne@gmail.com>
> > > ---
> > >
> > > Changes since v1
> > >  - Added openrisc, prefix
> > >  - Clarified 8 bytes per cpu
> > >  - Removed #interrupt-cells as this will not be an irq parent
> > >  - Changed ops to be percpu
> > >  - Added DTS and intialization failure validations
> > >
> > >  .../interrupt-controller/openrisc,ompic.txt        |  19 ++
> > >  arch/openrisc/Kconfig                              |   1 +
> > >  drivers/irqchip/Kconfig                            |   3 +
> > >  drivers/irqchip/Makefile                           |   1 +
> > >  drivers/irqchip/irq-ompic.c                        | 205 +++++++++++++++++++++
> > >  5 files changed, 229 insertions(+)
> > >  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt
> > >  create mode 100644 drivers/irqchip/irq-ompic.c
> > >
> > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt b/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt
> > > new file mode 100644
> > > index 000000000000..346e6042d62f
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt
> > > @@ -0,0 +1,19 @@
> > > +Open Multi-Processor Interrupt Controller
> > > +
> > > +Required properties:
> > > +
> > > +- compatible : This should be "openrisc,ompic"
> > > +- reg : Specifies base physical address and size of the register space. The
> > > +  size is based on the number of cores the controller has been configured
> > > +  to handle, this should be set to 8 bytes per cpu core.
> > > +- interrupt-controller : Identifies the node as an interrupt controller
> > > +- interrupts : Specifies the interrupt line to which the ompic is wired.
> > > +
> > > +Example:
> > > +
> > > +ompic: ompic {
> > > +	compatible = "openrisc,ompic";
> > > +	reg = <0x98000000 16>;
> > > +	interrupt-controller;
> > > +	interrupts = <1>;
> > > +};
> > > diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig
> > > index b49acda5e8f4..34eb4e90f56c 100644
> > > --- a/arch/openrisc/Kconfig
> > > +++ b/arch/openrisc/Kconfig
> > > @@ -30,6 +30,7 @@ config OPENRISC
> > >  	select NO_BOOTMEM
> > >  	select ARCH_USE_QUEUED_SPINLOCKS
> > >  	select ARCH_USE_QUEUED_RWLOCKS
> > > +	select OMPIC if SMP
> > >  
> > >  config CPU_BIG_ENDIAN
> > >  	def_bool y
> > > diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> > > index f1fd5f44d1d4..0e4c96c90b86 100644
> > > --- a/drivers/irqchip/Kconfig
> > > +++ b/drivers/irqchip/Kconfig
> > > @@ -145,6 +145,9 @@ config CLPS711X_IRQCHIP
> > >  	select SPARSE_IRQ
> > >  	default y
> > >  
> > > +config OMPIC
> > > +	bool
> > > +
> > >  config OR1K_PIC
> > >  	bool
> > >  	select IRQ_DOMAIN
> > > diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> > > index e88d856cc09c..123047d7a20d 100644
> > > --- a/drivers/irqchip/Makefile
> > > +++ b/drivers/irqchip/Makefile
> > > @@ -17,6 +17,7 @@ obj-$(CONFIG_DW_APB_ICTL)		+= irq-dw-apb-ictl.o
> > >  obj-$(CONFIG_METAG)			+= irq-metag-ext.o
> > >  obj-$(CONFIG_METAG_PERFCOUNTER_IRQS)	+= irq-metag.o
> > >  obj-$(CONFIG_CLPS711X_IRQCHIP)		+= irq-clps711x.o
> > > +obj-$(CONFIG_OMPIC)			+= irq-ompic.o
> > >  obj-$(CONFIG_OR1K_PIC)			+= irq-or1k-pic.o
> > >  obj-$(CONFIG_ORION_IRQCHIP)		+= irq-orion.o
> > >  obj-$(CONFIG_OMAP_IRQCHIP)		+= irq-omap-intc.o
> > > diff --git a/drivers/irqchip/irq-ompic.c b/drivers/irqchip/irq-ompic.c
> > > new file mode 100644
> > > index 000000000000..cd2616b6639b
> > > --- /dev/null
> > > +++ b/drivers/irqchip/irq-ompic.c
> > > @@ -0,0 +1,205 @@
> > > +/*
> > > + * Open Multi-Processor Interrupt Controller driver
> > > + *
> > > + * Copyright (C) 2014 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> > > + * Copyright (C) 2017 Stafford Horne <shorne@gmail.com>
> > > + *
> > > + * This file is licensed under the terms of the GNU General Public License
> > > + * version 2.  This program is licensed "as is" without any warranty of any
> > > + * kind, whether express or implied.
> > > + *
> > > + * The ompic device handles IPI communication because cores in mulicore
> > > + * OpenRISC systems.
> > 
> > Should the above read "between cores"?
> 
> Yes, it should be, I am bad with these kind of typos.

And "multi-core"

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#1734851 — Re: [PATCH v2 06/14] irqchip: add initial support for ompic

From	Stafford Horne <shorne@gmail.com>
Date	2017-09-19 14:20 +0200
Subject	Re: [PATCH v2 06/14] irqchip: add initial support for ompic
Message-ID	<urpFn-5m4-5@gated-at.bofh.it>
In reply to	#1734460

On Mon, Sep 18, 2017 at 03:29:58PM -0500, Rob Herring wrote:
> On Thu, Sep 14, 2017 at 03:54:02PM +0900, Stafford Horne wrote:
> > On Wed, Sep 13, 2017 at 06:21:39PM +0100, Marc Zyngier wrote:
> > > On Sun, Sep 10 2017 at  3:49:18 pm BST, Stafford Horne <shorne@gmail.com> wrote:
> > > > From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> > > >
[..]
> > > > diff --git a/drivers/irqchip/irq-ompic.c b/drivers/irqchip/irq-ompic.c
> > > > new file mode 100644
> > > > index 000000000000..cd2616b6639b
> > > > --- /dev/null
> > > > +++ b/drivers/irqchip/irq-ompic.c
> > > > @@ -0,0 +1,205 @@
> > > > +/*
> > > > + * Open Multi-Processor Interrupt Controller driver
> > > > + *
> > > > + * Copyright (C) 2014 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
> > > > + * Copyright (C) 2017 Stafford Horne <shorne@gmail.com>
> > > > + *
> > > > + * This file is licensed under the terms of the GNU General Public License
> > > > + * version 2.  This program is licensed "as is" without any warranty of any
> > > > + * kind, whether express or implied.
> > > > + *
> > > > + * The ompic device handles IPI communication because cores in mulicore
> > > > + * OpenRISC systems.
> > > 
> > > Should the above read "between cores"?
> > 
> > Yes, it should be, I am bad with these kind of typos.
> 
> And "multi-core"

Thanks, and I have many s/multicore/multi-core/ issues throughout the patch
series as well.

-Stafford

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Page 1 of 2 [1] 2 Next page →

csiph-web

[PATCH v2 00/14] OpenRISC SMP Support

Contents

#1729919 — [PATCH v2 00/14] OpenRISC SMP Support

#1729920 — [PATCH v2 10/14] openrisc: add cacheflush support to fix icache aliasing

#1729921 — [PATCH v2 11/14] openrisc: add simple_smp dts and defconfig for simulators

#1729922 — [PATCH v2 09/14] openrisc: sleep instead of spin on secondary wait

#1729923 — [PATCH v2 13/14] openrisc: enable LOCKDEP_SUPPORT and irqflags tracing

#1729924 — [PATCH v2 03/14] openrisc: add 1 and 2 byte cmpxchg support

#1729926 — [PATCH v2 02/14] openrisc: define CPU_BIG_ENDIAN as true

#1729927 — [PATCH v2 12/14] openrisc: support framepointers and STACKTRACE_SUPPORT

#1729928 — [PATCH v2 08/14] openrisc: fix initial preempt state for secondary cpu tasks

#1729929 — [PATCH v2 01/14] openrisc: use shadow registers to save regs on exception

#1729930 — [PATCH v2 04/14] openrisc: use qspinlocks and qrwlocks

#1729931 — [PATCH v2 05/14] dt-bindings: add openrisc to vendor prefixes list

#1729957 — Re: [PATCH v2 05/14] dt-bindings: add openrisc to vendor prefixes list

#1734461 — Re: [PATCH v2 05/14] dt-bindings: add openrisc to vendor prefixes list

#1729932 — [PATCH v2 06/14] irqchip: add initial support for ompic

#1731741 — Re: [PATCH v2 06/14] irqchip: add initial support for ompic

#1732071 — Re: [PATCH v2 06/14] irqchip: add initial support for ompic

#1732498 — Re: [PATCH v2 06/14] irqchip: add initial support for ompic

#1734460 — Re: [PATCH v2 06/14] irqchip: add initial support for ompic

#1734851 — Re: [PATCH v2 06/14] irqchip: add initial support for ompic