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Re: [PATCH] arm64: KVM: VHE: reset PSTATE.UAO when switch to host

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  Re: [PATCH] arm64: KVM: VHE: reset PSTATE.UAO when switch to host gengdongjiu <gengdongjiu@huawei.com> - 2017-09-07 17:10 +0200
    Re: [PATCH] arm64: KVM: VHE: reset PSTATE.UAO when switch to host Marc Zyngier <marc.zyngier@arm.com> - 2017-09-07 17:30 +0200
      Re: [PATCH] arm64: KVM: VHE: reset PSTATE.UAO when switch to host gengdongjiu <gengdongjiu@huawei.com> - 2017-09-08 09:30 +0200
        Re: [PATCH] arm64: KVM: VHE: reset PSTATE.UAO when switch to host Marc Zyngier <marc.zyngier@arm.com> - 2017-09-08 10:30 +0200
          Re: [PATCH] arm64: KVM: VHE: reset PSTATE.UAO when switch to host gengdongjiu <gengdongjiu@huawei.com> - 2017-09-08 11:10 +0200
            Re: [PATCH] arm64: KVM: VHE: reset PSTATE.UAO when switch to host Marc Zyngier <marc.zyngier@arm.com> - 2017-09-08 14:20 +0200

#1728258 — Re: [PATCH] arm64: KVM: VHE: reset PSTATE.UAO when switch to host

> On 07/09/17 12:49, gengdongjiu wrote:
> >
> >
> > On 2017/9/7 18:13, Marc Zyngier wrote:
> >> On 07/09/17 11:05, gengdongjiu wrote:
> >>> Hi James,
> >>>
> >>> On 2017/9/7 17:20, James Morse wrote:
> >>>> Hi Dongjiu Geng,
> >>>>
> >>>> On 07/09/17 06:54, Dongjiu Geng wrote:
> >>>>> In VHE mode, host kernel runs in the EL2 and can enable 'User
> >>>>> Access Override' when fs==KERNEL_DS so that it can access kernel
> >>>>> memory. However, PSTATE.UAO is set to 0 on an exception taken from
> >>>>> EL1 to EL2. Thus when VHE is used and exception taken from a guest
> >>>>> UAO will be disabled and host will use the incorrect PSTATE.UAO.
> >>>>> So check and reset the PSTATE.UAO when switching to host.
> >>>>
> >>>> This would only be a problem if KVM were calling into world-switch
> >>>> with fs==KERNEL_DS. I can't see where this happens.
> >>>  Not only KVM, may also kernel sets the fs == KERNEL_DS before
> >>> calling into world-switch
> >>
> >> How? Please describe the exact sequence of event that lead to this
> >> situation with the current code base.
> >
> > Hi Marc,
> >
> >    Different tasks have different fs, such as USER_DS or KERNEL_DS. In
> > the context switch, it will restore the task's fs. Thus, that depends
> > on task itself, as shown below code. UAO is different with PAN, PAN will be always enabled if hardware CPU supports PAN feature, but
> UAO is dynamical change.
> 
> You haven't answered my question: There is exactly one point where we enter the world-switch. Show me that, at this point, PSTATE.UAO
> *before* the call is different from PSTATE.UAO after the call. Give me the exact sequence of event that leads to this situation. Show me a
> stack trace.

Hi Marc,

  If using current mainline KVM code + Qemu and modify nothing, may not exist broken issue,  because the Qemu progress FS should be USER_DS. But if I make a modification for user space( Qemu or KVM tools) to change its FS property to KERNEL_DS or use third party application with KERNEL_DS FS to run the guest, it will have problem(the KERNEL_DS is cleared). If you think my case is reasonable and should support, I can show you the calling stack trace. If you think, my case is not reasonable and KVM should not support the application with KERNEL_DS fs to run guest. You can ignore this patch, thanks.


> 
> Until you do this, I will ignore any further comment coming from you on this subject.
> 
> Thanks,
> 
> 	M.
> --
> Jazz is not dead. It just smells funny...

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#1728269

On 07/09/17 16:03, gengdongjiu wrote:
>> On 07/09/17 12:49, gengdongjiu wrote:
>>>
>>>
>>> On 2017/9/7 18:13, Marc Zyngier wrote:
>>>> On 07/09/17 11:05, gengdongjiu wrote:
>>>>> Hi James,
>>>>>
>>>>> On 2017/9/7 17:20, James Morse wrote:
>>>>>> Hi Dongjiu Geng,
>>>>>>
>>>>>> On 07/09/17 06:54, Dongjiu Geng wrote:
>>>>>>> In VHE mode, host kernel runs in the EL2 and can enable 'User
>>>>>>> Access Override' when fs==KERNEL_DS so that it can access kernel
>>>>>>> memory. However, PSTATE.UAO is set to 0 on an exception taken from
>>>>>>> EL1 to EL2. Thus when VHE is used and exception taken from a guest
>>>>>>> UAO will be disabled and host will use the incorrect PSTATE.UAO.
>>>>>>> So check and reset the PSTATE.UAO when switching to host.
>>>>>>
>>>>>> This would only be a problem if KVM were calling into world-switch
>>>>>> with fs==KERNEL_DS. I can't see where this happens.
>>>>>  Not only KVM, may also kernel sets the fs == KERNEL_DS before
>>>>> calling into world-switch
>>>>
>>>> How? Please describe the exact sequence of event that lead to this
>>>> situation with the current code base.
>>>
>>> Hi Marc,
>>>
>>>    Different tasks have different fs, such as USER_DS or KERNEL_DS. In
>>> the context switch, it will restore the task's fs. Thus, that depends
>>> on task itself, as shown below code. UAO is different with PAN, PAN will be always enabled if hardware CPU supports PAN feature, but
>> UAO is dynamical change.
>>
>> You haven't answered my question: There is exactly one point where we enter the world-switch. Show me that, at this point, PSTATE.UAO
>> *before* the call is different from PSTATE.UAO after the call. Give me the exact sequence of event that leads to this situation. Show me a
>> stack trace.
> 
> Hi Marc,
> 
> If using current mainline KVM code + Qemu and modify nothing, may not
> exist broken issue,  because the Qemu progress FS should be USER_DS.

Thanks. You've just been wasting everybody's time for two days. In case
you haven't noticed, mainline KVM code is the *ONLY* thing we care about.

> But if I make a modification for user space( Qemu or KVM tools) to
> change its FS property to KERNEL_DS or use third party application
> with KERNEL_DS FS to run the guest, it will have problem(the
> KERNEL_DS is cleared). If you think my case is reasonable and should
> support, I can show you the calling stack trace. If you think, my
> case is not reasonable and KVM should not support the application
> with KERNEL_DS fs to run guest. You can ignore this patch, thanks.

I really cannot think of a good reason why we'd want to do that. Playing
with set_fs() is almost universally wrong, and I'm certainly going to
oppose to any change in that area unless the code that calls set_fs()
has been made public and properly reviewed. Until then, UAO/PAN will
stay as they are unless you prove that our current code is wrong.

	M.
-- 
Jazz is not dead. It just smells funny...

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#1728658

On 2017/9/7 23:23, Marc Zyngier wrote:
> On 07/09/17 16:03, gengdongjiu wrote:
>>> On 07/09/17 12:49, gengdongjiu wrote:
>>>>
[...]

> 
> I really cannot think of a good reason why we'd want to do that. Playing
> with set_fs() is almost universally wrong, and I'm certainly going to
> oppose to any change in that area unless the code that calls set_fs()
> has been made public and properly reviewed. Until then, UAO/PAN will
> stay as they are unless you prove that our current code is wrong.

Marc,

sorry I have another question for the PAN.

In the non-VHE mode, The host kernel is running in the EL1. Before host kernel enter guest, host OS will call 'HVC' instruction to do the world-switch,
and the pstate.PAN will be saved into the SPSR_EL2. When world-switch back to host kernel from EL2, it will call 'eret' instruction to EL1 host,
this 'eret' instruction will restore the SPSR_EL2 to the PSTATE. so the PSTATE.PAN will be restored.

For the Non-VHE mode, in the EL2 where mainly have word-switch code, do you think it needs to reset the PSTATE.PAN? From the spec, it does not provide SCTLR_EL2.SPAN bit for non-VHE mode,
so reset the PSTATE.PAN does not sure whether it is needed or whether affects the performance. If you think it is needed for El2 in Non-VHE mode, moving the reset PSTATE.PAN to
the exception entry to EL2 may be better, such as "el1_sync", because host can also call 'hvc' instruction without guest running.

> 
> 	M.
> 

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#1728686

On Fri, 8 Sep 2017 15:19:21 +0800
gengdongjiu <gengdongjiu@huawei.com> wrote:

> On 2017/9/7 23:23, Marc Zyngier wrote:
> > On 07/09/17 16:03, gengdongjiu wrote:  
> >>> On 07/09/17 12:49, gengdongjiu wrote:  
> >>>>  
> [...]
> 
> > 
> > I really cannot think of a good reason why we'd want to do that. Playing
> > with set_fs() is almost universally wrong, and I'm certainly going to
> > oppose to any change in that area unless the code that calls set_fs()
> > has been made public and properly reviewed. Until then, UAO/PAN will
> > stay as they are unless you prove that our current code is wrong.  
> 
> Marc,
> 
> sorry I have another question for the PAN.
> 
> In the non-VHE mode, The host kernel is running in the EL1. Before
> host kernel enter guest, host OS will call 'HVC' instruction to do
> the world-switch, and the pstate.PAN will be saved into the SPSR_EL2.
> When world-switch back to host kernel from EL2, it will call 'eret'
> instruction to EL1 host, this 'eret' instruction will restore the
> SPSR_EL2 to the PSTATE. so the PSTATE.PAN will be restored.
> 
> For the Non-VHE mode, in the EL2 where mainly have word-switch code,
> do you think it needs to reset the PSTATE.PAN? From the spec, it does
> not provide SCTLR_EL2.SPAN bit for non-VHE mode, so reset the
> PSTATE.PAN does not sure whether it is needed or whether affects the
> performance. If you think it is needed for El2 in Non-VHE mode,
> moving the reset PSTATE.PAN to the exception entry to EL2 may be
> better, such as "el1_sync", because host can also call 'hvc'
> instruction without guest running.

So let's see if I correctly understand your question:

You're worried that we don't set/reset PSTATE.PAN at EL2 in non-VHE?
In non-VHE, there is no user-space mapping that is present at the
same time as the hypervisor mappings. Actually, we hardly have any
mapping other than the HYP text/data and the vcpu/vm structures.

So how is PAN relevant in this context? What does it even mean?
If you have a ARMv8.0 behaviour, PAN doesn't even seem to *exist* at
EL2.

Or am I completely missing the point here?

	M.
-- 
Without deviation from the norm, progress is not possible.

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#1728711

Marc,
   Thanks for reply.

On 2017/9/8 16:21, Marc Zyngier wrote:
>> Marc,
>>
>> sorry I have another question for the PAN.
>>
>> In the non-VHE mode, The host kernel is running in the EL1. Before
>> host kernel enter guest, host OS will call 'HVC' instruction to do
>> the world-switch, and the pstate.PAN will be saved into the SPSR_EL2.
>> When world-switch back to host kernel from EL2, it will call 'eret'
>> instruction to EL1 host, this 'eret' instruction will restore the
>> SPSR_EL2 to the PSTATE. so the PSTATE.PAN will be restored.
>>
>> For the Non-VHE mode, in the EL2 where mainly have word-switch code,
>> do you think it needs to reset the PSTATE.PAN? From the spec, it does
>> not provide SCTLR_EL2.SPAN bit for non-VHE mode, so reset the
>> PSTATE.PAN does not sure whether it is needed or whether affects the
>> performance. If you think it is needed for El2 in Non-VHE mode,
>> moving the reset PSTATE.PAN to the exception entry to EL2 may be
>> better, such as "el1_sync", because host can also call 'hvc'
>> instruction without guest running.
> So let's see if I correctly understand your question:
> 
> You're worried that we don't set/reset PSTATE.PAN at EL2 in non-VHE?
> In non-VHE, there is no user-space mapping that is present at the
> same time as the hypervisor mappings. Actually, we hardly have any
> mapping other than the HYP text/data and the vcpu/vm structures.

Not that meaning.
there are two meanings:

In short, we should not set PAN for El2 in non-VHE; If you think we should, current code does not cover all scenarios.


1. In the current mainline code it sets the PSTATE.PAN at EL2 in non-VHE. As you said,
in non-VHE, there is no user-space mapping that is present at the same time as the
hypervisor mappings, so I think it may not need to set both for EL1 and El2 in non-VHE,
but current code sets it. As you see[1], the code does not check VHE.

2. Conversely, in non-VHE, if you think we should set PAN in the EL2,
current code only sets it in the guest_exit path, do not cover all scenarios.
For example, when there is no guest, only have host, host calling 'HVC' instruction enter to El2 to do somethings,
then it will not call the guest_exit, so the PAN will not be set.
In order to handle this case, we should move it to the 'el1_sync'


ENTRY(__guest_exit)
        // x0: return code
        // x1: vcpu
        // x2-x29,lr: vcpu regs
        // vcpu x0-x1 on the stack

        add     x1, x1, #VCPU_CONTEXT

        ALTERNATIVE(nop, SET_PSTATE_PAN(1), ARM64_HAS_PAN, CONFIG_ARM64_PAN)  	[1]

        // Store the guest regs x2 and x3
        stp     x2, x3,   [x1, #CPU_XREG_OFFSET(2)]

        // Retrieve the guest regs x0-x1 from the stack
        ldp     x2, x3, [sp], #16       // x0, x1


> 
> So how is PAN relevant in this context? What does it even mean?
> If you have a ARMv8.0 behaviour, PAN doesn't even seem to *exist* at
> EL2.
> 
> Or am I completely missing the point here?

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#1728786

On 08/09/17 10:05, gengdongjiu wrote:
> Marc,
>    Thanks for reply.
> 
> On 2017/9/8 16:21, Marc Zyngier wrote:
>>> Marc,
>>>
>>> sorry I have another question for the PAN.
>>>
>>> In the non-VHE mode, The host kernel is running in the EL1. Before
>>> host kernel enter guest, host OS will call 'HVC' instruction to do
>>> the world-switch, and the pstate.PAN will be saved into the SPSR_EL2.
>>> When world-switch back to host kernel from EL2, it will call 'eret'
>>> instruction to EL1 host, this 'eret' instruction will restore the
>>> SPSR_EL2 to the PSTATE. so the PSTATE.PAN will be restored.
>>>
>>> For the Non-VHE mode, in the EL2 where mainly have word-switch code,
>>> do you think it needs to reset the PSTATE.PAN? From the spec, it does
>>> not provide SCTLR_EL2.SPAN bit for non-VHE mode, so reset the
>>> PSTATE.PAN does not sure whether it is needed or whether affects the
>>> performance. If you think it is needed for El2 in Non-VHE mode,
>>> moving the reset PSTATE.PAN to the exception entry to EL2 may be
>>> better, such as "el1_sync", because host can also call 'hvc'
>>> instruction without guest running.
>> So let's see if I correctly understand your question:
>>
>> You're worried that we don't set/reset PSTATE.PAN at EL2 in non-VHE?
>> In non-VHE, there is no user-space mapping that is present at the
>> same time as the hypervisor mappings. Actually, we hardly have any
>> mapping other than the HYP text/data and the vcpu/vm structures.
> 
> Not that meaning.
> there are two meanings:
> 
> In short, we should not set PAN for El2 in non-VHE; If you think we should, current code does not cover all scenarios.
> 
> 
> 1. In the current mainline code it sets the PSTATE.PAN at EL2 in non-VHE. As you said,
> in non-VHE, there is no user-space mapping that is present at the same time as the
> hypervisor mappings, so I think it may not need to set both for EL1 and El2 in non-VHE,
> but current code sets it. As you see[1], the code does not check VHE.
> 
> 2. Conversely, in non-VHE, if you think we should set PAN in the EL2,

It is not about what I think. It is about what the architecture gives you.

There cannot be any userspace mapping at EL2 when non-VHE, so there
cannot be any valid PAN setting. I repeat: there is not such thing as
PAN at EL2 when HCR_EL2.E2H==0. This bit *has no effect*. Just read the
documentation (ARM DDI 0487B.a, D4.4.2).

If you're going to change this kind of code, please start by
understanding the architecture.

	M.
-- 
Jazz is not dead. It just smells funny...

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