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Groups > linux.kernel > #1723384 > unrolled thread

[PATCH v3 0/3] Workaround for bus/slot reset on Cavium cn8xxx root ports

Started byJan Glauber <jglauber@cavium.com>
First post2017-08-30 16:30 +0200
Last post2017-08-30 16:30 +0200
Articles 2 — 1 participant

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  [PATCH v3 0/3] Workaround for bus/slot reset on Cavium cn8xxx root ports Jan Glauber <jglauber@cavium.com> - 2017-08-30 16:30 +0200
    [PATCH v3 1/3] PCI: Allow PCI_DEV_FLAGS_NO_BUS_RESET to be used on bus device Jan Glauber <jglauber@cavium.com> - 2017-08-30 16:30 +0200

#1723384 — [PATCH v3 0/3] Workaround for bus/slot reset on Cavium cn8xxx root ports

FromJan Glauber <jglauber@cavium.com>
Date2017-08-30 16:30 +0200
Subject[PATCH v3 0/3] Workaround for bus/slot reset on Cavium cn8xxx root ports
Message-ID<ukcad-ZN-3@gated-at.bofh.it>
Using vfio-pci on a combination of cn8xxx and some PCI devices results in
a kernel panic. This is triggered by issuing a bus or a slot reset
on the PCI device.

The solution is to prevent the reset. I've dropped the vfio patch from the
previous series as vfio-pci already checks in the reset path for
pci_bus_resetable() and pci_slot_resetable().

With this series both checks indicate that the reset is not possible
preventing the kernel panic.

David Daney (2):
  PCI: Allow PCI_DEV_FLAGS_NO_BUS_RESET to be used on bus device
  PCI: Avoid bus reset for Cavium cn8xxx root ports

Jan Glauber (1):
  PCI: Avoid slot reset for Cavium cn8xxx root ports

 drivers/pci/pci.c    |  4 ++++
 drivers/pci/quirks.c | 24 ++++++++++++++++++++++++
 2 files changed, 28 insertions(+)

-- 
2.9.0.rc0.21.g7777322

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#1723390 — [PATCH v3 1/3] PCI: Allow PCI_DEV_FLAGS_NO_BUS_RESET to be used on bus device

FromJan Glauber <jglauber@cavium.com>
Date2017-08-30 16:30 +0200
Subject[PATCH v3 1/3] PCI: Allow PCI_DEV_FLAGS_NO_BUS_RESET to be used on bus device
Message-ID<ukcaf-ZN-35@gated-at.bofh.it>
In reply to#1723384
From: David Daney <david.daney@cavium.com>

When checking to see if a PCI bus can safely be reset, we check to see
if any of the children have their PCI_DEV_FLAGS_NO_BUS_RESET flag set.
As these devices are known not to behave well after a bus reset.

Some PCIe root port bridges also do not behave well after a bus reset,
sometimes causing the devices behind the bridge to become unusable.

Add a check for the PCI_DEV_FLAGS_NO_BUS_RESET flag being set in the
bridge device to allow these bridges to be flagged, and prevent their
buses from being reset.

A follow on patch will add a quirk for this type of bridge.

Signed-off-by: David Daney <david.daney@cavium.com>
[jglauber@cavium.com: fixed typo]
Signed-off-by: Jan Glauber <jglauber@cavium.com>
---
 drivers/pci/pci.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index af0cc34..d9abbc9 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -4290,6 +4290,10 @@ static bool pci_bus_resetable(struct pci_bus *bus)
 {
 	struct pci_dev *dev;
 
+
+	if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
+		return false;
+
 	list_for_each_entry(dev, &bus->devices, bus_list) {
 		if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
 		    (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
-- 
2.9.0.rc0.21.g7777322

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