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| Started by | Alexey Brodkin <Alexey.Brodkin@synopsys.com> |
|---|---|
| First post | 2017-08-31 16:30 +0200 |
| Last post | 2017-08-31 18:40 +0200 |
| Articles | 3 — 2 participants |
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[PATCH] arc: Flush and invalidate caches on start Alexey Brodkin <Alexey.Brodkin@synopsys.com> - 2017-08-31 16:30 +0200
Re: [PATCH] arc: Flush and invalidate caches on start Alexey Brodkin <Alexey.Brodkin@synopsys.com> - 2017-08-31 18:40 +0200
Re: [PATCH] arc: Flush and invalidate caches on start Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2017-08-31 18:40 +0200
| From | Alexey Brodkin <Alexey.Brodkin@synopsys.com> |
|---|---|
| Date | 2017-08-31 16:30 +0200 |
| Subject | [PATCH] arc: Flush and invalidate caches on start |
| Message-ID | <ukyDL-6JK-11@gated-at.bofh.it> |
This is useful to make sure no stale data exists in caches after bootloaders. The worst thing could be some lines of cache were locked in a bootloader for example during DDR recalibration and never unlocked. This may lead to really unpredictable issues later down the line. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> --- arch/arc/kernel/head.S | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arc/kernel/head.S b/arch/arc/kernel/head.S index 8b90d25a15cc..04e28b664183 100644 --- a/arch/arc/kernel/head.S +++ b/arch/arc/kernel/head.S @@ -34,6 +34,10 @@ #endif sr r5, [ARC_REG_IC_CTRL] + ; Invalidate entire I$ + mov r5, 1 + sr r5, [ARC_REG_IC_IVIC] + 1: lr r5, [ARC_REG_DC_BCR] breq r5, 0, 1f ; D$ doesn't exist @@ -46,6 +50,18 @@ #endif sr r5, [ARC_REG_DC_CTRL] + ; Flush entire D$ + mov r5, 1 + sr r5, [ARC_REG_DC_FLSH] + ; Wait for flush operation to complete +1: + lr r5, [ARC_REG_DC_CTRL] + bbit1 r5, DC_CTRL_FLUSH_STATUS, 1b + + ; Invalidate entire D$ + mov r5, 1 + sr r5, [ARC_REG_DC_IVDC] + 1: .endm -- 2.11.0
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| From | Alexey Brodkin <Alexey.Brodkin@synopsys.com> |
|---|---|
| Date | 2017-08-31 18:40 +0200 |
| Message-ID | <ukAFA-7XG-19@gated-at.bofh.it> |
| In reply to | #1724285 |
Hi Vineet, On Thu, 2017-08-31 at 09:31 -0700, Vineet Gupta wrote: > On 08/31/2017 07:22 AM, Alexey Brodkin wrote: > > > > This is useful to make sure no stale data exists in caches after bootloaders. > > The worst thing could be some lines of cache were locked in a bootloader > > for example during DDR recalibration and never unlocked. This may lead > > to really unpredictable issues later down the line. > > > > Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> > > --- > > arch/arc/kernel/head.S | 16 ++++++++++++++++ > > 1 file changed, 16 insertions(+) > > > > diff --git a/arch/arc/kernel/head.S b/arch/arc/kernel/head.S > > index 8b90d25a15cc..04e28b664183 100644 > > --- a/arch/arc/kernel/head.S > > +++ b/arch/arc/kernel/head.S > > @@ -34,6 +34,10 @@ > > #endif > > sr r5, [ARC_REG_IC_CTRL] > > > > + ; Invalidate entire I$ > > + mov r5, 1 > > + sr r5, [ARC_REG_IC_IVIC] > > + > > 1: > > lr r5, [ARC_REG_DC_BCR] > > breq r5, 0, 1f ; D$ doesn't exist > > @@ -46,6 +50,18 @@ > > #endif > > sr r5, [ARC_REG_DC_CTRL] > > > > + ; Flush entire D$ > > + mov r5, 1 > > + sr r5, [ARC_REG_DC_FLSH] > > + ; Wait for flush operation to complete > > +1: > > + lr r5, [ARC_REG_DC_CTRL] > > + bbit1 r5, DC_CTRL_FLUSH_STATUS, 1b > > + > > + ; Invalidate entire D$ > > + mov r5, 1 > > + sr r5, [ARC_REG_DC_IVDC] > > + > > AFAIK uboot already flushes the caches before handing control over to kernel - so > why do we need it here. > If uboot is locking lines, it needs to fix that and not penalize the general case > with or w/o uboot ! U-Boot indeed flushes caches.. but doesn't invalidate them! And only invalidation unlocks locked lines. That indeed should be added in U-Boot but I'd say above stuff doesn't influence a lot code size or execution time while makes system more fool-proof. -Alexey
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| From | Vineet Gupta <Vineet.Gupta1@synopsys.com> |
|---|---|
| Date | 2017-08-31 18:40 +0200 |
| Message-ID | <ukAFA-7XG-21@gated-at.bofh.it> |
| In reply to | #1724285 |
On 08/31/2017 07:22 AM, Alexey Brodkin wrote: > This is useful to make sure no stale data exists in caches after bootloaders. > The worst thing could be some lines of cache were locked in a bootloader > for example during DDR recalibration and never unlocked. This may lead > to really unpredictable issues later down the line. > > Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> > --- > arch/arc/kernel/head.S | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/arch/arc/kernel/head.S b/arch/arc/kernel/head.S > index 8b90d25a15cc..04e28b664183 100644 > --- a/arch/arc/kernel/head.S > +++ b/arch/arc/kernel/head.S > @@ -34,6 +34,10 @@ > #endif > sr r5, [ARC_REG_IC_CTRL] > > + ; Invalidate entire I$ > + mov r5, 1 > + sr r5, [ARC_REG_IC_IVIC] > + > 1: > lr r5, [ARC_REG_DC_BCR] > breq r5, 0, 1f ; D$ doesn't exist > @@ -46,6 +50,18 @@ > #endif > sr r5, [ARC_REG_DC_CTRL] > > + ; Flush entire D$ > + mov r5, 1 > + sr r5, [ARC_REG_DC_FLSH] > + ; Wait for flush operation to complete > +1: > + lr r5, [ARC_REG_DC_CTRL] > + bbit1 r5, DC_CTRL_FLUSH_STATUS, 1b > + > + ; Invalidate entire D$ > + mov r5, 1 > + sr r5, [ARC_REG_DC_IVDC] > + AFAIK uboot already flushes the caches before handing control over to kernel - so why do we need it here. If uboot is locking lines, it needs to fix that and not penalize the general case with or w/o uboot ! -Vineet
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