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[patch V3 37/44] x86/idt: Move ist stack based traps to table init

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  [patch V3 37/44] x86/idt: Move ist stack based traps to table init Thomas Gleixner <tglx@linutronix.de> - 2017-08-28 09:00 +0200
    [tip:x86/apic] x86/idt: Move IST stack based traps to table init tip-bot for Thomas Gleixner <tipbot@zytor.com> - 2017-08-29 13:30 +0200
      [PATCH] x86/idt: Fix the X86_TRAP_BP gate Ingo Molnar <mingo@kernel.org> - 2017-09-01 10:30 +0200
        Re: [PATCH] x86/idt: Fix the X86_TRAP_BP gate Thomas Gleixner <tglx@linutronix.de> - 2017-09-01 11:10 +0200
        [tip:x86/apic] x86/idt: Fix the X86_TRAP_BP gate tip-bot for Ingo Molnar <tipbot@zytor.com> - 2017-09-01 11:20 +0200

#1721083 — [patch V3 37/44] x86/idt: Move ist stack based traps to table init

Initialize the IST based traps via a table

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
 arch/x86/include/asm/desc.h |    2 ++
 arch/x86/kernel/idt.c       |   22 ++++++++++++++++++++++
 arch/x86/kernel/traps.c     |    9 +--------
 3 files changed, 25 insertions(+), 8 deletions(-)

--- a/arch/x86/include/asm/desc.h
+++ b/arch/x86/include/asm/desc.h
@@ -509,9 +509,11 @@ extern void idt_setup_early_traps(void);
 
 #ifdef CONFIG_X86_64
 extern void idt_setup_early_pf(void);
+extern void idt_setup_ist_traps(void);
 extern void idt_setup_debugidt_traps(void);
 #else
 static inline void idt_setup_early_pf(void) { }
+static inline void idt_setup_ist_traps(void) { }
 static inline void idt_setup_debugidt_traps(void) { }
 #endif
 
--- a/arch/x86/kernel/idt.c
+++ b/arch/x86/kernel/idt.c
@@ -92,6 +92,20 @@ struct desc_ptr idt_descr __ro_after_ini
 gate_desc debug_idt_table[IDT_ENTRIES] __page_aligned_bss;
 
 /*
+ * The exceptions which use Interrupt stacks. They are setup after
+ * cpu_init() when the TSS has been initialized.
+ */
+static const __initdata struct idt_data ist_idts[] = {
+	ISTG(X86_TRAP_DB,	debug,		DEBUG_STACK),
+	ISTG(X86_TRAP_NMI,	nmi,		NMI_STACK),
+	ISTG(X86_TRAP_BP,	int3,		DEBUG_STACK),
+	ISTG(X86_TRAP_DF,	double_fault,	DOUBLEFAULT_STACK),
+#ifdef CONFIG_X86_MCE
+	ISTG(X86_TRAP_MC,	&machine_check,	MCE_STACK),
+#endif
+};
+
+/*
  * Override for the debug_idt. Same as the default, but with interrupt
  * stack set to DEFAULT_STACK (0). Required for NMI trap handling.
  */
@@ -158,6 +172,14 @@ void __init idt_setup_early_pf(void)
 }
 
 /**
+ * idt_setup_ist_traps - Initialize the idt table with traps using IST
+ */
+void __init idt_setup_ist_traps(void)
+{
+	idt_setup_from_table(idt_table, ist_idts, ARRAY_SIZE(ist_idts));
+}
+
+/**
  * idt_setup_debugidt_traps - Initialize the debug idt table with debug traps
  */
 void __init idt_setup_debugidt_traps(void)
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -979,14 +979,7 @@ void __init trap_init(void)
 	 */
 	cpu_init();
 
-	/*
-	 * X86_TRAP_DB and X86_TRAP_BP have been set
-	 * in early_trap_init(). However, ITS works only after
-	 * cpu_init() loads TSS. See comments in early_trap_init().
-	 */
-	set_intr_gate_ist(X86_TRAP_DB, &debug, DEBUG_STACK);
-	/* int3 can be called from all */
-	set_system_intr_gate_ist(X86_TRAP_BP, &int3, DEBUG_STACK);
+	idt_setup_ist_traps();
 
 	x86_init.irqs.trap_init();
 

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#1722371 — [tip:x86/apic] x86/idt: Move IST stack based traps to table init

Commit-ID:  90f6225fba0c732f3f5f9f5e265bdefa021ff12d
Gitweb:     http://git.kernel.org/tip/90f6225fba0c732f3f5f9f5e265bdefa021ff12d
Author:     Thomas Gleixner <tglx@linutronix.de>
AuthorDate: Mon, 28 Aug 2017 08:47:52 +0200
Committer:  Ingo Molnar <mingo@kernel.org>
CommitDate: Tue, 29 Aug 2017 12:07:27 +0200

x86/idt: Move IST stack based traps to table init

Initialize the IST based traps via a table.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Josh Poimboeuf <jpoimboe@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Steven Rostedt <rostedt@goodmis.org>
Link: http://lkml.kernel.org/r/20170828064959.091328949@linutronix.de
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
 arch/x86/include/asm/desc.h |  2 ++
 arch/x86/kernel/idt.c       | 22 ++++++++++++++++++++++
 arch/x86/kernel/traps.c     |  9 +--------
 3 files changed, 25 insertions(+), 8 deletions(-)

diff --git a/arch/x86/include/asm/desc.h b/arch/x86/include/asm/desc.h
index 930acd5..e624527 100644
--- a/arch/x86/include/asm/desc.h
+++ b/arch/x86/include/asm/desc.h
@@ -509,9 +509,11 @@ extern void idt_setup_early_traps(void);
 
 #ifdef CONFIG_X86_64
 extern void idt_setup_early_pf(void);
+extern void idt_setup_ist_traps(void);
 extern void idt_setup_debugidt_traps(void);
 #else
 static inline void idt_setup_early_pf(void) { }
+static inline void idt_setup_ist_traps(void) { }
 static inline void idt_setup_debugidt_traps(void) { }
 #endif
 
diff --git a/arch/x86/kernel/idt.c b/arch/x86/kernel/idt.c
index f5281b8..a6326fd 100644
--- a/arch/x86/kernel/idt.c
+++ b/arch/x86/kernel/idt.c
@@ -92,6 +92,20 @@ struct desc_ptr idt_descr __ro_after_init = {
 gate_desc debug_idt_table[IDT_ENTRIES] __page_aligned_bss;
 
 /*
+ * The exceptions which use Interrupt stacks. They are setup after
+ * cpu_init() when the TSS has been initialized.
+ */
+static const __initdata struct idt_data ist_idts[] = {
+	ISTG(X86_TRAP_DB,	debug,		DEBUG_STACK),
+	ISTG(X86_TRAP_NMI,	nmi,		NMI_STACK),
+	ISTG(X86_TRAP_BP,	int3,		DEBUG_STACK),
+	ISTG(X86_TRAP_DF,	double_fault,	DOUBLEFAULT_STACK),
+#ifdef CONFIG_X86_MCE
+	ISTG(X86_TRAP_MC,	&machine_check,	MCE_STACK),
+#endif
+};
+
+/*
  * Override for the debug_idt. Same as the default, but with interrupt
  * stack set to DEFAULT_STACK (0). Required for NMI trap handling.
  */
@@ -158,6 +172,14 @@ void __init idt_setup_early_pf(void)
 }
 
 /**
+ * idt_setup_ist_traps - Initialize the idt table with traps using IST
+ */
+void __init idt_setup_ist_traps(void)
+{
+	idt_setup_from_table(idt_table, ist_idts, ARRAY_SIZE(ist_idts));
+}
+
+/**
  * idt_setup_debugidt_traps - Initialize the debug idt table with debug traps
  */
 void __init idt_setup_debugidt_traps(void)
diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
index 1492bf5..293f5bd 100644
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -979,14 +979,7 @@ void __init trap_init(void)
 	 */
 	cpu_init();
 
-	/*
-	 * X86_TRAP_DB and X86_TRAP_BP have been set
-	 * in early_trap_init(). However, ITS works only after
-	 * cpu_init() loads TSS. See comments in early_trap_init().
-	 */
-	set_intr_gate_ist(X86_TRAP_DB, &debug, DEBUG_STACK);
-	/* int3 can be called from all */
-	set_system_intr_gate_ist(X86_TRAP_BP, &int3, DEBUG_STACK);
+	idt_setup_ist_traps();
 
 	x86_init.irqs.trap_init();
 

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#1724871 — [PATCH] x86/idt: Fix the X86_TRAP_BP gate

Hi Andrei,

* Andrei Vagin <avagin@virtuozzo.com> wrote:

> Hi Thomas,
> 
> We run CRIU tests for linux-next and today they detected an issue. I've
> bisected this problem and it looks like a problem is in this patch.

Ok, there appears to be a bug in that conversion - does the patch below fix the 
regression for you?

Thanks,

	Ingo

================================>
Subject: x86/idt: Fix the X86_TRAP_BP gate
From: Ingo Molnar <mingo@kernel.org>

Andrei Vagin reported a CRIU regression and bisected it back to:

  90f6225fba0c ("x86/idt: Move IST stack based traps to table init")

This table init conversion loses the system-gate property of X86_TRAP_BP
and erroneously moves it from DPL3 to DPL0.

Fix it.

Reported-by: Andrei Vagin <avagin@virtuozzo.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/kernel/idt.c | 6 +++++-
 arch/x86/kernel/idt.c |    6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

Index: tip/arch/x86/kernel/idt.c
===================================================================
--- tip.orig/arch/x86/kernel/idt.c
+++ tip/arch/x86/kernel/idt.c
@@ -44,6 +44,10 @@ struct idt_data {
 #define ISTG(_vector, _addr, _ist)			\
 	G(_vector, _addr, _ist, GATE_INTERRUPT, DPL0, __KERNEL_CS)
 
+/* System interrupt gate with interrupt stack */
+#define SISTG(_vector, _addr, _ist)			\
+	G(_vector, _addr, _ist, GATE_INTERRUPT, DPL3, __KERNEL_CS)
+
 /* Task gate */
 #define TSKG(_vector, _gdt)				\
 	G(_vector, NULL, DEFAULT_STACK, GATE_TASK, DPL0, _gdt << 3)
@@ -181,7 +185,7 @@ gate_desc debug_idt_table[IDT_ENTRIES] _
 static const __initdata struct idt_data ist_idts[] = {
 	ISTG(X86_TRAP_DB,	debug,		DEBUG_STACK),
 	ISTG(X86_TRAP_NMI,	nmi,		NMI_STACK),
-	ISTG(X86_TRAP_BP,	int3,		DEBUG_STACK),
+	SISTG(X86_TRAP_BP,	int3,		DEBUG_STACK),
 	ISTG(X86_TRAP_DF,	double_fault,	DOUBLEFAULT_STACK),
 #ifdef CONFIG_X86_MCE
 	ISTG(X86_TRAP_MC,	&machine_check,	MCE_STACK),

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#1724893 — Re: [PATCH] x86/idt: Fix the X86_TRAP_BP gate

On Fri, 1 Sep 2017, Ingo Molnar wrote:
> Subject: x86/idt: Fix the X86_TRAP_BP gate
> From: Ingo Molnar <mingo@kernel.org>
> 
> Andrei Vagin reported a CRIU regression and bisected it back to:
> 
>   90f6225fba0c ("x86/idt: Move IST stack based traps to table init")
> 
> This table init conversion loses the system-gate property of X86_TRAP_BP
> and erroneously moves it from DPL3 to DPL0.

Duh, yes. Thanks for spotting it.

> Fix it.
> 
> Reported-by: Andrei Vagin <avagin@virtuozzo.com>
> Cc: Linus Torvalds <torvalds@linux-foundation.org>
> Cc: Peter Zijlstra <peterz@infradead.org>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Signed-off-by: Ingo Molnar <mingo@kernel.org>
> ---
> arch/x86/kernel/idt.c | 6 +++++-
>  arch/x86/kernel/idt.c |    6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> Index: tip/arch/x86/kernel/idt.c
> ===================================================================
> --- tip.orig/arch/x86/kernel/idt.c
> +++ tip/arch/x86/kernel/idt.c
> @@ -44,6 +44,10 @@ struct idt_data {
>  #define ISTG(_vector, _addr, _ist)			\
>  	G(_vector, _addr, _ist, GATE_INTERRUPT, DPL0, __KERNEL_CS)
>  
> +/* System interrupt gate with interrupt stack */
> +#define SISTG(_vector, _addr, _ist)			\
> +	G(_vector, _addr, _ist, GATE_INTERRUPT, DPL3, __KERNEL_CS)
> +
>  /* Task gate */
>  #define TSKG(_vector, _gdt)				\
>  	G(_vector, NULL, DEFAULT_STACK, GATE_TASK, DPL0, _gdt << 3)
> @@ -181,7 +185,7 @@ gate_desc debug_idt_table[IDT_ENTRIES] _
>  static const __initdata struct idt_data ist_idts[] = {
>  	ISTG(X86_TRAP_DB,	debug,		DEBUG_STACK),
>  	ISTG(X86_TRAP_NMI,	nmi,		NMI_STACK),
> -	ISTG(X86_TRAP_BP,	int3,		DEBUG_STACK),
> +	SISTG(X86_TRAP_BP,	int3,		DEBUG_STACK),
>  	ISTG(X86_TRAP_DF,	double_fault,	DOUBLEFAULT_STACK),
>  #ifdef CONFIG_X86_MCE
>  	ISTG(X86_TRAP_MC,	&machine_check,	MCE_STACK),
> 

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#1724901 — [tip:x86/apic] x86/idt: Fix the X86_TRAP_BP gate

Commit-ID:  c6ef89421e236d75693ae968d80d44a52409889d
Gitweb:     http://git.kernel.org/tip/c6ef89421e236d75693ae968d80d44a52409889d
Author:     Ingo Molnar <mingo@kernel.org>
AuthorDate: Fri, 1 Sep 2017 11:04:56 +0200
Committer:  Thomas Gleixner <tglx@linutronix.de>
CommitDate: Fri, 1 Sep 2017 11:04:56 +0200

x86/idt: Fix the X86_TRAP_BP gate

Andrei Vagin reported a CRIU regression and bisected it back to:

  90f6225fba0c ("x86/idt: Move IST stack based traps to table init")

This table init conversion loses the system-gate property of X86_TRAP_BP
and erroneously moves it from DPL3 to DPL0.

Fix it.

Reported-by: Andrei Vagin <avagin@virtuozzo.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: dvlasenk@redhat.com
Cc: linux-tip-commits@vger.kernel.org
Cc: peterz@infradead.org
Cc: brgerst@gmail.com
Cc: rostedt@goodmis.org
Cc: bp@alien8.de
Cc: luto@kernel.org
Cc: jpoimboe@redhat.com
Cc: Cyrill Gorcunov <gorcunov@openvz.org>
Cc: torvalds@linux-foundation.org
Cc: tip-bot for Jacob Shin <tipbot@zytor.com>
Link: http://lkml.kernel.org/r/20170901082630.xvyi5bwk6etmppqc@gmail.com

---
 arch/x86/kernel/idt.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/idt.c b/arch/x86/kernel/idt.c
index 61b490c..6107ee1 100644
--- a/arch/x86/kernel/idt.c
+++ b/arch/x86/kernel/idt.c
@@ -44,6 +44,10 @@ struct idt_data {
 #define ISTG(_vector, _addr, _ist)			\
 	G(_vector, _addr, _ist, GATE_INTERRUPT, DPL0, __KERNEL_CS)
 
+/* System interrupt gate with interrupt stack */
+#define SISTG(_vector, _addr, _ist)			\
+	G(_vector, _addr, _ist, GATE_INTERRUPT, DPL3, __KERNEL_CS)
+
 /* Task gate */
 #define TSKG(_vector, _gdt)				\
 	G(_vector, NULL, DEFAULT_STACK, GATE_TASK, DPL0, _gdt << 3)
@@ -181,7 +185,7 @@ gate_desc debug_idt_table[IDT_ENTRIES] __page_aligned_bss;
 static const __initdata struct idt_data ist_idts[] = {
 	ISTG(X86_TRAP_DB,	debug,		DEBUG_STACK),
 	ISTG(X86_TRAP_NMI,	nmi,		NMI_STACK),
-	ISTG(X86_TRAP_BP,	int3,		DEBUG_STACK),
+	SISTG(X86_TRAP_BP,	int3,		DEBUG_STACK),
 	ISTG(X86_TRAP_DF,	double_fault,	DOUBLEFAULT_STACK),
 #ifdef CONFIG_X86_MCE
 	ISTG(X86_TRAP_MC,	&machine_check,	MCE_STACK),

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