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[PATCH] Fix: xtensa: add missing sync_core

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  [PATCH] Fix: xtensa: add missing sync_core Mathieu Desnoyers <mathieu.desnoyers@efficios.com> - 2017-08-27 23:40 +0200
    Re: [PATCH] Fix: xtensa: add missing sync_core Max Filippov <jcmvbkbc@gmail.com> - 2017-08-28 19:20 +0200
      Re: [PATCH] Fix: xtensa: add missing sync_core Mathieu Desnoyers <mathieu.desnoyers@efficios.com> - 2017-08-29 21:00 +0200

#1720930 — [PATCH] Fix: xtensa: add missing sync_core

The membarrier system call now requires all architectures to implement
sync_core(). On Xtensa, it is provided by the EXTW instruction.

[ Completely untested! Can someone on the xtensa side confirm whether
  EXTW is the right way to serialize core execution and try it out ? ]

Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
CC: Peter Zijlstra <peterz@infradead.org>
CC: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
CC: Chris Zankel <chris@zankel.net>
CC: Max Filippov <jcmvbkbc@gmail.com>
CC: linux-xtensa@linux-xtensa.org
---
 arch/xtensa/include/asm/processor.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/xtensa/include/asm/processor.h b/arch/xtensa/include/asm/processor.h
index 30ee8c608853..b435bd6adbd6 100644
--- a/arch/xtensa/include/asm/processor.h
+++ b/arch/xtensa/include/asm/processor.h
@@ -248,5 +248,14 @@ static inline unsigned long get_er(unsigned long addr)
 
 #endif /* XCHAL_HAVE_EXTERN_REGS */
 
+static inline void sync_core(void)
+{
+	/*
+	 * Synchronize the core execution pipeline. Acts as a compiler
+	 * barrier.
+	 */
+	asm volatile ("extw" : : : "memory");
+}
+
 #endif	/* __ASSEMBLY__ */
 #endif	/* _XTENSA_PROCESSOR_H */
-- 
2.11.0

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#1721825

Hi Mathieu,

On Mon, Aug 28, 2017 at 12:36 AM, Mathieu Desnoyers
<mathieu.desnoyers@efficios.com> wrote:
> The membarrier system call now requires all architectures to implement
> sync_core(). On Xtensa, it is provided by the EXTW instruction.
>
> [ Completely untested! Can someone on the xtensa side confirm whether
>   EXTW is the right way to serialize core execution and try it out ? ]

Thanks for the patch. I'm currently travelling, I'll give it a try next week
once I'm back at work.

-- 
Thanks.
-- Max

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#1722699

----- On Aug 28, 2017, at 1:12 PM, Max Filippov jcmvbkbc@gmail.com wrote:

> Hi Mathieu,
> 
> On Mon, Aug 28, 2017 at 12:36 AM, Mathieu Desnoyers
> <mathieu.desnoyers@efficios.com> wrote:
>> The membarrier system call now requires all architectures to implement
>> sync_core(). On Xtensa, it is provided by the EXTW instruction.
>>
>> [ Completely untested! Can someone on the xtensa side confirm whether
>>   EXTW is the right way to serialize core execution and try it out ? ]
> 
> Thanks for the patch. I'm currently travelling, I'll give it a try next week
> once I'm back at work.

Hi Max,

I think we may need to flush the icache to make it consistent with the dcache
too on xtensa, in addition to the EXTW. The goal here is to allow JIT engines
to reclaim and re-use memory after they discard dynamically generated code.
This is similar to what we'd need to do on arm32, where they have inconsistent
d/i-caches.

Thoughts ?

Thanks,

Mathieu


> 
> --
> Thanks.
> -- Max

-- 
Mathieu Desnoyers
EfficiOS Inc.
http://www.efficios.com

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