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[PATCH v2 0/9] Ata ceva patches

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  [PATCH v2 0/9] Ata ceva patches Michal Simek <michal.simek@xilinx.com> - 2017-08-21 13:20 +0200
    [PATCH v2 1/9] devicetree: bindings: Add sata port phy config parameters in ahci-ceva Michal Simek <michal.simek@xilinx.com> - 2017-08-21 13:20 +0200
      Re: [PATCH v2 1/9] devicetree: bindings: Add sata port phy config  parameters in ahci-ceva Rob Herring <robh@kernel.org> - 2017-08-23 02:50 +0200
    [PATCH v2 8/9] ata: ceva: Correct the suspend and resume logic for SATA Michal Simek <michal.simek@xilinx.com> - 2017-08-21 13:20 +0200
    [PATCH v2 7/9] ata: ceva: Correct the AXI bus configuration for SATA ports Michal Simek <michal.simek@xilinx.com> - 2017-08-21 13:20 +0200

#1716336 — [PATCH v2 0/9] Ata ceva patches

Hi,

this patchset contains the latest changes which are available in Xilinx tree.

Thanks,
Michal

Changes in v2:
- DT fix naming in parameters description use pN instead of phy
  reported by Rob

Anurag Kumar Vulisha (9):
  devicetree: bindings: Add sata port phy config parameters in ahci-ceva
  ata: ceva: Move sata port phy oob settings to device-tree
  ata: ceva: Add gen 3 mode support in driver
  ata: ceva: Disable Device Sleep capability
  ata: ceva: Make RxWaterMark value as module parameter
  ata: ceva: Add CCI support for SATA if CCI is enabled
  ata: ceva: Correct the AXI bus configuration for SATA ports
  ata: ceva: Correct the suspend and resume logic for SATA
  ata: ceva: Add SMMU support for SATA IP

 .../devicetree/bindings/ata/ahci-ceva.txt          |  39 ++++
 drivers/ata/ahci_ceva.c                            | 197 +++++++++++++++++----
 2 files changed, 198 insertions(+), 38 deletions(-)

-- 
1.9.1

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#1716337 — [PATCH v2 1/9] devicetree: bindings: Add sata port phy config parameters in ahci-ceva

From: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>

This patch adds device tree bindings for sata port phy parameters
in the ahci-ceva.txt file.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

Changes in v2:
- DT fix naming in parameters description use pN instead of phy
  reported by Rob

 .../devicetree/bindings/ata/ahci-ceva.txt          | 39 ++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/Documentation/devicetree/bindings/ata/ahci-ceva.txt b/Documentation/devicetree/bindings/ata/ahci-ceva.txt
index 7ca8b976c13a..7561cc4de371 100644
--- a/Documentation/devicetree/bindings/ata/ahci-ceva.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-ceva.txt
@@ -5,6 +5,36 @@ Required properties:
   - compatible: Compatibility string. Must be 'ceva,ahci-1v84'.
   - clocks: Input clock specifier. Refer to common clock bindings.
   - interrupts: Interrupt specifier. Refer to interrupt binding.
+  - ceva,p0-cominit-params: OOB timing value for COMINIT parameter for port 0.
+  - ceva,p1-cominit-params: OOB timing value for COMINIT parameter for port 1.
+			The fields for the above parameter must be as shown below:
+			ceva,pN-cominit-params = /bits/ 8 <CIBGMN CIBGMX CIBGN CINMP>;
+			CINMP : COMINIT Negate Minimum Period.
+			CIBGN : COMINIT Burst Gap Nominal.
+			CIBGMX: COMINIT Burst Gap Maximum.
+			CIBGMN: COMINIT Burst Gap Minimum.
+  - ceva,p0-comwake-params: OOB timing value for COMWAKE parameter for port 0.
+  - ceva,p1-comwake-params: OOB timing value for COMWAKE parameter for port 1.
+			The fields for the above parameter must be as shown below:
+			ceva,pN-comwake-params = /bits/ 8 <CWBGMN CWBGMX CWBGN CWNMP>;
+			CWBGMN: COMWAKE Burst Gap Minimum.
+			CWBGMX: COMWAKE Burst Gap Maximum.
+			CWBGN: COMWAKE Burst Gap Nominal.
+			CWNMP: COMWAKE Negate Minimum Period.
+  - ceva,p0-burst-params: Burst timing value for COM parameter for port 0.
+  - ceva,p1-burst-params: Burst timing value for COM parameter for port 1.
+			The fields for the above parameter must be as shown below:
+			ceva,pN-burst-params = /bits/ 8 <BMX BNM SFD PTST>;
+			BMX: COM Burst Maximum.
+			BNM: COM Burst Nominal.
+			SFD: Signal Failure Detection value.
+			PTST: Partial to Slumber timer value.
+  - ceva,p0-retry-params: Retry interval timing value for port 0.
+  - ceva,p1-retry-params: Retry interval timing value for port 1.
+			The fields for the above parameter must be as shown below:
+			ceva,pN-retry-params = /bits/ 16 <RIT RCT>;
+			RIT:  Retry Interval Timer.
+			RCT:  Rate Change Timer.
 
 Optional properties:
   - ceva,broken-gen2: limit to gen1 speed instead of gen2.
@@ -16,5 +46,14 @@ Examples:
 		interrupt-parent = <&gic>;
 		interrupts = <0 133 4>;
 		clocks = <&clkc SATA_CLK_ID>;
+		ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
+		ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
+		ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
+		ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>;
+
+		ceva,p1-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
+		ceva,p1-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
+		ceva,p1-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
+		ceva,p1-retry-params = /bits/ 16 <0x0216 0x7F06>;
 		ceva,broken-gen2;
 	};
-- 
1.9.1

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#1717931 — Re: [PATCH v2 1/9] devicetree: bindings: Add sata port phy config parameters in ahci-ceva

On Mon, Aug 21, 2017 at 01:17:16PM +0200, Michal Simek wrote:
> From: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
> 
> This patch adds device tree bindings for sata port phy parameters
> in the ahci-ceva.txt file.
> 
> Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
> 
> Changes in v2:
> - DT fix naming in parameters description use pN instead of phy
>   reported by Rob
> 
>  .../devicetree/bindings/ata/ahci-ceva.txt          | 39 ++++++++++++++++++++++
>  1 file changed, 39 insertions(+)

Acked-by: Rob Herring <robh@kernel.org>

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#1716338 — [PATCH v2 8/9] ata: ceva: Correct the suspend and resume logic for SATA

From: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>

The present suspend code disables the port interrupts
and stops the HBA. On resume it enables the interrupts and HBA.
This works fine until the FPD power domain is not off.
If FPD is off then the ceva vendor specific configurations like
OOB, AXI settings are lost, they need to be re-programmed and
also since SERDES is also in FPD , SATA lane phy init needs to
be called again (which is not happening in the present sequence)
Because of this incorrect sequence SATA fails to work on resume.

This patch corrects the code to make Suspend & Resume work in normal
and FPD off cases.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Reviewed-by: Shubhrajyoti Datta <shubhraj@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

Changes in v2: None

 drivers/ata/ahci_ceva.c | 29 +++++++++++++++++++++++++++--
 1 file changed, 27 insertions(+), 2 deletions(-)

diff --git a/drivers/ata/ahci_ceva.c b/drivers/ata/ahci_ceva.c
index 113c1f617da9..c0742cbe4faa 100644
--- a/drivers/ata/ahci_ceva.c
+++ b/drivers/ata/ahci_ceva.c
@@ -298,12 +298,37 @@ static int ceva_ahci_probe(struct platform_device *pdev)
 
 static int __maybe_unused ceva_ahci_suspend(struct device *dev)
 {
-	return ahci_platform_suspend_host(dev);
+	return ahci_platform_suspend(dev);
 }
 
 static int __maybe_unused ceva_ahci_resume(struct device *dev)
 {
-	return ahci_platform_resume_host(dev);
+	struct ata_host *host = dev_get_drvdata(dev);
+	struct ahci_host_priv *hpriv = host->private_data;
+	int rc;
+
+	rc = ahci_platform_enable_resources(hpriv);
+	if (rc)
+		return rc;
+
+	/* Configure CEVA specific config before resuming HBA */
+	ahci_ceva_setup(hpriv);
+
+	rc = ahci_platform_resume_host(dev);
+	if (rc)
+		goto disable_resources;
+
+	/* We resumed so update PM runtime state */
+	pm_runtime_disable(dev);
+	pm_runtime_set_active(dev);
+	pm_runtime_enable(dev);
+
+	return 0;
+
+disable_resources:
+	ahci_platform_disable_resources(hpriv);
+
+	return rc;
 }
 
 static SIMPLE_DEV_PM_OPS(ahci_ceva_pm_ops, ceva_ahci_suspend, ceva_ahci_resume);
-- 
1.9.1

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#1716340 — [PATCH v2 7/9] ata: ceva: Correct the AXI bus configuration for SATA ports

From: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>

Previously PAXIC register was programmed before configuring PCFG
register. PCFG should be programmed with the address of the port
for which PAXIC should be configured for.
This was not happening before, so only one port PAXIC was written
correctly and the other port was having wrong value.
This patch moves the PXAIC register write after configuring PCFG,
doing so will correct the axi bus settings for sata port0 & port1.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

Changes in v2: None

 drivers/ata/ahci_ceva.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/ata/ahci_ceva.c b/drivers/ata/ahci_ceva.c
index ec9cfb52c6f6..113c1f617da9 100644
--- a/drivers/ata/ahci_ceva.c
+++ b/drivers/ata/ahci_ceva.c
@@ -134,14 +134,6 @@ static void ahci_ceva_setup(struct ahci_host_priv *hpriv)
 	u32 tmp;
 	int i;
 
-	/*
-	 * AXI Data bus width to 64
-	 * Set Mem Addr Read, Write ID for data transfers
-	 * Transfer limit to 72 DWord
-	 */
-	tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
-	writel(tmp, mmio + AHCI_VEND_PAXIC);
-
 	/* Set AHCI Enable */
 	tmp = readl(mmio + HOST_CTL);
 	tmp |= HOST_AHCI_EN;
@@ -152,6 +144,14 @@ static void ahci_ceva_setup(struct ahci_host_priv *hpriv)
 		tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | (PCFG_PAD_VAL + i);
 		writel(tmp, mmio + AHCI_VEND_PCFG);
 
+		/*
+		 * AXI Data bus width to 64
+		 * Set Mem Addr Read, Write ID for data transfers
+		 * Transfer limit to 72 DWord
+		 */
+		tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
+		writel(tmp, mmio + AHCI_VEND_PAXIC);
+
 		/* Set AXI cache control register if CCi is enabled */
 		if (cevapriv->is_cci_enabled) {
 			tmp = readl(mmio + AHCI_VEND_AXICC);
-- 
1.9.1

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