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Re: [PATCH 1/2] pinctrl: sunxi: fix wrong irq_banks number for H5 pinctrl

Started byLinus Walleij <linus.walleij@linaro.org>
First post2017-08-22 14:50 +0200
Last post2017-08-22 14:50 +0200
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  Re: [PATCH 1/2] pinctrl: sunxi: fix wrong irq_banks number for H5 pinctrl Linus Walleij <linus.walleij@linaro.org> - 2017-08-22 14:50 +0200

#1717377 — Re: [PATCH 1/2] pinctrl: sunxi: fix wrong irq_banks number for H5 pinctrl

FromLinus Walleij <linus.walleij@linaro.org>
Date2017-08-22 14:50 +0200
SubjectRe: [PATCH 1/2] pinctrl: sunxi: fix wrong irq_banks number for H5 pinctrl
Message-ID<uhgN4-2rg-11@gated-at.bofh.it>
On Fri, Aug 11, 2017 at 4:27 PM, Icenowy Zheng <icenowy@aosc.io> wrote:

> The pin controller of Allwinner H5 has three IRQ banks, however in old
> versions of drivers and device trees, only two are set, which makes
> PG bank IRQ not available.
>
> If it's directly set to 3, the old device trees will fail to boot.
>
> Add a workaround (and a warning) for older device trees, and allow new
> device trees to use correct 3 IRQ banks.
>
> Fixes: 838adb576d4a ("drivers: pinctrl: add driver for Allwinner H5 SoC")
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

Patch applied with Chen-Yu's ACK.

Yours,
Linus Walleij

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