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Groups > linux.kernel > #1714932 > unrolled thread

[PATCH v4 0/8] MIPS: Add virtual Ranchu board as a generic-based board

Started byAleksandar Markovic <aleksandar.markovic@rt-rk.com>
First post2017-08-18 15:20 +0200
Last post2017-08-18 16:00 +0200
Articles 5 — 2 participants

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Contents

  [PATCH v4 0/8] MIPS: Add virtual Ranchu board as a generic-based board Aleksandar Markovic <aleksandar.markovic@rt-rk.com> - 2017-08-18 15:20 +0200
    [PATCH v4 5/8] MIPS: ranchu: Add Ranchu as a new generic-based board Aleksandar Markovic <aleksandar.markovic@rt-rk.com> - 2017-08-18 15:20 +0200
    [PATCH v4 3/8] Documentation: Add device tree binding for Goldfish PIC driver Aleksandar Markovic <aleksandar.markovic@rt-rk.com> - 2017-08-18 15:20 +0200
    [PATCH v4 4/8] irqchip/irq-goldfish-pic: Add Goldfish PIC driver Aleksandar Markovic <aleksandar.markovic@rt-rk.com> - 2017-08-18 15:20 +0200
      Re: [PATCH v4 4/8] irqchip/irq-goldfish-pic: Add Goldfish PIC driver Marc Zyngier <marc.zyngier@arm.com> - 2017-08-18 16:00 +0200

#1714932 — [PATCH v4 0/8] MIPS: Add virtual Ranchu board as a generic-based board

FromAleksandar Markovic <aleksandar.markovic@rt-rk.com>
Date2017-08-18 15:20 +0200
Subject[PATCH v4 0/8] MIPS: Add virtual Ranchu board as a generic-based board
Message-ID<ufPlU-4d0-13@gated-at.bofh.it>
From: Aleksandar Markovic <aleksandar.markovic@imgtec.com>

v3->v4:

    - corrected RTC clock patch so that it does not cause build
      errors for some targets, and limited compile support to Mips
      architecture, since it is the only case where this driver is
      used
    - changed titles of patches 2 and 4 to make them consistent
      with commit messages of corresponding directories
    - applied "checkpatch --strict" to the whole series and
      corrected several instances of reported warnings 
    - rebased to the latest code

v2->v3:

    - fixed configuration dependency for VIRTIO_NET and
        RTC_DRV_GOLDFISH
    - fixed frequency calculation in ranchu_measure_hpt_freq()
    - use DT info instead of hard-coding RTC base in
        ranchu_measure_hpt_freq()
    - Goldfish PIC reworked to follow legacy irq domain paradigm
    - Goldfish RTC reimplemented to support alarm functionality
    - added COMPILE_TEST to Goldfish PIC & RTC to extend compile
        test coverage
    - corrected location of documentation for Goldfish FB
    - added a patch on unselecting ARCH_MIGHT_HAVE_PC_SERIO
    - removed two patches on i8042 as not needed in new organization
    - removed the patch on separate Mips Android config as not needed
    - rebased to the latest code

v1->v2:

    - patch on RTC driver cleaned up
    - added drivers for virtio console and net to the Ranchu board
    - minor improvements in commit messages
    - updated recipient lists using get_maintainer.pl
    - rebased to the latest code

This series adds Mips Ranchu virtual machine used by Android emulator.
The board relies on the concept of Mips generic boards, and utilizes
generic board framework for build and device organization.

The Ranchu board is intended to be used by Android emulator.The name
"Ranchu" originates from Android development community. "Goldfish" and
"Ranchu" are names for two generations of virtual boards used by
Android emulator. "Ranchu" is a newer one among the two, and this
series deals with Ranchu. However, for historical reasons, some file,
device, and variable names in this series still contain the word
"Goldfish".

Mips Ranchu machine includes a number of Goldfish devices. The
support for Virtio devices is also included. Ranchu board supports
up to 16 virtio devices which can be attached using virtio MMIO Bus.
This is summarized in the following picture:

       ABUS
        ||----MIPS CPU
        ||       |                    IRQs
        ||----Goldfish PIC------------(32)--------
        ||                     | | | | | | | | |
        ||----Goldfish TTY------ | | | | | | | |
        ||                       | | | | | | | |
        ||----Goldfish RTC-------- | | | | | | |
        ||                         | | | | | | |
        ||----Goldfish FB----------- | | | | | |
        ||                           | | | | | |
        ||----Goldfish Events--------- | | | | |
        ||                             | | | | |
        ||----Goldfish Audio------------ | | | |
        ||                               | | | |
        ||----Goldfish Battery------------ | | |
        ||                                 | | |
        ||----Android PIPE------------------ | |
        ||                                   | |
        ||----Virtio MMIO Bus                | |
        ||    |    |    |                    | |
        ||    |    |   (virtio-block)--------- |
        ||   (16)  |                           |
        ||    |   (virtio-net)------------------


Device Tree is created on the QEMU side based on the information about
devices IO map and IRQ numbers. Kernel will load this DTB using UHI
boot protocol.

Checkpatch script outputs a small number of warnings if applied to
this series. We did not correct the code, since we think the code is
correct for those particular cases of checkpatch warnings.

Aleksandar Markovic (4):
  Documentation: Add device tree binding for Goldfish RTC driver
  Documentation: Add device tree binding for Goldfish PIC driver
  Documentation: Add device tree binding for Goldfish FB driver
  video: goldfishfb: Add support for device tree bindings

Miodrag Dinic (4):
  rtc: goldfish: Add RTC driver for Android emulator
  irqchip/irq-goldfish-pic: Add Goldfish PIC driver
  MIPS: ranchu: Add Ranchu as a new generic-based board
  MIPS: Unselect ARCH_MIGHT_HAVE_PC_SERIO if MIPS_GENERIC

 .../bindings/display/google,goldfish-fb.txt        |  18 ++
 .../interrupt-controller/google,goldfish-pic.txt   |  18 ++
 .../bindings/rtc/google,goldfish-rtc.txt           |  17 ++
 MAINTAINERS                                        |  18 ++
 arch/mips/Kconfig                                  |   2 +-
 arch/mips/configs/generic/board-ranchu.config      |  30 +++
 arch/mips/generic/Kconfig                          |  11 +
 arch/mips/generic/Makefile                         |   1 +
 arch/mips/generic/board-ranchu.c                   |  78 +++++++
 drivers/irqchip/Kconfig                            |   8 +
 drivers/irqchip/Makefile                           |   1 +
 drivers/irqchip/irq-goldfish-pic.c                 | 145 +++++++++++++
 drivers/rtc/Kconfig                                |   8 +
 drivers/rtc/Makefile                               |   1 +
 drivers/rtc/rtc-goldfish.c                         | 237 +++++++++++++++++++++
 drivers/video/fbdev/goldfishfb.c                   |   8 +-
 16 files changed, 599 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/google,goldfish-fb.txt
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/google,goldfish-pic.txt
 create mode 100644 Documentation/devicetree/bindings/rtc/google,goldfish-rtc.txt
 create mode 100644 arch/mips/configs/generic/board-ranchu.config
 create mode 100644 arch/mips/generic/board-ranchu.c
 create mode 100644 drivers/irqchip/irq-goldfish-pic.c
 create mode 100644 drivers/rtc/rtc-goldfish.c

-- 
2.7.4

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#1714935 — [PATCH v4 5/8] MIPS: ranchu: Add Ranchu as a new generic-based board

FromAleksandar Markovic <aleksandar.markovic@rt-rk.com>
Date2017-08-18 15:20 +0200
Subject[PATCH v4 5/8] MIPS: ranchu: Add Ranchu as a new generic-based board
Message-ID<ufPlW-4d0-63@gated-at.bofh.it>
In reply to#1714932
From: Miodrag Dinic <miodrag.dinic@imgtec.com>

Provide amendments to the Mips generic platform framework so that
the new generic-based board Ranchu can be chosen to be built.

Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com>
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
---
 MAINTAINERS                                   |  6 +++
 arch/mips/configs/generic/board-ranchu.config | 30 +++++++++++
 arch/mips/generic/Kconfig                     | 11 ++++
 arch/mips/generic/Makefile                    |  1 +
 arch/mips/generic/board-ranchu.c              | 78 +++++++++++++++++++++++++++
 5 files changed, 126 insertions(+)
 create mode 100644 arch/mips/configs/generic/board-ranchu.config
 create mode 100644 arch/mips/generic/board-ranchu.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 6426875..03403c9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11063,6 +11063,12 @@ S:	Maintained
 F:	Documentation/blockdev/ramdisk.txt
 F:	drivers/block/brd.c
 
+RANCHU VIRTUAL BOARD FOR MIPS
+M:	Miodrag Dinic <miodrag.dinic@imgtec.com>
+L:	linux-mips@linux-mips.org
+S:	Supported
+F:	arch/mips/generic/board-ranchu.c
+
 RANDOM NUMBER DRIVER
 M:	"Theodore Ts'o" <tytso@mit.edu>
 S:	Maintained
diff --git a/arch/mips/configs/generic/board-ranchu.config b/arch/mips/configs/generic/board-ranchu.config
new file mode 100644
index 0000000..fee9ad4
--- /dev/null
+++ b/arch/mips/configs/generic/board-ranchu.config
@@ -0,0 +1,30 @@
+CONFIG_VIRT_BOARD_RANCHU=y
+
+CONFIG_BATTERY_GOLDFISH=y
+CONFIG_FB=y
+CONFIG_FB_GOLDFISH=y
+CONFIG_GOLDFISH=y
+CONFIG_STAGING=y
+CONFIG_GOLDFISH_AUDIO=y
+CONFIG_GOLDFISH_PIC=y
+CONFIG_GOLDFISH_PIPE=y
+CONFIG_GOLDFISH_TTY=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_GOLDFISH=y
+
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_GOLDFISH_EVENTS=y
+
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_RESET_SYSCON_POWEROFF=y
+
+CONFIG_VIRTIO_BLK=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_VIRTIO_MMIO=y
+CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
+CONFIG_NETDEVICES=y
+CONFIG_VIRTIO_NET=y
diff --git a/arch/mips/generic/Kconfig b/arch/mips/generic/Kconfig
index 51ffbba..fe1231d 100644
--- a/arch/mips/generic/Kconfig
+++ b/arch/mips/generic/Kconfig
@@ -36,4 +36,15 @@ config FIT_IMAGE_FDT_BOSTON
 	  enable this if you wish to boot on a MIPS Boston board, as it is
 	  expected by the bootloader.
 
+config VIRT_BOARD_RANCHU
+	bool "Ranchu platform for Android emulator"
+	select LEGACY_BOARDS
+	help
+	  This enables support for the platform used by Android emulator.
+
+	  Ranchu platform consists of a set of virtual devices. This platform
+	  enables emulation of variety of virtual configurations while using
+	  Android emulator. Android emulator is based on Qemu, and contains
+	  the support for the same set of virtual devices.
+
 endif
diff --git a/arch/mips/generic/Makefile b/arch/mips/generic/Makefile
index 56b3ea5..14931f2 100644
--- a/arch/mips/generic/Makefile
+++ b/arch/mips/generic/Makefile
@@ -14,4 +14,5 @@ obj-y += proc.o
 
 obj-$(CONFIG_YAMON_DT_SHIM)		+= yamon-dt.o
 obj-$(CONFIG_LEGACY_BOARD_SEAD3)	+= board-sead3.o
+obj-$(CONFIG_VIRT_BOARD_RANCHU)	+= board-ranchu.o
 obj-$(CONFIG_KEXEC)			+= kexec.o
diff --git a/arch/mips/generic/board-ranchu.c b/arch/mips/generic/board-ranchu.c
new file mode 100644
index 0000000..500874d
--- /dev/null
+++ b/arch/mips/generic/board-ranchu.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2017 Imagination Technologies Ltd.
+ * Author: Miodrag Dinic <miodrag.dinic@imgtec.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/of_address.h>
+
+#include <asm/machine.h>
+#include <asm/time.h>
+
+#define GOLDFISH_TIMER_LOW		0x00
+#define GOLDFISH_TIMER_HIGH		0x04
+
+static __init uint64_t read_rtc_time(void __iomem *base)
+{
+	u64 time_low;
+	u64 time_high;
+
+	time_low = readl(base + GOLDFISH_TIMER_LOW);
+	time_high = readl(base + GOLDFISH_TIMER_HIGH);
+
+	return (time_high << 32) | time_low;
+}
+
+static __init unsigned int ranchu_measure_hpt_freq(void)
+{
+	u64 rtc_start, rtc_current, rtc_delta;
+	unsigned int start, count;
+	struct device_node *np;
+	void __iomem *rtc_base;
+
+	np = of_find_compatible_node(NULL, NULL, "google,goldfish-rtc");
+	if (!np)
+		panic("%s(): Failed to find 'google,goldfish-rtc' dt node!",
+		      __func__);
+
+	rtc_base = of_iomap(np, 0);
+	if (!rtc_base)
+		panic("%s(): Failed to ioremap Goldfish RTC base!", __func__);
+
+	/*
+	 * poll the nanosecond resolution RTC for 1 second
+	 * to calibrate the CPU frequency
+	 */
+	rtc_start = read_rtc_time(rtc_base);
+	start = read_c0_count();
+
+	do {
+		rtc_current = read_rtc_time(rtc_base);
+		rtc_delta = rtc_current - rtc_start;
+	} while (rtc_delta < NSEC_PER_SEC);
+
+	count = read_c0_count() - start;
+
+	count += 5000;	/* round */
+	count -= count % 10000;
+
+	return count;
+}
+
+static const struct of_device_id ranchu_of_match[];
+
+MIPS_MACHINE(ranchu) = {
+	.matches = ranchu_of_match,
+	.measure_hpt_freq = ranchu_measure_hpt_freq,
+};
+
+static const struct of_device_id ranchu_of_match[] = {
+	{
+		.compatible = "mti,ranchu",
+		.data = &__mips_mach_ranchu,
+	},
+};
-- 
2.7.4

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#1714939 — [PATCH v4 3/8] Documentation: Add device tree binding for Goldfish PIC driver

FromAleksandar Markovic <aleksandar.markovic@rt-rk.com>
Date2017-08-18 15:20 +0200
Subject[PATCH v4 3/8] Documentation: Add device tree binding for Goldfish PIC driver
Message-ID<ufPlX-4d0-73@gated-at.bofh.it>
In reply to#1714932
From: Aleksandar Markovic <aleksandar.markovic@imgtec.com>

Add documentation for DT binding of Goldfish PIC driver. The compatible
string used by OS for binding the driver is "google,goldfish-pic".

Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com>
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
---
 .../interrupt-controller/google,goldfish-pic.txt       | 18 ++++++++++++++++++
 MAINTAINERS                                            |  5 +++++
 2 files changed, 23 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/google,goldfish-pic.txt

diff --git a/Documentation/devicetree/bindings/interrupt-controller/google,goldfish-pic.txt b/Documentation/devicetree/bindings/interrupt-controller/google,goldfish-pic.txt
new file mode 100644
index 0000000..f198762
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/google,goldfish-pic.txt
@@ -0,0 +1,18 @@
+Android Goldfish PIC
+
+Android Goldfish programmable interrupt device used by Android
+emulator.
+
+Required properties:
+
+- compatible : should contain "google,goldfish-pic"
+- reg        : <registers mapping>
+- interrupts : <interrupt mapping>
+
+Example:
+
+        goldfish_pic@9020000 {
+                compatible = "google,goldfish-pic";
+                reg = <0x9020000 0x1000>;
+                interrupts = <0x3>;
+        };
diff --git a/MAINTAINERS b/MAINTAINERS
index 3d105be..013da1d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -840,6 +840,11 @@ S:	Supported
 F:	drivers/android/
 F:	drivers/staging/android/
 
+ANDROID GOLDFISH PIC DRIVER
+M:	Miodrag Dinic <miodrag.dinic@imgtec.com>
+S:	Supported
+F:	Documentation/devicetree/bindings/interrupt-controller/google,goldfish-pic.txt
+
 ANDROID GOLDFISH RTC DRIVER
 M:	Miodrag Dinic <miodrag.dinic@imgtec.com>
 S:	Supported
-- 
2.7.4

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#1714941 — [PATCH v4 4/8] irqchip/irq-goldfish-pic: Add Goldfish PIC driver

FromAleksandar Markovic <aleksandar.markovic@rt-rk.com>
Date2017-08-18 15:20 +0200
Subject[PATCH v4 4/8] irqchip/irq-goldfish-pic: Add Goldfish PIC driver
Message-ID<ufPlX-4d0-77@gated-at.bofh.it>
In reply to#1714932
From: Miodrag Dinic <miodrag.dinic@imgtec.com>

Add device driver for a virtual programmable interrupt controller

The virtual PIC is designed as a device tree-based interrupt controller.

The compatible string used by OS for binding the driver is
"google,goldfish-pic".

Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com>
Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
---
 MAINTAINERS                        |   1 +
 drivers/irqchip/Kconfig            |   8 ++
 drivers/irqchip/Makefile           |   1 +
 drivers/irqchip/irq-goldfish-pic.c | 145 +++++++++++++++++++++++++++++++++++++
 4 files changed, 155 insertions(+)
 create mode 100644 drivers/irqchip/irq-goldfish-pic.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 013da1d..6426875 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -844,6 +844,7 @@ ANDROID GOLDFISH PIC DRIVER
 M:	Miodrag Dinic <miodrag.dinic@imgtec.com>
 S:	Supported
 F:	Documentation/devicetree/bindings/interrupt-controller/google,goldfish-pic.txt
+F:	drivers/irqchip/irq-goldfish-pic.c
 
 ANDROID GOLDFISH RTC DRIVER
 M:	Miodrag Dinic <miodrag.dinic@imgtec.com>
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index f1fd5f4..21fab14 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -306,3 +306,11 @@ config QCOM_IRQ_COMBINER
 	help
 	  Say yes here to add support for the IRQ combiner devices embedded
 	  in Qualcomm Technologies chips.
+
+config GOLDFISH_PIC
+	bool "Goldfish programmable interrupt controller"
+	depends on MIPS && (GOLDFISH || COMPILE_TEST)
+	select IRQ_DOMAIN
+	help
+	  Say yes here to enable Goldfish interrupt controller driver used
+	  for Goldfish based virtual platforms.
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index e88d856..ade04a1 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -78,3 +78,4 @@ obj-$(CONFIG_EZNPS_GIC)			+= irq-eznps.o
 obj-$(CONFIG_ARCH_ASPEED)		+= irq-aspeed-vic.o irq-aspeed-i2c-ic.o
 obj-$(CONFIG_STM32_EXTI) 		+= irq-stm32-exti.o
 obj-$(CONFIG_QCOM_IRQ_COMBINER)		+= qcom-irq-combiner.o
+obj-$(CONFIG_GOLDFISH_PIC) 		+= irq-goldfish-pic.o
diff --git a/drivers/irqchip/irq-goldfish-pic.c b/drivers/irqchip/irq-goldfish-pic.c
new file mode 100644
index 0000000..948c35e
--- /dev/null
+++ b/drivers/irqchip/irq-goldfish-pic.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright (C) 2017 Imagination Technologies Ltd.	All rights reserved
+ *	Author: Miodrag Dinic <miodrag.dinic@imgtec.com>
+ *
+ * This file implements interrupt controller driver for MIPS Goldfish PIC.
+ *
+ * This program is free software; you can redistribute	it and/or modify it
+ * under  the terms of	the GNU General	 Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqdomain.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#include <asm/setup.h>
+
+/* 0..7 MIPS CPU interrupts */
+#define GF_CPU_IRQ_PIC		(MIPS_CPU_IRQ_BASE + 2)
+#define GF_CPU_IRQ_COMPARE	(MIPS_CPU_IRQ_BASE + 7)
+
+#define GF_NR_IRQS		40
+/* 8..39 Cascaded Goldfish PIC interrupts */
+#define GF_IRQ_OFFSET		8
+
+#define GF_PIC_NUMBER		0x04
+#define GF_PIC_DISABLE_ALL	0x08
+#define GF_PIC_DISABLE		0x0c
+#define GF_PIC_ENABLE		0x10
+
+static struct irq_domain *irq_domain;
+static void __iomem *gf_pic_base;
+
+static inline void unmask_goldfish_irq(struct irq_data *d)
+{
+	writel(d->hwirq - GF_IRQ_OFFSET,
+	       gf_pic_base + GF_PIC_ENABLE);
+	irq_enable_hazard();
+}
+
+static inline void mask_goldfish_irq(struct irq_data *d)
+{
+	writel(d->hwirq - GF_IRQ_OFFSET,
+	       gf_pic_base + GF_PIC_DISABLE);
+	irq_disable_hazard();
+}
+
+static struct irq_chip goldfish_irq_controller = {
+	.name		= "Goldfish PIC",
+	.irq_ack	= mask_goldfish_irq,
+	.irq_mask	= mask_goldfish_irq,
+	.irq_mask_ack	= mask_goldfish_irq,
+	.irq_unmask	= unmask_goldfish_irq,
+	.irq_eoi	= unmask_goldfish_irq,
+	.irq_disable	= mask_goldfish_irq,
+	.irq_enable	= unmask_goldfish_irq,
+};
+
+static void goldfish_irq_dispatch(void)
+{
+	u32 irq;
+	u32 virq;
+
+	irq = readl(gf_pic_base + GF_PIC_NUMBER);
+	if (irq == 0) {
+		/* Timer interrupt */
+		do_IRQ(GF_CPU_IRQ_COMPARE);
+		return;
+	}
+
+	virq = irq_linear_revmap(irq_domain, irq);
+	virq += GF_IRQ_OFFSET;
+	do_IRQ(virq);
+}
+
+static void goldfish_ip2_irq_dispatch(struct irq_desc *desc)
+{
+	unsigned long pending = read_c0_cause() & read_c0_status() & ST0_IM;
+
+	if (pending & CAUSEF_IP2)
+		goldfish_irq_dispatch();
+	else
+		spurious_interrupt();
+}
+
+static int goldfish_pic_map(struct irq_domain *d, unsigned int irq,
+			    irq_hw_number_t hw)
+{
+	if (cpu_has_vint)
+		set_vi_handler(hw, goldfish_irq_dispatch);
+
+	irq_set_chip_and_handler(irq, &goldfish_irq_controller,
+				 handle_level_irq);
+
+	return 0;
+}
+
+static const struct irq_domain_ops gf_pic_irq_domain_ops = {
+	.map = goldfish_pic_map,
+	.xlate = irq_domain_xlate_onetwocell,
+};
+
+static struct irqaction cascade = {
+	.handler	= no_action,
+	.flags		= IRQF_PROBE_SHARED,
+	.name		= "cascade",
+};
+
+static void __init __goldfish_pic_init(struct device_node *of_node)
+{
+	gf_pic_base = of_iomap(of_node, 0);
+	if (!gf_pic_base)
+		panic("Failed to map Goldfish PIC base : No such device!");
+
+	/* Mask interrupts. */
+	writel(1, gf_pic_base + GF_PIC_DISABLE_ALL);
+
+	if (!cpu_has_vint)
+		irq_set_chained_handler(GF_CPU_IRQ_PIC,
+					goldfish_ip2_irq_dispatch);
+
+	setup_irq(GF_CPU_IRQ_PIC, &cascade);
+
+	irq_domain = irq_domain_add_legacy(of_node, GF_NR_IRQS,
+					   GF_IRQ_OFFSET, 0,
+					   &gf_pic_irq_domain_ops, NULL);
+	if (!irq_domain)
+		panic("Failed to add irqdomain for Goldfish PIC");
+}
+
+int __init goldfish_pic_of_init(struct device_node *of_node,
+				struct device_node *parent)
+{
+	__goldfish_pic_init(of_node);
+	return 0;
+}
+
+IRQCHIP_DECLARE(google_gf_pic, "google,goldfish-pic", goldfish_pic_of_init);
+
-- 
2.7.4

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#1715097 — Re: [PATCH v4 4/8] irqchip/irq-goldfish-pic: Add Goldfish PIC driver

FromMarc Zyngier <marc.zyngier@arm.com>
Date2017-08-18 16:00 +0200
SubjectRe: [PATCH v4 4/8] irqchip/irq-goldfish-pic: Add Goldfish PIC driver
Message-ID<ufPYE-4vA-83@gated-at.bofh.it>
In reply to#1714941
On 18/08/17 14:08, Aleksandar Markovic wrote:
> From: Miodrag Dinic <miodrag.dinic@imgtec.com>
> 
> Add device driver for a virtual programmable interrupt controller
> 
> The virtual PIC is designed as a device tree-based interrupt controller.
> 
> The compatible string used by OS for binding the driver is
> "google,goldfish-pic".
> 
> Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
> Signed-off-by: Goran Ferenc <goran.ferenc@imgtec.com>
> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@imgtec.com>
> ---
>  MAINTAINERS                        |   1 +
>  drivers/irqchip/Kconfig            |   8 ++
>  drivers/irqchip/Makefile           |   1 +
>  drivers/irqchip/irq-goldfish-pic.c | 145 +++++++++++++++++++++++++++++++++++++
>  4 files changed, 155 insertions(+)
>  create mode 100644 drivers/irqchip/irq-goldfish-pic.c
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 013da1d..6426875 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -844,6 +844,7 @@ ANDROID GOLDFISH PIC DRIVER
>  M:	Miodrag Dinic <miodrag.dinic@imgtec.com>
>  S:	Supported
>  F:	Documentation/devicetree/bindings/interrupt-controller/google,goldfish-pic.txt
> +F:	drivers/irqchip/irq-goldfish-pic.c
>  
>  ANDROID GOLDFISH RTC DRIVER
>  M:	Miodrag Dinic <miodrag.dinic@imgtec.com>
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index f1fd5f4..21fab14 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -306,3 +306,11 @@ config QCOM_IRQ_COMBINER
>  	help
>  	  Say yes here to add support for the IRQ combiner devices embedded
>  	  in Qualcomm Technologies chips.
> +
> +config GOLDFISH_PIC
> +	bool "Goldfish programmable interrupt controller"
> +	depends on MIPS && (GOLDFISH || COMPILE_TEST)
> +	select IRQ_DOMAIN
> +	help
> +	  Say yes here to enable Goldfish interrupt controller driver used
> +	  for Goldfish based virtual platforms.
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index e88d856..ade04a1 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -78,3 +78,4 @@ obj-$(CONFIG_EZNPS_GIC)			+= irq-eznps.o
>  obj-$(CONFIG_ARCH_ASPEED)		+= irq-aspeed-vic.o irq-aspeed-i2c-ic.o
>  obj-$(CONFIG_STM32_EXTI) 		+= irq-stm32-exti.o
>  obj-$(CONFIG_QCOM_IRQ_COMBINER)		+= qcom-irq-combiner.o
> +obj-$(CONFIG_GOLDFISH_PIC) 		+= irq-goldfish-pic.o
> diff --git a/drivers/irqchip/irq-goldfish-pic.c b/drivers/irqchip/irq-goldfish-pic.c
> new file mode 100644
> index 0000000..948c35e
> --- /dev/null
> +++ b/drivers/irqchip/irq-goldfish-pic.c
> @@ -0,0 +1,145 @@
> +/*
> + * Copyright (C) 2017 Imagination Technologies Ltd.	All rights reserved
> + *	Author: Miodrag Dinic <miodrag.dinic@imgtec.com>
> + *
> + * This file implements interrupt controller driver for MIPS Goldfish PIC.
> + *
> + * This program is free software; you can redistribute	it and/or modify it
> + * under  the terms of	the GNU General	 Public License as published by the
> + * Free Software Foundation;  either version 2 of the  License, or (at your
> + * option) any later version.
> + */
> +
> +#include <linux/init.h>
> +#include <linux/interrupt.h>
> +#include <linux/kernel.h>
> +#include <linux/irq.h>
> +#include <linux/irqchip.h>
> +#include <linux/irqdomain.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +
> +#include <asm/setup.h>
> +
> +/* 0..7 MIPS CPU interrupts */
> +#define GF_CPU_IRQ_PIC		(MIPS_CPU_IRQ_BASE + 2)
> +#define GF_CPU_IRQ_COMPARE	(MIPS_CPU_IRQ_BASE + 7)
> +
> +#define GF_NR_IRQS		40
> +/* 8..39 Cascaded Goldfish PIC interrupts */
> +#define GF_IRQ_OFFSET		8
> +
> +#define GF_PIC_NUMBER		0x04
> +#define GF_PIC_DISABLE_ALL	0x08
> +#define GF_PIC_DISABLE		0x0c
> +#define GF_PIC_ENABLE		0x10
> +
> +static struct irq_domain *irq_domain;
> +static void __iomem *gf_pic_base;
> +
> +static inline void unmask_goldfish_irq(struct irq_data *d)
> +{
> +	writel(d->hwirq - GF_IRQ_OFFSET,
> +	       gf_pic_base + GF_PIC_ENABLE);
> +	irq_enable_hazard();
> +}
> +
> +static inline void mask_goldfish_irq(struct irq_data *d)
> +{
> +	writel(d->hwirq - GF_IRQ_OFFSET,
> +	       gf_pic_base + GF_PIC_DISABLE);
> +	irq_disable_hazard();
> +}
> +
> +static struct irq_chip goldfish_irq_controller = {
> +	.name		= "Goldfish PIC",
> +	.irq_ack	= mask_goldfish_irq,

I'm slightly puzzled.

> +	.irq_mask	= mask_goldfish_irq,
> +	.irq_mask_ack	= mask_goldfish_irq,

What does it mean to have irq_mask_ack implemented as mask?

> +	.irq_unmask	= unmask_goldfish_irq,
> +	.irq_eoi	= unmask_goldfish_irq,

Really? Are you joking?

> +	.irq_disable	= mask_goldfish_irq,
> +	.irq_enable	= unmask_goldfish_irq,

If enable/disable are the same as mask/unmask, you don't need separate
entry points.

> +};
> +
> +static void goldfish_irq_dispatch(void)
> +{
> +	u32 irq;
> +	u32 virq;
> +
> +	irq = readl(gf_pic_base + GF_PIC_NUMBER);
> +	if (irq == 0) {
> +		/* Timer interrupt */
> +		do_IRQ(GF_CPU_IRQ_COMPARE);
> +		return;
> +	}

Why isn't this indirected through the irqdomain just like the rest?

> +
> +	virq = irq_linear_revmap(irq_domain, irq);
> +	virq += GF_IRQ_OFFSET;


?????? Why do you have to add an offset here? The whole point of an
irqdomain is to convert a hwirq to an irq. If you need to adjust it, it
means you're doing something completely wrong the first place.

> +	do_IRQ(virq);
> +}
> +
> +static void goldfish_ip2_irq_dispatch(struct irq_desc *desc)
> +{
> +	unsigned long pending = read_c0_cause() & read_c0_status() & ST0_IM;
> +
> +	if (pending & CAUSEF_IP2)
> +		goldfish_irq_dispatch();
> +	else
> +		spurious_interrupt();

chained_irq_enter/exit when this is a chained interrupt handler?

> +}
> +
> +static int goldfish_pic_map(struct irq_domain *d, unsigned int irq,
> +			    irq_hw_number_t hw)
> +{
> +	if (cpu_has_vint)
> +		set_vi_handler(hw, goldfish_irq_dispatch);
> +
> +	irq_set_chip_and_handler(irq, &goldfish_irq_controller,
> +				 handle_level_irq);
> +
> +	return 0;
> +}
> +
> +static const struct irq_domain_ops gf_pic_irq_domain_ops = {
> +	.map = goldfish_pic_map,
> +	.xlate = irq_domain_xlate_onetwocell,

Why "twocell"? You only seem to handle level interrupts, so one single
cell should be enough, right? That's even the way you document it in the
DT...

> +};
> +
> +static struct irqaction cascade = {
> +	.handler	= no_action,
> +	.flags		= IRQF_PROBE_SHARED,
> +	.name		= "cascade",
> +};
> +
> +static void __init __goldfish_pic_init(struct device_node *of_node)

Why this __ prefix?

> +{
> +	gf_pic_base = of_iomap(of_node, 0);
> +	if (!gf_pic_base)
> +		panic("Failed to map Goldfish PIC base : No such device!");

No such device? Or more accurately out of space to do the IO mapping?

> +
> +	/* Mask interrupts. */
> +	writel(1, gf_pic_base + GF_PIC_DISABLE_ALL);
> +
> +	if (!cpu_has_vint)
> +		irq_set_chained_handler(GF_CPU_IRQ_PIC,
> +					goldfish_ip2_irq_dispatch);
> +
> +	setup_irq(GF_CPU_IRQ_PIC, &cascade);
> +
> +	irq_domain = irq_domain_add_legacy(of_node, GF_NR_IRQS,
> +					   GF_IRQ_OFFSET, 0,
> +					   &gf_pic_irq_domain_ops, NULL);
> +	if (!irq_domain)
> +		panic("Failed to add irqdomain for Goldfish PIC");
> +}
> +
> +int __init goldfish_pic_of_init(struct device_node *of_node,
> +				struct device_node *parent)

Why isn't it static?

> +{
> +	__goldfish_pic_init(of_node);

Why do we need to indirect it at all?

> +	return 0;
> +}
> +
> +IRQCHIP_DECLARE(google_gf_pic, "google,goldfish-pic", goldfish_pic_of_init);
> +
> 

Really, this is not any better than the initial version. You clearly
have not tried to understand the requirements for an interrupt
controller with respect to the flows it uses. Also, the use of the
irqdomain is completely backward.

	M.
-- 
Jazz is not dead. It just smells funny...

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