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| Started by | Ben Hutchings <ben@decadent.org.uk> |
|---|---|
| First post | 2017-08-18 15:50 +0200 |
| Last post | 2017-08-21 04:30 +0200 |
| Articles | 2 — 2 participants |
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[PATCH 3.16 032/134] MIPS: Loongson-3: Select MIPS_L1_CACHE_SHIFT_6 Ben Hutchings <ben@decadent.org.uk> - 2017-08-18 15:50 +0200
Re: [PATCH 3.16 032/134] MIPS: Loongson-3: Select MIPS_L1_CACHE_SHIFT_6 Huacai Chen <chenhc@lemote.com> - 2017-08-21 04:30 +0200
| From | Ben Hutchings <ben@decadent.org.uk> |
|---|---|
| Date | 2017-08-18 15:50 +0200 |
| Subject | [PATCH 3.16 032/134] MIPS: Loongson-3: Select MIPS_L1_CACHE_SHIFT_6 |
| Message-ID | <ufPOW-4q2-17@gated-at.bofh.it> |
3.16.47-rc1 review patch. If anyone has any objections, please let me know. ------------------ From: Huacai Chen <chenhc@lemote.com> commit 17c99d9421695a0e0de18bf1e7091d859e20ec1d upstream. Some newer Loongson-3 have 64 bytes cache lines, so select MIPS_L1_CACHE_SHIFT_6. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J . Hill <Steven.Hill@caviumnetworks.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/15755/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> [bwh: Backported to 3.16: adjust context] Signed-off-by: Ben Hutchings <ben@decadent.org.uk> --- arch/mips/Kconfig | 1 + 1 file changed, 1 insertion(+) --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1193,6 +1193,7 @@ config CPU_LOONGSON3 select CPU_SUPPORTS_HUGEPAGES select WEAK_ORDERING select WEAK_REORDERING_BEYOND_LLSC + select MIPS_L1_CACHE_SHIFT_6 help The Loongson 3 processor implements the MIPS64R2 instruction set with many extensions.
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| From | Huacai Chen <chenhc@lemote.com> |
|---|---|
| Date | 2017-08-21 04:30 +0200 |
| Message-ID | <ugKDw-6Kr-11@gated-at.bofh.it> |
| In reply to | #1715027 |
3.16 doesn't need this, because 3.16 doesn't support Loongson-3 R2/R3. Huacai On Fri, Aug 18, 2017 at 9:13 PM, Ben Hutchings <ben@decadent.org.uk> wrote: > 3.16.47-rc1 review patch. If anyone has any objections, please let me know. > > ------------------ > > From: Huacai Chen <chenhc@lemote.com> > > commit 17c99d9421695a0e0de18bf1e7091d859e20ec1d upstream. > > Some newer Loongson-3 have 64 bytes cache lines, so select > MIPS_L1_CACHE_SHIFT_6. > > Signed-off-by: Huacai Chen <chenhc@lemote.com> > Cc: John Crispin <john@phrozen.org> > Cc: Steven J . Hill <Steven.Hill@caviumnetworks.com> > Cc: Fuxin Zhang <zhangfx@lemote.com> > Cc: Zhangjin Wu <wuzhangjin@gmail.com> > Cc: linux-mips@linux-mips.org > Patchwork: https://patchwork.linux-mips.org/patch/15755/ > Signed-off-by: Ralf Baechle <ralf@linux-mips.org> > [bwh: Backported to 3.16: adjust context] > Signed-off-by: Ben Hutchings <ben@decadent.org.uk> > --- > arch/mips/Kconfig | 1 + > 1 file changed, 1 insertion(+) > > --- a/arch/mips/Kconfig > +++ b/arch/mips/Kconfig > @@ -1193,6 +1193,7 @@ config CPU_LOONGSON3 > select CPU_SUPPORTS_HUGEPAGES > select WEAK_ORDERING > select WEAK_REORDERING_BEYOND_LLSC > + select MIPS_L1_CACHE_SHIFT_6 > help > The Loongson 3 processor implements the MIPS64R2 instruction > set with many extensions. > >
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