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[PATCH v1 0/4] KVM: MMU: 5 level EPT/shadow support

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  [PATCH v1 0/4] KVM: MMU: 5 level EPT/shadow support Yu Zhang <yu.c.zhang@linux.intel.com> - 2017-08-12 16:00 +0200
    Re: [PATCH v1 0/4] KVM: MMU: 5 level EPT/shadow support Paolo Bonzini <pbonzini@redhat.com> - 2017-08-14 09:40 +0200

#1710286 — [PATCH v1 0/4] KVM: MMU: 5 level EPT/shadow support

Intel's existing processors limit the maximum linear address width to
48 bits, and the maximum physical address width to 46 bits. And the
upcoming processors will extend maximum linear address width to 57 bits
and maximum physical address width can go upto 52 bits in practical.

With linear address width greater than 48, a new paging mode in IA-32e
is introduced - 5 level paging(also known as LA57). And to support VMs
with this feature, KVM MMU code need to be extended. 

And to achieve this, this patchset:
1> leverages 2 qemu parameters: +la57 and phys-bits to expose wider linear
address width and physical address width to the VM;
2> extends shadow logic to construct 5 level shadow page for VMs running
in LA57 mode;
3> extends ept logic to construct 5 level ept table for VMs whose maximum
physical width exceeds 48 bits.

Yu Zhang (4):
  KVM: MMU: check guest CR3 reserved bits based on its physical address
    width.
  KVM: MMU: Rename PT64_ROOT_LEVEL to PT64_ROOT_4LEVEL.
  KVM: MMU: Add 5 level EPT & Shadow page table support.
  KVM: MMU: Expose the LA57 feature to VM.

 arch/x86/include/asm/kvm_host.h | 29 +++++----------------
 arch/x86/include/asm/vmx.h      |  1 +
 arch/x86/kvm/cpuid.c            | 21 ++++++++++-----
 arch/x86/kvm/emulate.c          | 24 +++++++++++------
 arch/x86/kvm/kvm_cache_regs.h   |  2 +-
 arch/x86/kvm/mmu.c              | 58 +++++++++++++++++++++++++----------------
 arch/x86/kvm/mmu.h              |  8 +++++-
 arch/x86/kvm/mmu_audit.c        |  4 +--
 arch/x86/kvm/svm.c              |  6 ++---
 arch/x86/kvm/vmx.c              | 27 ++++++++++++-------
 arch/x86/kvm/x86.c              | 15 ++++++-----
 arch/x86/kvm/x86.h              | 44 +++++++++++++++++++++++++++++++
 12 files changed, 158 insertions(+), 81 deletions(-)

-- 
2.5.0

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#1710693

On 12/08/2017 15:35, Yu Zhang wrote:
> Intel's existing processors limit the maximum linear address width to
> 48 bits, and the maximum physical address width to 46 bits. And the
> upcoming processors will extend maximum linear address width to 57 bits
> and maximum physical address width can go upto 52 bits in practical.
> 
> With linear address width greater than 48, a new paging mode in IA-32e
> is introduced - 5 level paging(also known as LA57). And to support VMs
> with this feature, KVM MMU code need to be extended. 
> 
> And to achieve this, this patchset:
> 1> leverages 2 qemu parameters: +la57 and phys-bits to expose wider linear
> address width and physical address width to the VM;
> 2> extends shadow logic to construct 5 level shadow page for VMs running
> in LA57 mode;
> 3> extends ept logic to construct 5 level ept table for VMs whose maximum
> physical width exceeds 48 bits.

Thanks, this looks good.  I only had a few suggestions in my reply to
patch 3.

Paolo

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