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| Started by | "Ong, Hean Loong" <hean.loong.ong@intel.com> |
|---|---|
| First post | 2017-08-14 04:30 +0200 |
| Last post | 2017-08-14 04:30 +0200 |
| Articles | 1 — 1 participant |
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Re: [PATCHv6 3/3] ARM:drm ivip Intel FPGA Video and Image Processing Suite "Ong, Hean Loong" <hean.loong.ong@intel.com> - 2017-08-14 04:30 +0200
| From | "Ong, Hean Loong" <hean.loong.ong@intel.com> |
|---|---|
| Date | 2017-08-14 04:30 +0200 |
| Subject | Re: [PATCHv6 3/3] ARM:drm ivip Intel FPGA Video and Image Processing Suite |
| Message-ID | <uediF-6Mg-3@gated-at.bofh.it> |
On Fri, 2017-08-11 at 08:21 -0700, Randy Dunlap wrote: > On 08/10/2017 11:49 PM, Hean-Loong, Ong wrote: > > > > diff --git a/drivers/gpu/drm/ivip/Kconfig > > b/drivers/gpu/drm/ivip/Kconfig > > new file mode 100644 > > index 0000000..398c9ab > > --- /dev/null > > +++ b/drivers/gpu/drm/ivip/Kconfig > > @@ -0,0 +1,14 @@ > > +config DRM_IVIP > > + tristate "Intel FGPA Video and Image Processing" > > + depends on DRM && OF > > + select DRM_GEM_CMA_HELPER > > + select DRM_KMS_HELPER > > + select DRM_KMS_FB_HELPER > > + select DRM_KMS_CMA_HELPER > > + help > > + Choose this option if you have a Intel FPGA Arria 10 > > system > an > > > > > + and above with an Intel Display Port IP. This does not > > support > > + legacy Intel FPGA Cyclone V display port. Currently > > only single > > + frame buffer is supported. Note that ACPI and X_86 > > architecture > > + is not supported for Arria10.If M is selected the > > module will be > Arria10. If M is > > > > > + called ivip. > All of the help text should be indented with one tab + 2 spaces > according to coding-style.rst. > > Noted.
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