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Groups > linux.kernel > #1708270 > unrolled thread

[PATCH 1/2] clk: uniphier: add audio system clock

Started byKatsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
First post2017-08-10 09:30 +0200
Last post2017-08-10 13:10 +0200
Articles 4 — 2 participants

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  [PATCH 1/2] clk: uniphier: add audio system clock Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> - 2017-08-10 09:30 +0200
    [PATCH 2/2] clk: uniphier: add video input subsystem clock Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com> - 2017-08-10 09:30 +0200
      Re: [PATCH 2/2] clk: uniphier: add video input subsystem clock Masahiro Yamada <yamada.masahiro@socionext.com> - 2017-08-10 13:10 +0200
    Re: [PATCH 1/2] clk: uniphier: add audio system clock Masahiro Yamada <yamada.masahiro@socionext.com> - 2017-08-10 13:10 +0200

#1708270 — [PATCH 1/2] clk: uniphier: add audio system clock

FromKatsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
Date2017-08-10 09:30 +0200
Subject[PATCH 1/2] clk: uniphier: add audio system clock
Message-ID<ucQ4O-2jh-3@gated-at.bofh.it>
Add clock for audio subsystem (AIO) and SoC internal audio codec
(EVEA) on UniPhier LD11/LD20 SoCs.

Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
---
 drivers/clk/uniphier/clk-uniphier-sys.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c
index ad0218182a9f..7c4528d0fb6e 100644
--- a/drivers/clk/uniphier/clk-uniphier-sys.c
+++ b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -57,6 +57,14 @@
 #define UNIPHIER_PRO4_SYS_CLK_USB3(idx, ch)				\
 	UNIPHIER_CLK_GATE("usb3" #ch, (idx), NULL, 0x2104, 16 + (ch))
 
+#define UNIPHIER_LD11_SYS_CLK_AIO(idx)					\
+	UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 10),		\
+	UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2108, 0)
+
+#define UNIPHIER_LD11_SYS_CLK_EVEA(idx)					\
+	UNIPHIER_CLK_FACTOR("evea-io100m", -1, "spll", 1, 20),		\
+	UNIPHIER_CLK_GATE("evea", (idx), "evea-io100m", 0x2108, 1)
+
 const struct uniphier_clk_data uniphier_sld3_sys_clk_data[] = {
 	UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1),		/* 1597.44 MHz */
 	UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512),	/* 288 MHz */
@@ -158,6 +166,8 @@ const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = {
 	/* Index 5 reserved for eMMC PHY */
 	UNIPHIER_LD11_SYS_CLK_STDMAC(8),			/* HSC, MIO */
 	UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25),
+	UNIPHIER_LD11_SYS_CLK_AIO(40),
+	UNIPHIER_LD11_SYS_CLK_EVEA(41),
 	/* CPU gears */
 	UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
 	UNIPHIER_CLK_DIV4("mpll", 2, 3, 4, 8),
@@ -194,6 +204,8 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
 	UNIPHIER_CLK_GATE("usb30", 14, NULL, 0x210c, 14),
 	UNIPHIER_CLK_GATE("usb30-phy0", 16, NULL, 0x210c, 12),
 	UNIPHIER_CLK_GATE("usb30-phy1", 17, NULL, 0x210c, 13),
+	UNIPHIER_LD11_SYS_CLK_AIO(40),
+	UNIPHIER_LD11_SYS_CLK_EVEA(41),
 	/* CPU gears */
 	UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
 	UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),
-- 
2.13.2

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#1708272 — [PATCH 2/2] clk: uniphier: add video input subsystem clock

FromKatsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
Date2017-08-10 09:30 +0200
Subject[PATCH 2/2] clk: uniphier: add video input subsystem clock
Message-ID<ucQ4O-2jh-5@gated-at.bofh.it>
In reply to#1708270
Add a clock for video input subsystem (EXIV) on
UniPhier LD11/LD20 SoCs.

Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
---
 drivers/clk/uniphier/clk-uniphier-sys.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c
index 7c4528d0fb6e..c60aa586fea7 100644
--- a/drivers/clk/uniphier/clk-uniphier-sys.c
+++ b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -65,6 +65,10 @@
 	UNIPHIER_CLK_FACTOR("evea-io100m", -1, "spll", 1, 20),		\
 	UNIPHIER_CLK_GATE("evea", (idx), "evea-io100m", 0x2108, 1)
 
+#define UNIPHIER_LD11_SYS_CLK_EXIV(idx)					\
+	UNIPHIER_CLK_FACTOR("exiv-io200m", -1, "spll", 1, 10),		\
+	UNIPHIER_CLK_GATE("exiv", (idx), "exiv-io200m", 0x2110, 2)
+
 const struct uniphier_clk_data uniphier_sld3_sys_clk_data[] = {
 	UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1),		/* 1597.44 MHz */
 	UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512),	/* 288 MHz */
@@ -168,6 +172,7 @@ const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = {
 	UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25),
 	UNIPHIER_LD11_SYS_CLK_AIO(40),
 	UNIPHIER_LD11_SYS_CLK_EVEA(41),
+	UNIPHIER_LD11_SYS_CLK_EXIV(42),
 	/* CPU gears */
 	UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
 	UNIPHIER_CLK_DIV4("mpll", 2, 3, 4, 8),
@@ -206,6 +211,7 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
 	UNIPHIER_CLK_GATE("usb30-phy1", 17, NULL, 0x210c, 13),
 	UNIPHIER_LD11_SYS_CLK_AIO(40),
 	UNIPHIER_LD11_SYS_CLK_EVEA(41),
+	UNIPHIER_LD11_SYS_CLK_EXIV(42),
 	/* CPU gears */
 	UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
 	UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),
-- 
2.13.2

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#1708443 — Re: [PATCH 2/2] clk: uniphier: add video input subsystem clock

FromMasahiro Yamada <yamada.masahiro@socionext.com>
Date2017-08-10 13:10 +0200
SubjectRe: [PATCH 2/2] clk: uniphier: add video input subsystem clock
Message-ID<ucTvJ-4OI-31@gated-at.bofh.it>
In reply to#1708272
2017-08-10 16:23 GMT+09:00 Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>:
> Add a clock for video input subsystem (EXIV) on
> UniPhier LD11/LD20 SoCs.
>
> Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>


Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>

-- 
Best Regards
Masahiro Yamada

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#1708442

FromMasahiro Yamada <yamada.masahiro@socionext.com>
Date2017-08-10 13:10 +0200
Message-ID<ucTvI-4OI-29@gated-at.bofh.it>
In reply to#1708270
2017-08-10 16:23 GMT+09:00 Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>:
> Add clock for audio subsystem (AIO) and SoC internal audio codec
> (EVEA) on UniPhier LD11/LD20 SoCs.
>
> Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
> ---

Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>




-- 
Best Regards
Masahiro Yamada

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