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| Started by | Boris Brezillon <boris.brezillon@free-electrons.com> |
|---|---|
| First post | 2017-08-03 17:50 +0200 |
| Last post | 2017-08-03 20:00 +0200 |
| Articles | 2 — 2 participants |
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Re: [PATCH v2 02/25] mtd: nand: qcom: program NAND_DEV_CMD_VLD register Boris Brezillon <boris.brezillon@free-electrons.com> - 2017-08-03 17:50 +0200
Re: [PATCH v2 02/25] mtd: nand: qcom: program NAND_DEV_CMD_VLD register Abhishek Sahu <absahu@codeaurora.org> - 2017-08-03 20:00 +0200
| From | Boris Brezillon <boris.brezillon@free-electrons.com> |
|---|---|
| Date | 2017-08-03 17:50 +0200 |
| Subject | Re: [PATCH v2 02/25] mtd: nand: qcom: program NAND_DEV_CMD_VLD register |
| Message-ID | <uaqxP-1Y5-11@gated-at.bofh.it> |
On Wed, 19 Jul 2017 17:17:50 +0530
Abhishek Sahu <absahu@codeaurora.org> wrote:
> The current driver is failing without complete bootchain since
> NAND_DEV_CMD_VLD value is not valid.
>
> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
BTW, do you want to backport this fix? Maybe you add Fixes and
Cc-stable tags...
> ---
> drivers/mtd/nand/qcom_nandc.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
> index bc0408c..f3b995d 100644
> --- a/drivers/mtd/nand/qcom_nandc.c
> +++ b/drivers/mtd/nand/qcom_nandc.c
> @@ -148,6 +148,9 @@
> #define FETCH_ID 0xb
> #define RESET_DEVICE 0xd
>
> +/* Value for NAND_DEV_CMD_VLD */
> +#define NAND_DEV_CMD_VLD_VAL 0x1d
> +
> /*
> * the NAND controller performs reads/writes with ECC in 516 byte chunks.
> * the driver calls the chunks 'step' or 'codeword' interchangeably
> @@ -1972,6 +1975,7 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
> {
> /* kill onenand */
> nandc_write(nandc, SFLASHC_BURST_CFG, 0);
> + nandc_write(nandc, NAND_DEV_CMD_VLD, NAND_DEV_CMD_VLD_VAL);
>
> /* enable ADM DMA */
> nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
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| From | Abhishek Sahu <absahu@codeaurora.org> |
|---|---|
| Date | 2017-08-03 20:00 +0200 |
| Message-ID | <uaszE-3m4-13@gated-at.bofh.it> |
| In reply to | #1703208 |
On 2017-08-03 21:18, Boris Brezillon wrote:
> On Wed, 19 Jul 2017 17:17:50 +0530
> Abhishek Sahu <absahu@codeaurora.org> wrote:
>
>> The current driver is failing without complete bootchain since
>> NAND_DEV_CMD_VLD value is not valid.
>>
>> Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
>
> BTW, do you want to backport this fix? Maybe you add Fixes and
> Cc-stable tags...
>
It was not a critical fix but its better to backport this.
I will add these tags in v3.
>> ---
>> drivers/mtd/nand/qcom_nandc.c | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/drivers/mtd/nand/qcom_nandc.c
>> b/drivers/mtd/nand/qcom_nandc.c
>> index bc0408c..f3b995d 100644
>> --- a/drivers/mtd/nand/qcom_nandc.c
>> +++ b/drivers/mtd/nand/qcom_nandc.c
>> @@ -148,6 +148,9 @@
>> #define FETCH_ID 0xb
>> #define RESET_DEVICE 0xd
>>
>> +/* Value for NAND_DEV_CMD_VLD */
>> +#define NAND_DEV_CMD_VLD_VAL 0x1d
>> +
>> /*
>> * the NAND controller performs reads/writes with ECC in 516 byte
>> chunks.
>> * the driver calls the chunks 'step' or 'codeword' interchangeably
>> @@ -1972,6 +1975,7 @@ static int qcom_nandc_setup(struct
>> qcom_nand_controller *nandc)
>> {
>> /* kill onenand */
>> nandc_write(nandc, SFLASHC_BURST_CFG, 0);
>> + nandc_write(nandc, NAND_DEV_CMD_VLD, NAND_DEV_CMD_VLD_VAL);
>>
>> /* enable ADM DMA */
>> nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN);
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