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| Started by | George Wilson <ltcgcw@us.ibm.com> |
|---|---|
| First post | 2017-08-01 18:00 +0200 |
| Last post | 2017-08-01 18:00 +0200 |
| Articles | 1 — 1 participant |
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Re: [tpmdd-devel] tpm: read burstcount from TPM_STS in one 32-bit transaction George Wilson <ltcgcw@us.ibm.com> - 2017-08-01 18:00 +0200
| From | George Wilson <ltcgcw@us.ibm.com> |
|---|---|
| Date | 2017-08-01 18:00 +0200 |
| Subject | Re: [tpmdd-devel] tpm: read burstcount from TPM_STS in one 32-bit transaction |
| Message-ID | <u9HKp-5Q8-3@gated-at.bofh.it> |
On Tue, Jul 25, 2017 at 10:36:11AM -0700, James Bottomley wrote:
> On Tue, 2017-07-25 at 15:04 +0200, Michal Suchánek wrote:
> > Hello,
> >
> > in commit 9754d45e9970 ("tpm: read burstcount from TPM_STS in one
> > 32-bit transaction") you change reading of two 8-bit values to one
> > 32bit read. This is obviously wrong wrt endianess unless the
> > underlying tpm_tis_read32 does endian conversion.
>
> Some of the bus read primitives do do endianness conversions. The
> problem is with the SPI attachment, which has unclear endianness. A
> standard PCI bus attachment uses ioread32() which automatically
> transforms from a little endian bus to the cpu endianness, however SPI
> is forced to transfer the bytes one at a time over the serial bus and
> then transform. The assumption seems to be that the TIS TPM is
> replying in little endian format when SPI connected.
>
> We can probably get the PPC people to confirm this, I believe they have
> a SPI attached TPM.
All the current OpenPOWER hardware designs I'm aware of have the TPM on
I2C. Trusted Computing support in OpenPOWER firmware depends on it
being on I2C.
>
> James
>
>
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