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Groups > linux.kernel > #1701018 > unrolled thread

[PATCH 00/13] Allwinner H3 DE2 basical support

Started byIcenowy Zheng <icenowy@aosc.io>
First post2017-08-01 15:20 +0200
Last post2017-08-02 06:50 +0200
Articles 20 on this page of 32 — 5 participants

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Contents

  [PATCH 00/13] Allwinner H3 DE2 basical support Icenowy Zheng <icenowy@aosc.io> - 2017-08-01 15:20 +0200
    [PATCH 03/13] drm: sun4i: add support for H3's TCON Icenowy Zheng <icenowy@aosc.io> - 2017-08-01 15:20 +0200
      Re: [linux-sunxi] [PATCH 03/13] drm: sun4i: add support for H3's TCON Chen-Yu Tsai <wens@csie.org> - 2017-08-04 06:10 +0200
    [PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support Icenowy Zheng <icenowy@aosc.io> - 2017-08-01 15:20 +0200
      Re: [linux-sunxi] [PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support Jernej Škrabec <jernej.skrabec@siol.net> - 2017-08-02 07:00 +0200
        Re: [linux-sunxi] [PATCH 01/13] dt-bindings: update the binding for  Allwinner H3 DE2 support icenowy@aosc.io - 2017-08-02 07:10 +0200
          Re: [linux-sunxi] [PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support Jernej Škrabec <jernej.skrabec@siol.net> - 2017-08-02 21:10 +0200
            Re: [linux-sunxi] [PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support Icenowy Zheng <icenowy@aosc.io> - 2017-08-03 01:00 +0200
            Re: [linux-sunxi] [PATCH 01/13] dt-bindings: update the binding for  Allwinner H3 DE2 support Rob Herring <robh@kernel.org> - 2017-08-10 02:30 +0200
      Re: [PATCH 01/13] dt-bindings: update the binding for Allwinner H3  DE2 support Rob Herring <robh@kernel.org> - 2017-08-10 02:20 +0200
    [PATCH 04/13] drm: sun4i: add compatible for H3 display engine Icenowy Zheng <icenowy@aosc.io> - 2017-08-01 15:40 +0200
    [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock Icenowy Zheng <icenowy@aosc.io> - 2017-08-01 15:40 +0200
      Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add  CLK_SET_RATE_PARENT flag for H3 HDMI clock Chen-Yu Tsai <wens@csie.org> - 2017-08-04 06:20 +0200
        Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock Icenowy Zheng <icenowy@aosc.io> - 2017-08-04 06:20 +0200
          Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add  CLK_SET_RATE_PARENT flag for H3 HDMI clock Chen-Yu Tsai <wens@csie.org> - 2017-08-04 06:40 +0200
            Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock Jernej Škrabec <jernej.skrabec@siol.net> - 2017-08-04 11:00 +0200
              Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock Icenowy Zheng <icenowy@aosc.io> - 2017-08-04 11:10 +0200
                Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add  CLK_SET_RATE_PARENT flag for H3 HDMI clock Chen-Yu Tsai <wens@csie.org> - 2017-08-04 11:40 +0200
              Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add  CLK_SET_RATE_PARENT flag for H3 HDMI clock Chen-Yu Tsai <wens@csie.org> - 2017-08-04 11:30 +0200
                Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock Jernej Škrabec <jernej.skrabec@siol.net> - 2017-08-04 15:50 +0200
                  Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add  CLK_SET_RATE_PARENT flag for H3 HDMI clock Chen-Yu Tsai <wens@csie.org> - 2017-08-04 16:20 +0200
    [PATCH 09/13] [NOT FOR REVIEW NOW] drm: bridge: Add a pre_init function for the dw_hdmi driver Icenowy Zheng <icenowy@aosc.io> - 2017-08-01 15:40 +0200
    [PATCH 08/13] [NOT FOR REVIEW NOW] drm: bridge: Enable polling hpd event in dw_hdmi Icenowy Zheng <icenowy@aosc.io> - 2017-08-01 15:40 +0200
    [PATCH 07/13] ARM: sun8i: h3: add display engine pipeline barebone Icenowy Zheng <icenowy@aosc.io> - 2017-08-01 15:40 +0200
      Re: [linux-sunxi] [PATCH 07/13] ARM: sun8i: h3: add display engine pipeline barebone Jernej Škrabec <jernej.skrabec@siol.net> - 2017-08-02 06:50 +0200
        Re: [linux-sunxi] [PATCH 07/13] ARM: sun8i: h3: add display engine  pipeline barebone icenowy@aosc.io - 2017-08-02 07:10 +0200
    [PATCH 05/13] clk: sunxi-ng: allow CLK_DE to set CLK_PLL_DE for H3 Icenowy Zheng <icenowy@aosc.io> - 2017-08-01 15:40 +0200
    [PATCH 06/13] clk: sunxi-ng: export CLK_PLL_DE for H3 Icenowy Zheng <icenowy@aosc.io> - 2017-08-01 15:40 +0200
    [PATCH 12/13] [NOT FOR REVIEW NOW] ARM: sun8i: h3: enable DesignWare HDMI controller Icenowy Zheng <icenowy@aosc.io> - 2017-08-01 15:50 +0200
    [PATCH 13/13] [NOT FOR REVIEW NOW] ARM: sun8i: h3: enable HDMI output on Orange Pi PC Icenowy Zheng <icenowy@aosc.io> - 2017-08-01 15:50 +0200
    [PATCH 11/13] [NOT FOR REVIEW NOW] drm: sun4i: Add a glue for the DesignWare HDMI controller in H3 Icenowy Zheng <icenowy@aosc.io> - 2017-08-01 15:50 +0200
    Re: [linux-sunxi] [PATCH 00/13] Allwinner H3 DE2 basical support Chen-Yu Tsai <wens@csie.org> - 2017-08-02 06:50 +0200

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#1701018 — [PATCH 00/13] Allwinner H3 DE2 basical support

FromIcenowy Zheng <icenowy@aosc.io>
Date2017-08-01 15:20 +0200
Subject[PATCH 00/13] Allwinner H3 DE2 basical support
Message-ID<u9Ffz-4tk-3@gated-at.bofh.it>
Allwinner H3 features a "Display Engine 2.0", which needs some support
to be present in the DRM driver.

This patchset is now a basical version, which dropped some features I
used to submitted:
- TVE support (not so high priority now)
- Multi-pipeline support (also not so high priority now due to no TVE)

The last 6 patches are only used for testing this patchset, and they're
going to be sent by Jernej Skrabec after this patchset is applied.

Icenowy Zheng (9):
  dt-bindings: update the binding for Allwinner H3 DE2 support
  drm: sun4i: add support for H3 mixers
  drm: sun4i: add support for H3's TCON
  drm: sun4i: add compatible for H3 display engine
  clk: sunxi-ng: allow CLK_DE to set CLK_PLL_DE for H3
  clk: sunxi-ng: export CLK_PLL_DE for H3
  ARM: sun8i: h3: add display engine pipeline barebone
  [NOT FOR REVIEW NOW] ARM: sun8i: h3: enable DesignWare HDMI controller
  [NOT FOR REVIEW NOW] ARM: sun8i: h3: enable HDMI output on Orange Pi
    PC

Jernej Skrabec (4):
  [NOT FOR REVIEW NOW] drm: bridge: Enable polling hpd event in dw_hdmi
  [NOT FOR REVIEW NOW] drm: bridge: Add a pre_init function for the
    dw_hdmi driver
  [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3
    HDMI clock
  [NOT FOR REVIEW NOW] drm: sun4i: Add a glue for the DesignWare HDMI
    controller in H3

 .../bindings/display/sunxi/sun4i-drm.txt           |  25 +-
 arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts         |  16 +
 arch/arm/boot/dts/sun8i-h3.dtsi                    | 205 +++++++++
 drivers/clk/sunxi-ng/ccu-sun8i-h3.c                |   4 +-
 drivers/clk/sunxi-ng/ccu-sun8i-h3.h                |   3 +-
 drivers/gpu/drm/bridge/synopsys/dw-hdmi.c          |   9 +-
 drivers/gpu/drm/sun4i/Kconfig                      |   9 +
 drivers/gpu/drm/sun4i/Makefile                     |   1 +
 drivers/gpu/drm/sun4i/sun4i_drv.c                  |   2 +
 drivers/gpu/drm/sun4i/sun4i_tcon.c                 |  43 +-
 drivers/gpu/drm/sun4i/sun4i_tcon.h                 |   1 +
 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c              | 462 +++++++++++++++++++++
 drivers/gpu/drm/sun4i/sun8i_mixer.c                |  18 +
 include/drm/bridge/dw_hdmi.h                       |   2 +
 include/dt-bindings/clock/sun8i-h3-ccu.h           |   2 +
 15 files changed, 781 insertions(+), 21 deletions(-)
 create mode 100644 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c

-- 
2.13.0

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#1701021 — [PATCH 03/13] drm: sun4i: add support for H3's TCON

FromIcenowy Zheng <icenowy@aosc.io>
Date2017-08-01 15:20 +0200
Subject[PATCH 03/13] drm: sun4i: add support for H3's TCON
Message-ID<u9FfA-4tk-13@gated-at.bofh.it>
In reply to#1701018
From: Icenowy Zheng <icenowy@aosc.xyz>

Allwinner H3 has two special TCONs without channel 0.

Add support for this kind of TCON.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 drivers/gpu/drm/sun4i/sun4i_drv.c  |  1 +
 drivers/gpu/drm/sun4i/sun4i_tcon.c | 43 +++++++++++++++++++++++++++-----------
 drivers/gpu/drm/sun4i/sun4i_tcon.h |  1 +
 3 files changed, 33 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c
index ace59651892f..fd99fe8a4df7 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -188,6 +188,7 @@ static bool sun4i_drv_node_is_tcon(struct device_node *node)
 		of_device_is_compatible(node, "allwinner,sun6i-a31-tcon") ||
 		of_device_is_compatible(node, "allwinner,sun6i-a31s-tcon") ||
 		of_device_is_compatible(node, "allwinner,sun8i-a33-tcon") ||
+		of_device_is_compatible(node, "allwinner,sun8i-h3-tcon") ||
 		of_device_is_compatible(node, "allwinner,sun8i-v3s-tcon");
 }
 
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index d9791292553e..270f09e381a5 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -59,6 +59,7 @@ void sun4i_tcon_channel_disable(struct sun4i_tcon *tcon, int channel)
 
 	/* Disable the TCON's channel */
 	if (channel == 0) {
+		WARN_ON(!tcon->quirks->has_channel_0);
 		regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
 				   SUN4I_TCON0_CTL_TCON_ENABLE, 0);
 		clk_disable_unprepare(tcon->dclk);
@@ -78,6 +79,7 @@ void sun4i_tcon_channel_enable(struct sun4i_tcon *tcon, int channel)
 
 	/* Enable the TCON's channel */
 	if (channel == 0) {
+		WARN_ON(!tcon->quirks->has_channel_0);
 		regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
 				   SUN4I_TCON0_CTL_TCON_ENABLE,
 				   SUN4I_TCON0_CTL_TCON_ENABLE);
@@ -157,6 +159,8 @@ void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon,
 	u8 clk_delay;
 	u32 val = 0;
 
+	WARN_ON(!tcon->quirks->has_channel_0);
+
 	/* Configure the dot clock */
 	clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
 
@@ -366,10 +370,12 @@ static int sun4i_tcon_init_clocks(struct device *dev,
 	}
 	clk_prepare_enable(tcon->clk);
 
-	tcon->sclk0 = devm_clk_get(dev, "tcon-ch0");
-	if (IS_ERR(tcon->sclk0)) {
-		dev_err(dev, "Couldn't get the TCON channel 0 clock\n");
-		return PTR_ERR(tcon->sclk0);
+	if (tcon->quirks->has_channel_0) {
+		tcon->sclk0 = devm_clk_get(dev, "tcon-ch0");
+		if (IS_ERR(tcon->sclk0)) {
+			dev_err(dev, "Couldn't get the TCON channel 0 clock\n");
+			return PTR_ERR(tcon->sclk0);
+		}
 	}
 
 	if (tcon->quirks->has_channel_1) {
@@ -551,10 +557,12 @@ static int sun4i_tcon_bind(struct device *dev, struct device *master,
 		goto err_free_clocks;
 	}
 
-	ret = sun4i_dclk_create(dev, tcon);
-	if (ret) {
-		dev_err(dev, "Couldn't create our TCON dot clock\n");
-		goto err_free_clocks;
+	if (tcon->quirks->has_channel_0) {
+		ret = sun4i_dclk_create(dev, tcon);
+		if (ret) {
+			dev_err(dev, "Couldn't create our TCON dot clock\n");
+			goto err_free_clocks;
+		}
 	}
 
 	ret = sun4i_tcon_init_irq(dev, tcon);
@@ -579,7 +587,8 @@ static int sun4i_tcon_bind(struct device *dev, struct device *master,
 	return 0;
 
 err_free_dotclock:
-	sun4i_dclk_free(tcon);
+	if (tcon->quirks->has_channel_0)
+		sun4i_dclk_free(tcon);
 err_free_clocks:
 	sun4i_tcon_free_clocks(tcon);
 err_assert_reset:
@@ -593,7 +602,9 @@ static void sun4i_tcon_unbind(struct device *dev, struct device *master,
 	struct sun4i_tcon *tcon = dev_get_drvdata(dev);
 
 	list_del(&tcon->list);
-	sun4i_dclk_free(tcon);
+
+	if (tcon->quirks->has_channel_0)
+		sun4i_dclk_free(tcon);
 	sun4i_tcon_free_clocks(tcon);
 }
 
@@ -625,23 +636,30 @@ static int sun4i_tcon_remove(struct platform_device *pdev)
 
 static const struct sun4i_tcon_quirks sun5i_a13_quirks = {
 	.has_unknown_mux = true,
+	.has_channel_0	= true,
 	.has_channel_1	= true,
 };
 
 static const struct sun4i_tcon_quirks sun6i_a31_quirks = {
+	.has_channel_0	= true,
 	.has_channel_1	= true,
 };
 
 static const struct sun4i_tcon_quirks sun6i_a31s_quirks = {
+	.has_channel_0	= true,
 	.has_channel_1	= true,
 };
 
 static const struct sun4i_tcon_quirks sun8i_a33_quirks = {
-	/* nothing is supported */
+	.has_channel_0	= true,
 };
 
 static const struct sun4i_tcon_quirks sun8i_v3s_quirks = {
-	/* nothing is supported */
+	.has_channel_0	= true,
+};
+
+static const struct sun4i_tcon_quirks sun8i_h3_quirks = {
+	.has_channel_1	= true,
 };
 
 static const struct of_device_id sun4i_tcon_of_table[] = {
@@ -649,6 +667,7 @@ static const struct of_device_id sun4i_tcon_of_table[] = {
 	{ .compatible = "allwinner,sun6i-a31-tcon", .data = &sun6i_a31_quirks },
 	{ .compatible = "allwinner,sun6i-a31s-tcon", .data = &sun6i_a31s_quirks },
 	{ .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks },
+	{ .compatible = "allwinner,sun8i-h3-tcon", .data = &sun8i_h3_quirks },
 	{ .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks },
 	{ }
 };
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
index 552c88ec16be..de035e598129 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
@@ -145,6 +145,7 @@
 
 struct sun4i_tcon_quirks {
 	bool	has_unknown_mux; /* sun5i has undocumented mux */
+	bool	has_channel_0;	/* some A83T+ TCONs don't have channel 0*/
 	bool	has_channel_1;	/* a33 does not have channel 1 */
 };
 
-- 
2.13.0

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#1703636 — Re: [linux-sunxi] [PATCH 03/13] drm: sun4i: add support for H3's TCON

FromChen-Yu Tsai <wens@csie.org>
Date2017-08-04 06:10 +0200
SubjectRe: [linux-sunxi] [PATCH 03/13] drm: sun4i: add support for H3's TCON
Message-ID<uaC5Y-1Xl-3@gated-at.bofh.it>
In reply to#1701021
On Tue, Aug 1, 2017 at 9:12 PM, Icenowy Zheng <icenowy@aosc.io> wrote:
> From: Icenowy Zheng <icenowy@aosc.xyz>
>
> Allwinner H3 has two special TCONs without channel 0.
>
> Add support for this kind of TCON.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

Ideally you would split this into two patches. The first one would add
the quirks support for TCONs without channel 0. I can also use this for
the A80. The second would add the H3 TCON.

ChenYu

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#1701022 — [PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support

FromIcenowy Zheng <icenowy@aosc.io>
Date2017-08-01 15:20 +0200
Subject[PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support
Message-ID<u9FfA-4tk-15@gated-at.bofh.it>
In reply to#1701018
Allwinner H3 features a "Display Engine 2.0".

Add device tree bindings for the following parts:
- H3 TCONs
- H3 Mixers
- H3 Display engine

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 .../bindings/display/sunxi/sun4i-drm.txt           | 25 ++++++++++++++++++----
 1 file changed, 21 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index 2ee6ff0ef98e..92512953943e 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -87,18 +87,17 @@ Required properties:
    * allwinner,sun6i-a31-tcon
    * allwinner,sun6i-a31s-tcon
    * allwinner,sun8i-a33-tcon
+   * allwinner,sun8i-h3-tcon
    * allwinner,sun8i-v3s-tcon
  - reg: base address and size of memory-mapped region
  - interrupts: interrupt associated to this IP
  - clocks: phandles to the clocks feeding the TCON. Three are needed:
    - 'ahb': the interface clocks
-   - 'tcon-ch0': The clock driving the TCON channel 0
  - resets: phandles to the reset controllers driving the encoder
    - "lcd": the reset line for the TCON channel 0
 
  - clock-names: the clock names mentioned above
  - reset-names: the reset names mentioned above
- - clock-output-names: Name of the pixel clock created
 
 - ports: A ports node with endpoint definitions as defined in
   Documentation/devicetree/bindings/media/video-interfaces.txt. The
@@ -112,7 +111,23 @@ Required properties:
   channel the endpoint is associated to. If that property is not
   present, the endpoint number will be used as the channel number.
 
-On SoCs other than the A33 and V3s, there is one more clock required:
+For the following compatibles:
+   * allwinner,sun5i-a13-tcon
+   * allwinner,sun6i-a31-tcon
+   * allwinner,sun6i-a31s-tcon
+   * allwinner,sun8i-a33-tcon
+   * allwinner,sun8i-v3s-tcon
+there is one more clock and one more property required:
+ - clocks:
+   - 'tcon-ch0': The clock driving the TCON channel 0
+ - clock-output-names: Name of the pixel clock created
+
+For the following compatibles:
+   * allwinner,sun5i-a13-tcon
+   * allwinner,sun6i-a31-tcon
+   * allwinner,sun6i-a31s-tcon
+   * allwinner,sun8i-h3-tcon
+there is one more clock required:
    - 'tcon-ch1': The clock driving the TCON channel 1
 
 DRC
@@ -207,6 +222,8 @@ supported.
 Required properties:
   - compatible: value must be one of:
     * allwinner,sun8i-v3s-de2-mixer
+    * allwinner,sun8i-h3-de2-mixer0
+    * allwinner,sun8i-h3-de2-mixer1
   - reg: base address and size of the memory-mapped region.
   - clocks: phandles to the clocks feeding the mixer
     * bus: the mixer interface clock
@@ -218,7 +235,6 @@ Required properties:
   Documentation/devicetree/bindings/media/video-interfaces.txt. The
   first port should be the input endpoints, the second one the output
 
-
 Display Engine Pipeline
 -----------------------
 
@@ -233,6 +249,7 @@ Required properties:
     * allwinner,sun6i-a31-display-engine
     * allwinner,sun6i-a31s-display-engine
     * allwinner,sun8i-a33-display-engine
+    * allwinner,sun8i-h3-display-engine
     * allwinner,sun8i-v3s-display-engine
 
   - allwinner,pipelines: list of phandle to the display engine
-- 
2.13.0

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#1701715 — Re: [linux-sunxi] [PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support

FromJernej Škrabec <jernej.skrabec@siol.net>
Date2017-08-02 07:00 +0200
SubjectRe: [linux-sunxi] [PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support
Message-ID<u9TVg-5fD-11@gated-at.bofh.it>
In reply to#1701022
Hi Icenowy,

Dne torek, 01. avgust 2017 ob 15:12:52 CEST je Icenowy Zheng napisal(a):
> Allwinner H3 features a "Display Engine 2.0".
> 
> Add device tree bindings for the following parts:
> - H3 TCONs
> - H3 Mixers
> - H3 Display engine
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
>  .../bindings/display/sunxi/sun4i-drm.txt           | 25
> ++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt index
> 2ee6ff0ef98e..92512953943e 100644
> --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> @@ -87,18 +87,17 @@ Required properties:
>     * allwinner,sun6i-a31-tcon
>     * allwinner,sun6i-a31s-tcon
>     * allwinner,sun8i-a33-tcon
> +   * allwinner,sun8i-h3-tcon
>     * allwinner,sun8i-v3s-tcon
>   - reg: base address and size of memory-mapped region
>   - interrupts: interrupt associated to this IP
>   - clocks: phandles to the clocks feeding the TCON. Three are needed:
>     - 'ahb': the interface clocks
> -   - 'tcon-ch0': The clock driving the TCON channel 0
>   - resets: phandles to the reset controllers driving the encoder
>     - "lcd": the reset line for the TCON channel 0
> 
>   - clock-names: the clock names mentioned above
>   - reset-names: the reset names mentioned above
> - - clock-output-names: Name of the pixel clock created
> 
>  - ports: A ports node with endpoint definitions as defined in
>    Documentation/devicetree/bindings/media/video-interfaces.txt. The
> @@ -112,7 +111,23 @@ Required properties:
>    channel the endpoint is associated to. If that property is not
>    present, the endpoint number will be used as the channel number.
> 
> -On SoCs other than the A33 and V3s, there is one more clock required:
> +For the following compatibles:
> +   * allwinner,sun5i-a13-tcon
> +   * allwinner,sun6i-a31-tcon
> +   * allwinner,sun6i-a31s-tcon
> +   * allwinner,sun8i-a33-tcon
> +   * allwinner,sun8i-v3s-tcon
> +there is one more clock and one more property required:
> + - clocks:
> +   - 'tcon-ch0': The clock driving the TCON channel 0
> + - clock-output-names: Name of the pixel clock created
> +
> +For the following compatibles:
> +   * allwinner,sun5i-a13-tcon
> +   * allwinner,sun6i-a31-tcon
> +   * allwinner,sun6i-a31s-tcon
> +   * allwinner,sun8i-h3-tcon
> +there is one more clock required:
>     - 'tcon-ch1': The clock driving the TCON channel 1
> 
>  DRC
> @@ -207,6 +222,8 @@ supported.
>  Required properties:
>    - compatible: value must be one of:
>      * allwinner,sun8i-v3s-de2-mixer
> +    * allwinner,sun8i-h3-de2-mixer0
> +    * allwinner,sun8i-h3-de2-mixer1

About that, I concur with Maxime here, plane number properties would be 
better. If we don't do this now, we will never have it.

Reference:
http://lists.infradead.org/pipermail/linux-arm-kernel/2017-June/512902.html

Regards,
Jernej

>    - reg: base address and size of the memory-mapped region.
>    - clocks: phandles to the clocks feeding the mixer
>      * bus: the mixer interface clock
> @@ -218,7 +235,6 @@ Required properties:
>    Documentation/devicetree/bindings/media/video-interfaces.txt. The
>    first port should be the input endpoints, the second one the output
> 
> -
>  Display Engine Pipeline
>  -----------------------
> 
> @@ -233,6 +249,7 @@ Required properties:
>      * allwinner,sun6i-a31-display-engine
>      * allwinner,sun6i-a31s-display-engine
>      * allwinner,sun8i-a33-display-engine
> +    * allwinner,sun8i-h3-display-engine
>      * allwinner,sun8i-v3s-display-engine
> 
>    - allwinner,pipelines: list of phandle to the display engine
> --
> 2.13.0
> 
> --
> You received this message because you are subscribed to the Google Groups
> "linux-sunxi" group. To unsubscribe from this group and stop receiving
> emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com.
> For more options, visit https://groups.google.com/d/optout.

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#1701721 — Re: [linux-sunxi] [PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support

Fromicenowy@aosc.io
Date2017-08-02 07:10 +0200
SubjectRe: [linux-sunxi] [PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support
Message-ID<u9U4W-5yI-13@gated-at.bofh.it>
In reply to#1701715
在 2017-08-02 12:53，Jernej Škrabec 写道：
> Hi Icenowy,
> 
> Dne torek, 01. avgust 2017 ob 15:12:52 CEST je Icenowy Zheng 
> napisal(a):
>> Allwinner H3 features a "Display Engine 2.0".
>> 
>> Add device tree bindings for the following parts:
>> - H3 TCONs
>> - H3 Mixers
>> - H3 Display engine
>> 
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>> ---
>>  .../bindings/display/sunxi/sun4i-drm.txt           | 25
>> ++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 
>> deletions(-)
>> 
>> diff --git 
>> a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
>> b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt index
>> 2ee6ff0ef98e..92512953943e 100644
>> --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
>> +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
>> @@ -87,18 +87,17 @@ Required properties:
>>     * allwinner,sun6i-a31-tcon
>>     * allwinner,sun6i-a31s-tcon
>>     * allwinner,sun8i-a33-tcon
>> +   * allwinner,sun8i-h3-tcon
>>     * allwinner,sun8i-v3s-tcon
>>   - reg: base address and size of memory-mapped region
>>   - interrupts: interrupt associated to this IP
>>   - clocks: phandles to the clocks feeding the TCON. Three are needed:
>>     - 'ahb': the interface clocks
>> -   - 'tcon-ch0': The clock driving the TCON channel 0
>>   - resets: phandles to the reset controllers driving the encoder
>>     - "lcd": the reset line for the TCON channel 0
>> 
>>   - clock-names: the clock names mentioned above
>>   - reset-names: the reset names mentioned above
>> - - clock-output-names: Name of the pixel clock created
>> 
>>  - ports: A ports node with endpoint definitions as defined in
>>    Documentation/devicetree/bindings/media/video-interfaces.txt. The
>> @@ -112,7 +111,23 @@ Required properties:
>>    channel the endpoint is associated to. If that property is not
>>    present, the endpoint number will be used as the channel number.
>> 
>> -On SoCs other than the A33 and V3s, there is one more clock required:
>> +For the following compatibles:
>> +   * allwinner,sun5i-a13-tcon
>> +   * allwinner,sun6i-a31-tcon
>> +   * allwinner,sun6i-a31s-tcon
>> +   * allwinner,sun8i-a33-tcon
>> +   * allwinner,sun8i-v3s-tcon
>> +there is one more clock and one more property required:
>> + - clocks:
>> +   - 'tcon-ch0': The clock driving the TCON channel 0
>> + - clock-output-names: Name of the pixel clock created
>> +
>> +For the following compatibles:
>> +   * allwinner,sun5i-a13-tcon
>> +   * allwinner,sun6i-a31-tcon
>> +   * allwinner,sun6i-a31s-tcon
>> +   * allwinner,sun8i-h3-tcon
>> +there is one more clock required:
>>     - 'tcon-ch1': The clock driving the TCON channel 1
>> 
>>  DRC
>> @@ -207,6 +222,8 @@ supported.
>>  Required properties:
>>    - compatible: value must be one of:
>>      * allwinner,sun8i-v3s-de2-mixer
>> +    * allwinner,sun8i-h3-de2-mixer0
>> +    * allwinner,sun8i-h3-de2-mixer1
> 
> About that, I concur with Maxime here, plane number properties would be
> better. If we don't do this now, we will never have it.

But I still prefer different compatibles, as the capabilities are 
already
proven to be different between mixer0 and mixer1, and furtherly we 
cannot
promise Allwinner won't add more functions only available at mixer0.

Then we will be trapped into a situation that we describe more and more
functions via properties, but they should be encoded into the 
compatible.

> 
> Reference:
> http://lists.infradead.org/pipermail/linux-arm-kernel/2017-June/512902.html
> 
> Regards,
> Jernej

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#1702384 — Re: [linux-sunxi] [PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support

FromJernej Škrabec <jernej.skrabec@siol.net>
Date2017-08-02 21:10 +0200
SubjectRe: [linux-sunxi] [PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support
Message-ID<ua7bP-5Aw-5@gated-at.bofh.it>
In reply to#1701721
Hi,

Dne sreda, 02. avgust 2017 ob 07:02:39 CEST je icenowy@aosc.io napisal(a):
> 在 2017-08-02 12:53，Jernej Škrabec 写道：
> 
> > Hi Icenowy,
> > 
> > Dne torek, 01. avgust 2017 ob 15:12:52 CEST je Icenowy Zheng
> > 
> > napisal(a):
> >> Allwinner H3 features a "Display Engine 2.0".
> >> 
> >> Add device tree bindings for the following parts:
> >> - H3 TCONs
> >> - H3 Mixers
> >> - H3 Display engine
> >> 
> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> >> ---
> >> 
> >>  .../bindings/display/sunxi/sun4i-drm.txt           | 25
> >> 
> >> ++++++++++++++++++---- 1 file changed, 21 insertions(+), 4
> >> deletions(-)
> >> 
> >> diff --git
> >> a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> >> b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt index
> >> 2ee6ff0ef98e..92512953943e 100644
> >> --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> >> +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> >> 
> >> @@ -87,18 +87,17 @@ Required properties:
> >>     * allwinner,sun6i-a31-tcon
> >>     * allwinner,sun6i-a31s-tcon
> >>     * allwinner,sun8i-a33-tcon
> >> 
> >> +   * allwinner,sun8i-h3-tcon
> >> 
> >>     * allwinner,sun8i-v3s-tcon
> >>   
> >>   - reg: base address and size of memory-mapped region
> >>   - interrupts: interrupt associated to this IP
> >>   
> >>   - clocks: phandles to the clocks feeding the TCON. Three are needed:
> >>     - 'ahb': the interface clocks
> >> 
> >> -   - 'tcon-ch0': The clock driving the TCON channel 0
> >> 
> >>   - resets: phandles to the reset controllers driving the encoder
> >>   
> >>     - "lcd": the reset line for the TCON channel 0
> >>   
> >>   - clock-names: the clock names mentioned above
> >>   - reset-names: the reset names mentioned above
> >> 
> >> - - clock-output-names: Name of the pixel clock created
> >> 
> >>  - ports: A ports node with endpoint definitions as defined in
> >>  
> >>    Documentation/devicetree/bindings/media/video-interfaces.txt. The
> >> 
> >> @@ -112,7 +111,23 @@ Required properties:
> >>    channel the endpoint is associated to. If that property is not
> >>    present, the endpoint number will be used as the channel number.
> >> 
> >> -On SoCs other than the A33 and V3s, there is one more clock required:
> >> +For the following compatibles:
> >> +   * allwinner,sun5i-a13-tcon
> >> +   * allwinner,sun6i-a31-tcon
> >> +   * allwinner,sun6i-a31s-tcon
> >> +   * allwinner,sun8i-a33-tcon
> >> +   * allwinner,sun8i-v3s-tcon
> >> +there is one more clock and one more property required:
> >> + - clocks:
> >> +   - 'tcon-ch0': The clock driving the TCON channel 0
> >> + - clock-output-names: Name of the pixel clock created
> >> +
> >> +For the following compatibles:
> >> +   * allwinner,sun5i-a13-tcon
> >> +   * allwinner,sun6i-a31-tcon
> >> +   * allwinner,sun6i-a31s-tcon
> >> +   * allwinner,sun8i-h3-tcon
> >> 
> >> +there is one more clock required:
> >>     - 'tcon-ch1': The clock driving the TCON channel 1
> >>  
> >>  DRC
> >> 
> >> @@ -207,6 +222,8 @@ supported.
> >> 
> >>  Required properties:
> >>    - compatible: value must be one of:
> >>      * allwinner,sun8i-v3s-de2-mixer
> >> 
> >> +    * allwinner,sun8i-h3-de2-mixer0
> >> +    * allwinner,sun8i-h3-de2-mixer1
> > 
> > About that, I concur with Maxime here, plane number properties would be
> > better. If we don't do this now, we will never have it.
> 
> But I still prefer different compatibles, as the capabilities are
> already
> proven to be different between mixer0 and mixer1, and furtherly we
> cannot
> promise Allwinner won't add more functions only available at mixer0.
> 
> Then we will be trapped into a situation that we describe more and more
> functions via properties, but they should be encoded into the
> compatible.

It is either multiple compatibles or multiple properties. I prefer the later, 
but it is up to maintainers to decide.

Anyway, I think DE2 will not evolve much since DE3 is almost ready (H6). At 
least basics seems to be similar according to a BSP code drop.

Regards,
Jernej

> 
> > Reference:
> > http://lists.infradead.org/pipermail/linux-arm-kernel/2017-June/512902.htm
> > l
> > 
> > Regards,
> > Jernej
> 
> --
> You received this message because you are subscribed to the Google Groups
> "linux-sunxi" group. To unsubscribe from this group and stop receiving
> emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com.
> For more options, visit https://groups.google.com/d/optout.

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#1702538 — Re: [linux-sunxi] [PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support

FromIcenowy Zheng <icenowy@aosc.io>
Date2017-08-03 01:00 +0200
SubjectRe: [linux-sunxi] [PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support
Message-ID<uaaMq-7QI-1@gated-at.bofh.it>
In reply to#1702384

于 2017年8月3日 GMT+08:00 上午3:06:26, "Jernej Škrabec" <jernej.skrabec@siol.net> 写到:
>Hi,
>
>Dne sreda, 02. avgust 2017 ob 07:02:39 CEST je icenowy@aosc.io
>napisal(a):
>> 在 2017-08-02 12:53，Jernej Škrabec 写道：
>> 
>> > Hi Icenowy,
>> > 
>> > Dne torek, 01. avgust 2017 ob 15:12:52 CEST je Icenowy Zheng
>> > 
>> > napisal(a):
>> >> Allwinner H3 features a "Display Engine 2.0".
>> >> 
>> >> Add device tree bindings for the following parts:
>> >> - H3 TCONs
>> >> - H3 Mixers
>> >> - H3 Display engine
>> >> 
>> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>> >> ---
>> >> 
>> >>  .../bindings/display/sunxi/sun4i-drm.txt           | 25
>> >> 
>> >> ++++++++++++++++++---- 1 file changed, 21 insertions(+), 4
>> >> deletions(-)
>> >> 
>> >> diff --git
>> >> a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
>> >> b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
>index
>> >> 2ee6ff0ef98e..92512953943e 100644
>> >> ---
>a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
>> >> +++
>b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
>> >> 
>> >> @@ -87,18 +87,17 @@ Required properties:
>> >>     * allwinner,sun6i-a31-tcon
>> >>     * allwinner,sun6i-a31s-tcon
>> >>     * allwinner,sun8i-a33-tcon
>> >> 
>> >> +   * allwinner,sun8i-h3-tcon
>> >> 
>> >>     * allwinner,sun8i-v3s-tcon
>> >>   
>> >>   - reg: base address and size of memory-mapped region
>> >>   - interrupts: interrupt associated to this IP
>> >>   
>> >>   - clocks: phandles to the clocks feeding the TCON. Three are
>needed:
>> >>     - 'ahb': the interface clocks
>> >> 
>> >> -   - 'tcon-ch0': The clock driving the TCON channel 0
>> >> 
>> >>   - resets: phandles to the reset controllers driving the encoder
>> >>   
>> >>     - "lcd": the reset line for the TCON channel 0
>> >>   
>> >>   - clock-names: the clock names mentioned above
>> >>   - reset-names: the reset names mentioned above
>> >> 
>> >> - - clock-output-names: Name of the pixel clock created
>> >> 
>> >>  - ports: A ports node with endpoint definitions as defined in
>> >>  
>> >>    Documentation/devicetree/bindings/media/video-interfaces.txt.
>The
>> >> 
>> >> @@ -112,7 +111,23 @@ Required properties:
>> >>    channel the endpoint is associated to. If that property is not
>> >>    present, the endpoint number will be used as the channel
>number.
>> >> 
>> >> -On SoCs other than the A33 and V3s, there is one more clock
>required:
>> >> +For the following compatibles:
>> >> +   * allwinner,sun5i-a13-tcon
>> >> +   * allwinner,sun6i-a31-tcon
>> >> +   * allwinner,sun6i-a31s-tcon
>> >> +   * allwinner,sun8i-a33-tcon
>> >> +   * allwinner,sun8i-v3s-tcon
>> >> +there is one more clock and one more property required:
>> >> + - clocks:
>> >> +   - 'tcon-ch0': The clock driving the TCON channel 0
>> >> + - clock-output-names: Name of the pixel clock created
>> >> +
>> >> +For the following compatibles:
>> >> +   * allwinner,sun5i-a13-tcon
>> >> +   * allwinner,sun6i-a31-tcon
>> >> +   * allwinner,sun6i-a31s-tcon
>> >> +   * allwinner,sun8i-h3-tcon
>> >> 
>> >> +there is one more clock required:
>> >>     - 'tcon-ch1': The clock driving the TCON channel 1
>> >>  
>> >>  DRC
>> >> 
>> >> @@ -207,6 +222,8 @@ supported.
>> >> 
>> >>  Required properties:
>> >>    - compatible: value must be one of:
>> >>      * allwinner,sun8i-v3s-de2-mixer
>> >> 
>> >> +    * allwinner,sun8i-h3-de2-mixer0
>> >> +    * allwinner,sun8i-h3-de2-mixer1
>> > 
>> > About that, I concur with Maxime here, plane number properties
>would be
>> > better. If we don't do this now, we will never have it.
>> 
>> But I still prefer different compatibles, as the capabilities are
>> already
>> proven to be different between mixer0 and mixer1, and furtherly we
>> cannot
>> promise Allwinner won't add more functions only available at mixer0.
>> 
>> Then we will be trapped into a situation that we describe more and
>more
>> functions via properties, but they should be encoded into the
>> compatible.
>
>It is either multiple compatibles or multiple properties. I prefer the
>later, 
>but it is up to maintainers to decide.
>
>Anyway, I think DE2 will not evolve much since DE3 is almost ready
>(H6). At 
>least basics seems to be similar according to a BSP code drop.

According to what I heard from TL Lim, DE3 is just an evolution
to DE2.

>
>Regards,
>Jernej
>
>> 
>> > Reference:
>> >
>http://lists.infradead.org/pipermail/linux-arm-kernel/2017-June/512902.htm
>> > l
>> > 
>> > Regards,
>> > Jernej
>> 
>> --
>> You received this message because you are subscribed to the Google
>Groups
>> "linux-sunxi" group. To unsubscribe from this group and stop
>receiving
>> emails from it, send an email to
>linux-sunxi+unsubscribe@googlegroups.com.
>> For more options, visit https://groups.google.com/d/optout.

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#1708099 — Re: [linux-sunxi] [PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support

FromRob Herring <robh@kernel.org>
Date2017-08-10 02:30 +0200
SubjectRe: [linux-sunxi] [PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support
Message-ID<ucJwl-6s8-11@gated-at.bofh.it>
In reply to#1702384
On Wed, Aug 02, 2017 at 09:06:26PM +0200, Jernej Škrabec wrote:
> Hi,
> 
> Dne sreda, 02. avgust 2017 ob 07:02:39 CEST je icenowy@aosc.io napisal(a):
> > 在 2017-08-02 12:53，Jernej Škrabec 写道：
> > 
> > > Hi Icenowy,
> > > 
> > > Dne torek, 01. avgust 2017 ob 15:12:52 CEST je Icenowy Zheng
> > > 
> > > napisal(a):
> > >> Allwinner H3 features a "Display Engine 2.0".
> > >> 
> > >> Add device tree bindings for the following parts:
> > >> - H3 TCONs
> > >> - H3 Mixers
> > >> - H3 Display engine
> > >> 
> > >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> > >> ---
> > >> 
> > >>  .../bindings/display/sunxi/sun4i-drm.txt           | 25
> > >> 
> > >> ++++++++++++++++++---- 1 file changed, 21 insertions(+), 4
> > >> deletions(-)
> > >> 
> > >> diff --git
> > >> a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> > >> b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt index
> > >> 2ee6ff0ef98e..92512953943e 100644
> > >> --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> > >> +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> > >> 
> > >> @@ -87,18 +87,17 @@ Required properties:
> > >>     * allwinner,sun6i-a31-tcon
> > >>     * allwinner,sun6i-a31s-tcon
> > >>     * allwinner,sun8i-a33-tcon
> > >> 
> > >> +   * allwinner,sun8i-h3-tcon
> > >> 
> > >>     * allwinner,sun8i-v3s-tcon
> > >>   
> > >>   - reg: base address and size of memory-mapped region
> > >>   - interrupts: interrupt associated to this IP
> > >>   
> > >>   - clocks: phandles to the clocks feeding the TCON. Three are needed:
> > >>     - 'ahb': the interface clocks
> > >> 
> > >> -   - 'tcon-ch0': The clock driving the TCON channel 0
> > >> 
> > >>   - resets: phandles to the reset controllers driving the encoder
> > >>   
> > >>     - "lcd": the reset line for the TCON channel 0
> > >>   
> > >>   - clock-names: the clock names mentioned above
> > >>   - reset-names: the reset names mentioned above
> > >> 
> > >> - - clock-output-names: Name of the pixel clock created
> > >> 
> > >>  - ports: A ports node with endpoint definitions as defined in
> > >>  
> > >>    Documentation/devicetree/bindings/media/video-interfaces.txt. The
> > >> 
> > >> @@ -112,7 +111,23 @@ Required properties:
> > >>    channel the endpoint is associated to. If that property is not
> > >>    present, the endpoint number will be used as the channel number.
> > >> 
> > >> -On SoCs other than the A33 and V3s, there is one more clock required:
> > >> +For the following compatibles:
> > >> +   * allwinner,sun5i-a13-tcon
> > >> +   * allwinner,sun6i-a31-tcon
> > >> +   * allwinner,sun6i-a31s-tcon
> > >> +   * allwinner,sun8i-a33-tcon
> > >> +   * allwinner,sun8i-v3s-tcon
> > >> +there is one more clock and one more property required:
> > >> + - clocks:
> > >> +   - 'tcon-ch0': The clock driving the TCON channel 0
> > >> + - clock-output-names: Name of the pixel clock created
> > >> +
> > >> +For the following compatibles:
> > >> +   * allwinner,sun5i-a13-tcon
> > >> +   * allwinner,sun6i-a31-tcon
> > >> +   * allwinner,sun6i-a31s-tcon
> > >> +   * allwinner,sun8i-h3-tcon
> > >> 
> > >> +there is one more clock required:
> > >>     - 'tcon-ch1': The clock driving the TCON channel 1
> > >>  
> > >>  DRC
> > >> 
> > >> @@ -207,6 +222,8 @@ supported.
> > >> 
> > >>  Required properties:
> > >>    - compatible: value must be one of:
> > >>      * allwinner,sun8i-v3s-de2-mixer
> > >> 
> > >> +    * allwinner,sun8i-h3-de2-mixer0
> > >> +    * allwinner,sun8i-h3-de2-mixer1
> > > 
> > > About that, I concur with Maxime here, plane number properties would be
> > > better. If we don't do this now, we will never have it.
> > 
> > But I still prefer different compatibles, as the capabilities are
> > already
> > proven to be different between mixer0 and mixer1, and furtherly we
> > cannot
> > promise Allwinner won't add more functions only available at mixer0.
> > 
> > Then we will be trapped into a situation that we describe more and more
> > functions via properties, but they should be encoded into the
> > compatible.
> 
> It is either multiple compatibles or multiple properties. I prefer the later, 
> but it is up to maintainers to decide.

It's not the same. A compatible can imply an infinite number of 
properties. I'm fine with properties too, but with only 2 instances I 
don't think it makes much sense.

Rob

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#1708091 — Re: [PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support

FromRob Herring <robh@kernel.org>
Date2017-08-10 02:20 +0200
SubjectRe: [PATCH 01/13] dt-bindings: update the binding for Allwinner H3 DE2 support
Message-ID<ucJmG-6oY-3@gated-at.bofh.it>
In reply to#1701022
On Tue, Aug 01, 2017 at 09:12:52PM +0800, Icenowy Zheng wrote:
> Allwinner H3 features a "Display Engine 2.0".
> 
> Add device tree bindings for the following parts:
> - H3 TCONs
> - H3 Mixers
> - H3 Display engine
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
>  .../bindings/display/sunxi/sun4i-drm.txt           | 25 ++++++++++++++++++----
>  1 file changed, 21 insertions(+), 4 deletions(-)

Acked-by: Rob Herring <robh@kernel.org>

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#1701043 — [PATCH 04/13] drm: sun4i: add compatible for H3 display engine

FromIcenowy Zheng <icenowy@aosc.io>
Date2017-08-01 15:40 +0200
Subject[PATCH 04/13] drm: sun4i: add compatible for H3 display engine
Message-ID<u9FyW-4zN-3@gated-at.bofh.it>
In reply to#1701018
Add a compatible string for H3 display engine in sun4i_drv code.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c
index fd99fe8a4df7..02c80bb7b385 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -314,6 +314,7 @@ static const struct of_device_id sun4i_drv_of_table[] = {
 	{ .compatible = "allwinner,sun6i-a31-display-engine" },
 	{ .compatible = "allwinner,sun6i-a31s-display-engine" },
 	{ .compatible = "allwinner,sun8i-a33-display-engine" },
+	{ .compatible = "allwinner,sun8i-h3-display-engine" },
 	{ .compatible = "allwinner,sun8i-v3s-display-engine" },
 	{ }
 };
-- 
2.13.0

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#1701045 — [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock

FromIcenowy Zheng <icenowy@aosc.io>
Date2017-08-01 15:40 +0200
Subject[PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock
Message-ID<u9FyW-4zN-13@gated-at.bofh.it>
In reply to#1701018
From: Jernej Skrabec <jernej.skrabec@siol.net>

When setting the HDMI clock of H3, the PLL_VIDEO clock needs to be set.

Add CLK_SET_RATE_PARENT flag for H3 HDMI clock.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index b1127e8629d9..2ebb3d865b01 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -474,7 +474,7 @@ static SUNXI_CCU_GATE(avs_clk,		"avs",		"osc24M",
 
 static const char * const hdmi_parents[] = { "pll-video" };
 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
-				 0x150, 0, 4, 24, 2, BIT(31), 0);
+				 0x150, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
 
 static SUNXI_CCU_GATE(hdmi_ddc_clk,	"hdmi-ddc",	"osc24M",
 		      0x154, BIT(31), 0);
-- 
2.13.0

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#1703644 — Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock

FromChen-Yu Tsai <wens@csie.org>
Date2017-08-04 06:20 +0200
SubjectRe: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock
Message-ID<uaCfD-218-7@gated-at.bofh.it>
In reply to#1701045
Hi,

On Tue, Aug 1, 2017 at 9:13 PM, Icenowy Zheng <icenowy@aosc.io> wrote:
> From: Jernej Skrabec <jernej.skrabec@siol.net>
>
> When setting the HDMI clock of H3, the PLL_VIDEO clock needs to be set.
>
> Add CLK_SET_RATE_PARENT flag for H3 HDMI clock.
>
> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
>  drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
> index b1127e8629d9..2ebb3d865b01 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
> @@ -474,7 +474,7 @@ static SUNXI_CCU_GATE(avs_clk,              "avs",          "osc24M",
>
>  static const char * const hdmi_parents[] = { "pll-video" };
>  static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
> -                                0x150, 0, 4, 24, 2, BIT(31), 0);
> +                                0x150, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);

Line is longer than 80 characters.

This looks independent enough so I've merged this for 4.14 with the
offending line wrapped and the following tag added:

Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")

ChenYu

>
>  static SUNXI_CCU_GATE(hdmi_ddc_clk,    "hdmi-ddc",     "osc24M",
>                       0x154, BIT(31), 0);
> --
> 2.13.0
>
> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com.
> For more options, visit https://groups.google.com/d/optout.

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#1703645 — Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock

FromIcenowy Zheng <icenowy@aosc.io>
Date2017-08-04 06:20 +0200
SubjectRe: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock
Message-ID<uaCfE-218-9@gated-at.bofh.it>
In reply to#1703644

于 2017年8月4日 GMT+08:00 下午12:15:27, Chen-Yu Tsai <wens@csie.org> 写到:
>Hi,
>
>On Tue, Aug 1, 2017 at 9:13 PM, Icenowy Zheng <icenowy@aosc.io> wrote:
>> From: Jernej Skrabec <jernej.skrabec@siol.net>
>>
>> When setting the HDMI clock of H3, the PLL_VIDEO clock needs to be
>set.
>>
>> Add CLK_SET_RATE_PARENT flag for H3 HDMI clock.
>>
>> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>> ---
>>  drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>> index b1127e8629d9..2ebb3d865b01 100644
>> --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>> @@ -474,7 +474,7 @@ static SUNXI_CCU_GATE(avs_clk,             
>"avs",          "osc24M",
>>
>>  static const char * const hdmi_parents[] = { "pll-video" };
>>  static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
>> -                                0x150, 0, 4, 24, 2, BIT(31), 0);
>> +                                0x150, 0, 4, 24, 2, BIT(31),
>CLK_SET_RATE_PARENT);
>
>Line is longer than 80 characters.
>
>This looks independent enough so I've merged this for 4.14 with the
>offending line wrapped and the following tag added:
>
>Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")

Please don't merge this now until Jernej send it.

>
>ChenYu
>
>>
>>  static SUNXI_CCU_GATE(hdmi_ddc_clk,    "hdmi-ddc",     "osc24M",
>>                       0x154, BIT(31), 0);
>> --
>> 2.13.0
>>
>> --
>> You received this message because you are subscribed to the Google
>Groups "linux-sunxi" group.
>> To unsubscribe from this group and stop receiving emails from it,
>send an email to linux-sunxi+unsubscribe@googlegroups.com.
>> For more options, visit https://groups.google.com/d/optout.

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#1703650 — Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock

FromChen-Yu Tsai <wens@csie.org>
Date2017-08-04 06:40 +0200
SubjectRe: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock
Message-ID<uaCz0-2b0-5@gated-at.bofh.it>
In reply to#1703645
On Fri, Aug 4, 2017 at 12:16 PM, Icenowy Zheng <icenowy@aosc.io> wrote:
>
>
> 于 2017年8月4日 GMT+08:00 下午12:15:27, Chen-Yu Tsai <wens@csie.org> 写到:
>>Hi,
>>
>>On Tue, Aug 1, 2017 at 9:13 PM, Icenowy Zheng <icenowy@aosc.io> wrote:
>>> From: Jernej Skrabec <jernej.skrabec@siol.net>
>>>
>>> When setting the HDMI clock of H3, the PLL_VIDEO clock needs to be
>>set.
>>>
>>> Add CLK_SET_RATE_PARENT flag for H3 HDMI clock.
>>>
>>> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
>>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>>> ---
>>>  drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>>b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>>> index b1127e8629d9..2ebb3d865b01 100644
>>> --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>>> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>>> @@ -474,7 +474,7 @@ static SUNXI_CCU_GATE(avs_clk,
>>"avs",          "osc24M",
>>>
>>>  static const char * const hdmi_parents[] = { "pll-video" };
>>>  static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
>>> -                                0x150, 0, 4, 24, 2, BIT(31), 0);
>>> +                                0x150, 0, 4, 24, 2, BIT(31),
>>CLK_SET_RATE_PARENT);
>>
>>Line is longer than 80 characters.
>>
>>This looks independent enough so I've merged this for 4.14 with the
>>offending line wrapped and the following tag added:
>>
>>Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
>
> Please don't merge this now until Jernej send it.

(Dropped Rob, devicetree and dri mailing lists)

Hi Jernej,

Is it OK if we take this patch for the next release? Or rather,
if there anything blocking this patch?

Thanks
ChenYu

>
>>
>>ChenYu
>>
>>>
>>>  static SUNXI_CCU_GATE(hdmi_ddc_clk,    "hdmi-ddc",     "osc24M",
>>>                       0x154, BIT(31), 0);
>>> --
>>> 2.13.0
>>>
>>> --
>>> You received this message because you are subscribed to the Google
>>Groups "linux-sunxi" group.
>>> To unsubscribe from this group and stop receiving emails from it,
>>send an email to linux-sunxi+unsubscribe@googlegroups.com.
>>> For more options, visit https://groups.google.com/d/optout.
>
> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com.
> For more options, visit https://groups.google.com/d/optout.

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#1703798 — Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock

FromJernej Škrabec <jernej.skrabec@siol.net>
Date2017-08-04 11:00 +0200
SubjectRe: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock
Message-ID<uaGCB-4L1-5@gated-at.bofh.it>
In reply to#1703650
Hi Chen-Yu,

Dne petek, 04. avgust 2017 ob 06:29:50 CEST je Chen-Yu Tsai napisal(a):
> On Fri, Aug 4, 2017 at 12:16 PM, Icenowy Zheng <icenowy@aosc.io> wrote:
> > 于 2017年8月4日 GMT+08:00 下午12:15:27, Chen-Yu Tsai <wens@csie.org> 写到:
> >>Hi,
> >>
> >>On Tue, Aug 1, 2017 at 9:13 PM, Icenowy Zheng <icenowy@aosc.io> wrote:
> >>> From: Jernej Skrabec <jernej.skrabec@siol.net>
> >>> 
> >>> When setting the HDMI clock of H3, the PLL_VIDEO clock needs to be
> >>
> >>set.
> >>
> >>> Add CLK_SET_RATE_PARENT flag for H3 HDMI clock.
> >>> 
> >>> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> >>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> >>> ---
> >>> 
> >>>  drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
> >>>  1 file changed, 1 insertion(+), 1 deletion(-)
> >>> 
> >>> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
> >>
> >>b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
> >>
> >>> index b1127e8629d9..2ebb3d865b01 100644
> >>> --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
> >>> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
> >>> @@ -474,7 +474,7 @@ static SUNXI_CCU_GATE(avs_clk,
> >>
> >>"avs",          "osc24M",
> >>
> >>>  static const char * const hdmi_parents[] = { "pll-video" };
> >>>  static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
> >>> 
> >>> -                                0x150, 0, 4, 24, 2, BIT(31), 0);
> >>> +                                0x150, 0, 4, 24, 2, BIT(31),
> >>
> >>CLK_SET_RATE_PARENT);
> >>
> >>Line is longer than 80 characters.
> >>
> >>This looks independent enough so I've merged this for 4.14 with the
> >>offending line wrapped and the following tag added:
> >>
> >>Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
> >>
> > Please don't merge this now until Jernej send it.
> 
> (Dropped Rob, devicetree and dri mailing lists)
> 
> Hi Jernej,
> 
> Is it OK if we take this patch for the next release? Or rather,
> if there anything blocking this patch?

I just made last check now and this patch is indeed OK. Before merging, please 
read explanation below.

Background:
According to H3 datasheet and BSP driver, HDMI clock has M factor (divider) to 
correctly set pixel clock to desired value. However, Jens Kuske discovered 
that this factor doesn't play any role whatsoever and instead, division factor 
set in PHY registers is the important one. I confirmed that on BSP kernel by 
tying M factor to 0. Both, HDMI video and audio, still worked correctly.

So that flag is necessary to set pll-video to pixel clock * div factor. I can 
also change HDMI clock type to SUNXI_CCU_GATE (without M factor) and document 
discrepancy with datasheet in ccu-sun8i-h3.c. Alternatively to this patch, 
just in case, to be on the safe side, I can add pll-video clock phandle to the 
dt node. However, as far as I know, that might prevent selecting another 
parent on SoCs where HDMI clock has multiple parents.

Regards,
Jernej

> 
> Thanks
> ChenYu
> 
> >>ChenYu
> >>
> >>>  static SUNXI_CCU_GATE(hdmi_ddc_clk,    "hdmi-ddc",     "osc24M",
> >>>  
> >>>                       0x154, BIT(31), 0);
> >>> 
> >>> --
> >>> 2.13.0
> >>> 
> >>> --
> >>> You received this message because you are subscribed to the Google
> >>
> >>Groups "linux-sunxi" group.
> >>
> >>> To unsubscribe from this group and stop receiving emails from it,
> >>
> >>send an email to linux-sunxi+unsubscribe@googlegroups.com.
> >>
> >>> For more options, visit https://groups.google.com/d/optout.
> > 
> > --
> > You received this message because you are subscribed to the Google Groups
> > "linux-sunxi" group. To unsubscribe from this group and stop receiving
> > emails from it, send an email to
> > linux-sunxi+unsubscribe@googlegroups.com. For more options, visit
> > https://groups.google.com/d/optout.
> 
> --
> You received this message because you are subscribed to the Google Groups
> "linux-sunxi" group. To unsubscribe from this group and stop receiving
> emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com.
> For more options, visit https://groups.google.com/d/optout.

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#1703810 — Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock

FromIcenowy Zheng <icenowy@aosc.io>
Date2017-08-04 11:10 +0200
SubjectRe: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock
Message-ID<uaGMi-53u-21@gated-at.bofh.it>
In reply to#1703798

于 2017年8月4日 GMT+08:00 下午4:59:03, "Jernej Škrabec" <jernej.skrabec@siol.net> 写到:
>Hi Chen-Yu,
>
>Dne petek, 04. avgust 2017 ob 06:29:50 CEST je Chen-Yu Tsai napisal(a):
>> On Fri, Aug 4, 2017 at 12:16 PM, Icenowy Zheng <icenowy@aosc.io>
>wrote:
>> > 于 2017年8月4日 GMT+08:00 下午12:15:27, Chen-Yu Tsai <wens@csie.org> 写到:
>> >>Hi,
>> >>
>> >>On Tue, Aug 1, 2017 at 9:13 PM, Icenowy Zheng <icenowy@aosc.io>
>wrote:
>> >>> From: Jernej Skrabec <jernej.skrabec@siol.net>
>> >>> 
>> >>> When setting the HDMI clock of H3, the PLL_VIDEO clock needs to
>be
>> >>
>> >>set.
>> >>
>> >>> Add CLK_SET_RATE_PARENT flag for H3 HDMI clock.
>> >>> 
>> >>> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
>> >>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>> >>> ---
>> >>> 
>> >>>  drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
>> >>>  1 file changed, 1 insertion(+), 1 deletion(-)
>> >>> 
>> >>> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>> >>
>> >>b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>> >>
>> >>> index b1127e8629d9..2ebb3d865b01 100644
>> >>> --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>> >>> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>> >>> @@ -474,7 +474,7 @@ static SUNXI_CCU_GATE(avs_clk,
>> >>
>> >>"avs",          "osc24M",
>> >>
>> >>>  static const char * const hdmi_parents[] = { "pll-video" };
>> >>>  static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
>> >>> 
>> >>> -                                0x150, 0, 4, 24, 2, BIT(31), 0);
>> >>> +                                0x150, 0, 4, 24, 2, BIT(31),
>> >>
>> >>CLK_SET_RATE_PARENT);
>> >>
>> >>Line is longer than 80 characters.
>> >>
>> >>This looks independent enough so I've merged this for 4.14 with the
>> >>offending line wrapped and the following tag added:
>> >>
>> >>Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
>> >>
>> > Please don't merge this now until Jernej send it.
>> 
>> (Dropped Rob, devicetree and dri mailing lists)
>> 
>> Hi Jernej,
>> 
>> Is it OK if we take this patch for the next release? Or rather,
>> if there anything blocking this patch?
>
>I just made last check now and this patch is indeed OK. Before merging,
>please 
>read explanation below.
>
>Background:
>According to H3 datasheet and BSP driver, HDMI clock has M factor
>(divider) to 
>correctly set pixel clock to desired value. However, Jens Kuske
>discovered 
>that this factor doesn't play any role whatsoever and instead, division
>factor 
>set in PHY registers is the important one. I confirmed that on BSP
>kernel by 
>tying M factor to 0. Both, HDMI video and audio, still worked
>correctly.
>
>So that flag is necessary to set pll-video to pixel clock * div factor.
>I can 
>also change HDMI clock type to SUNXI_CCU_GATE (without M factor) and
>document 
>discrepancy with datasheet in ccu-sun8i-h3.c. Alternatively to this
>patch, 
>just in case, to be on the safe side, I can add pll-video clock phandle
>to the 
>dt node. However, as far as I know, that might prevent selecting
>another 
>parent on SoCs where HDMI clock has multiple parents.

Unfortunately A64 is this situation -- A64 TCON1/HDMI clocks can
use pll-video0/1 as parent, but TCON0 can only use pll-video0 or
pll-mipi (also a downstream clock of pll-video0), and by default
TCON1/HDMI also uses pll-video0.

Because of this I have never succeeded in multihead (LCD+HDMI)
on Pinebook.

>
>Regards,
>Jernej
>
>> 
>> Thanks
>> ChenYu
>> 
>> >>ChenYu
>> >>
>> >>>  static SUNXI_CCU_GATE(hdmi_ddc_clk,    "hdmi-ddc",     "osc24M",
>> >>>  
>> >>>                       0x154, BIT(31), 0);
>> >>> 
>> >>> --
>> >>> 2.13.0
>> >>> 
>> >>> --
>> >>> You received this message because you are subscribed to the
>Google
>> >>
>> >>Groups "linux-sunxi" group.
>> >>
>> >>> To unsubscribe from this group and stop receiving emails from it,
>> >>
>> >>send an email to linux-sunxi+unsubscribe@googlegroups.com.
>> >>
>> >>> For more options, visit https://groups.google.com/d/optout.
>> > 
>> > --
>> > You received this message because you are subscribed to the Google
>Groups
>> > "linux-sunxi" group. To unsubscribe from this group and stop
>receiving
>> > emails from it, send an email to
>> > linux-sunxi+unsubscribe@googlegroups.com. For more options, visit
>> > https://groups.google.com/d/optout.
>> 
>> --
>> You received this message because you are subscribed to the Google
>Groups
>> "linux-sunxi" group. To unsubscribe from this group and stop
>receiving
>> emails from it, send an email to
>linux-sunxi+unsubscribe@googlegroups.com.
>> For more options, visit https://groups.google.com/d/optout.

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#1703829 — Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock

FromChen-Yu Tsai <wens@csie.org>
Date2017-08-04 11:40 +0200
SubjectRe: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock
Message-ID<uaHfk-5fr-23@gated-at.bofh.it>
In reply to#1703810
On Fri, Aug 4, 2017 at 5:03 PM, Icenowy Zheng <icenowy@aosc.io> wrote:
>
>
> 于 2017年8月4日 GMT+08:00 下午4:59:03, "Jernej Škrabec" <jernej.skrabec@siol.net> 写到:
>>Hi Chen-Yu,
>>
>>Dne petek, 04. avgust 2017 ob 06:29:50 CEST je Chen-Yu Tsai napisal(a):
>>> On Fri, Aug 4, 2017 at 12:16 PM, Icenowy Zheng <icenowy@aosc.io>
>>wrote:
>>> > 于 2017年8月4日 GMT+08:00 下午12:15:27, Chen-Yu Tsai <wens@csie.org> 写到:
>>> >>Hi,
>>> >>
>>> >>On Tue, Aug 1, 2017 at 9:13 PM, Icenowy Zheng <icenowy@aosc.io>
>>wrote:
>>> >>> From: Jernej Skrabec <jernej.skrabec@siol.net>
>>> >>>
>>> >>> When setting the HDMI clock of H3, the PLL_VIDEO clock needs to
>>be
>>> >>
>>> >>set.
>>> >>
>>> >>> Add CLK_SET_RATE_PARENT flag for H3 HDMI clock.
>>> >>>
>>> >>> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
>>> >>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>>> >>> ---
>>> >>>
>>> >>>  drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
>>> >>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>> >>>
>>> >>> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>>> >>
>>> >>b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>>> >>
>>> >>> index b1127e8629d9..2ebb3d865b01 100644
>>> >>> --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>>> >>> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>>> >>> @@ -474,7 +474,7 @@ static SUNXI_CCU_GATE(avs_clk,
>>> >>
>>> >>"avs",          "osc24M",
>>> >>
>>> >>>  static const char * const hdmi_parents[] = { "pll-video" };
>>> >>>  static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
>>> >>>
>>> >>> -                                0x150, 0, 4, 24, 2, BIT(31), 0);
>>> >>> +                                0x150, 0, 4, 24, 2, BIT(31),
>>> >>
>>> >>CLK_SET_RATE_PARENT);
>>> >>
>>> >>Line is longer than 80 characters.
>>> >>
>>> >>This looks independent enough so I've merged this for 4.14 with the
>>> >>offending line wrapped and the following tag added:
>>> >>
>>> >>Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
>>> >>
>>> > Please don't merge this now until Jernej send it.
>>>
>>> (Dropped Rob, devicetree and dri mailing lists)
>>>
>>> Hi Jernej,
>>>
>>> Is it OK if we take this patch for the next release? Or rather,
>>> if there anything blocking this patch?
>>
>>I just made last check now and this patch is indeed OK. Before merging,
>>please
>>read explanation below.
>>
>>Background:
>>According to H3 datasheet and BSP driver, HDMI clock has M factor
>>(divider) to
>>correctly set pixel clock to desired value. However, Jens Kuske
>>discovered
>>that this factor doesn't play any role whatsoever and instead, division
>>factor
>>set in PHY registers is the important one. I confirmed that on BSP
>>kernel by
>>tying M factor to 0. Both, HDMI video and audio, still worked
>>correctly.
>>
>>So that flag is necessary to set pll-video to pixel clock * div factor.
>>I can
>>also change HDMI clock type to SUNXI_CCU_GATE (without M factor) and
>>document
>>discrepancy with datasheet in ccu-sun8i-h3.c. Alternatively to this
>>patch,
>>just in case, to be on the safe side, I can add pll-video clock phandle
>>to the
>>dt node. However, as far as I know, that might prevent selecting
>>another
>>parent on SoCs where HDMI clock has multiple parents.
>
> Unfortunately A64 is this situation -- A64 TCON1/HDMI clocks can
> use pll-video0/1 as parent, but TCON0 can only use pll-video0 or
> pll-mipi (also a downstream clock of pll-video0), and by default
> TCON1/HDMI also uses pll-video0.
>
> Because of this I have never succeeded in multihead (LCD+HDMI)
> on Pinebook.

Multihead support hasn't been tested, despite all the patches I've
done to try and support it. I had to do some more to get HDMI and
LCD working together on the A31. And even then there are still
issues.

The current (as of Maxime's sunxi-drm/for-next branch) issues are

  - Two outputs with incompatible dot clocks will step on each
    other, instead of switching to another PLL. Maxime seems to
    have some patches to prevent this.

  - Engine and TCON pairing in a fully connected display system
    is (still) broken. You will end up tying both TCON with the
    same engine. I have patches to fix this in my a31-hdmi-v2
    branch.

You can work around both issues, the first one by adding
CLK_SET_RATE_NO_REPARENT to the TCON clocks, and forcing the
TCON parents at ccu probe time. The second one can be worked
around by removing the extra unused connections between mixer0
and TCON1, and vice versa.

This should at least allow you to test your hardware.

Regards
ChenYu

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#1703820 — Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock

FromChen-Yu Tsai <wens@csie.org>
Date2017-08-04 11:30 +0200
SubjectRe: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock
Message-ID<uaH5D-5ax-15@gated-at.bofh.it>
In reply to#1703798
On Fri, Aug 4, 2017 at 4:59 PM, Jernej Škrabec <jernej.skrabec@siol.net> wrote:
> Hi Chen-Yu,
>
> Dne petek, 04. avgust 2017 ob 06:29:50 CEST je Chen-Yu Tsai napisal(a):
>> On Fri, Aug 4, 2017 at 12:16 PM, Icenowy Zheng <icenowy@aosc.io> wrote:
>> > 于 2017年8月4日 GMT+08:00 下午12:15:27, Chen-Yu Tsai <wens@csie.org> 写到:
>> >>Hi,
>> >>
>> >>On Tue, Aug 1, 2017 at 9:13 PM, Icenowy Zheng <icenowy@aosc.io> wrote:
>> >>> From: Jernej Skrabec <jernej.skrabec@siol.net>
>> >>>
>> >>> When setting the HDMI clock of H3, the PLL_VIDEO clock needs to be
>> >>
>> >>set.
>> >>
>> >>> Add CLK_SET_RATE_PARENT flag for H3 HDMI clock.
>> >>>
>> >>> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
>> >>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>> >>> ---
>> >>>
>> >>>  drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
>> >>>  1 file changed, 1 insertion(+), 1 deletion(-)
>> >>>
>> >>> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>> >>
>> >>b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>> >>
>> >>> index b1127e8629d9..2ebb3d865b01 100644
>> >>> --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>> >>> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
>> >>> @@ -474,7 +474,7 @@ static SUNXI_CCU_GATE(avs_clk,
>> >>
>> >>"avs",          "osc24M",
>> >>
>> >>>  static const char * const hdmi_parents[] = { "pll-video" };
>> >>>  static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
>> >>>
>> >>> -                                0x150, 0, 4, 24, 2, BIT(31), 0);
>> >>> +                                0x150, 0, 4, 24, 2, BIT(31),
>> >>
>> >>CLK_SET_RATE_PARENT);
>> >>
>> >>Line is longer than 80 characters.
>> >>
>> >>This looks independent enough so I've merged this for 4.14 with the
>> >>offending line wrapped and the following tag added:
>> >>
>> >>Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
>> >>
>> > Please don't merge this now until Jernej send it.
>>
>> (Dropped Rob, devicetree and dri mailing lists)
>>
>> Hi Jernej,
>>
>> Is it OK if we take this patch for the next release? Or rather,
>> if there anything blocking this patch?
>
> I just made last check now and this patch is indeed OK. Before merging, please
> read explanation below.

Ack.

>
> Background:
> According to H3 datasheet and BSP driver, HDMI clock has M factor (divider) to
> correctly set pixel clock to desired value. However, Jens Kuske discovered
> that this factor doesn't play any role whatsoever and instead, division factor
> set in PHY registers is the important one. I confirmed that on BSP kernel by
> tying M factor to 0. Both, HDMI video and audio, still worked correctly.

Great. Sounds like what we have on A31 and earlier SoCs.

>
> So that flag is necessary to set pll-video to pixel clock * div factor. I can
> also change HDMI clock type to SUNXI_CCU_GATE (without M factor) and document
> discrepancy with datasheet in ccu-sun8i-h3.c. Alternatively to this patch,
> just in case, to be on the safe side, I can add pll-video clock phandle to the
> dt node. However, as far as I know, that might prevent selecting another
> parent on SoCs where HDMI clock has multiple parents.

It could be that the HDMI clock only drives the DW-HDMI sampler and other
internal logic, while the PHY takes the PLL input directly for the TMDS
clock? I'm not sure how you could verify this though. Maybe increase M
to the maximum, and see if there is any tearing or other artifacts?
Ideally we could just ask Allwinner...

You should change it to SUNXI_CCU_MUX_WITH_GATE if you want to change it.
If there are mux bits, even if there's only one valid setting, you should
still have the mux, so the kernel can actually correct any invalid settings
that may be incorrectly programmed into the hardware by the bootloader or
user. This would be a separate patch.

How we support other SoCs really depends on whether the TMDS clock bits
have a mux or not, or whether they are connected to the HDMI mod clock
in any way.

Regards
ChenYu

>
> Regards,
> Jernej
>
>>
>> Thanks
>> ChenYu
>>
>> >>ChenYu
>> >>
>> >>>  static SUNXI_CCU_GATE(hdmi_ddc_clk,    "hdmi-ddc",     "osc24M",
>> >>>
>> >>>                       0x154, BIT(31), 0);
>> >>>

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#1703995 — Re: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock

FromJernej Škrabec <jernej.skrabec@siol.net>
Date2017-08-04 15:50 +0200
SubjectRe: [linux-sunxi] [PATCH 10/13] [NOT FOR REVIEW NOW] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock
Message-ID<uaL9f-7DN-3@gated-at.bofh.it>
In reply to#1703820
Hi Chen-Yu,

Dne petek, 04. avgust 2017 ob 11:27:33 CEST je Chen-Yu Tsai napisal(a):
> On Fri, Aug 4, 2017 at 4:59 PM, Jernej Škrabec <jernej.skrabec@siol.net> 
wrote:
> > Hi Chen-Yu,
> > 
> > Dne petek, 04. avgust 2017 ob 06:29:50 CEST je Chen-Yu Tsai napisal(a):
> >> On Fri, Aug 4, 2017 at 12:16 PM, Icenowy Zheng <icenowy@aosc.io> wrote:
> >> > 于 2017年8月4日 GMT+08:00 下午12:15:27, Chen-Yu Tsai <wens@csie.org> 写到:
> >> >>Hi,
> >> >>
> >> >>On Tue, Aug 1, 2017 at 9:13 PM, Icenowy Zheng <icenowy@aosc.io> wrote:
> >> >>> From: Jernej Skrabec <jernej.skrabec@siol.net>
> >> >>> 
> >> >>> When setting the HDMI clock of H3, the PLL_VIDEO clock needs to be
> >> >>
> >> >>set.
> >> >>
> >> >>> Add CLK_SET_RATE_PARENT flag for H3 HDMI clock.
> >> >>> 
> >> >>> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> >> >>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> >> >>> ---
> >> >>> 
> >> >>>  drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
> >> >>>  1 file changed, 1 insertion(+), 1 deletion(-)
> >> >>> 
> >> >>> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
> >> >>
> >> >>b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
> >> >>
> >> >>> index b1127e8629d9..2ebb3d865b01 100644
> >> >>> --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
> >> >>> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
> >> >>> @@ -474,7 +474,7 @@ static SUNXI_CCU_GATE(avs_clk,
> >> >>
> >> >>"avs",          "osc24M",
> >> >>
> >> >>>  static const char * const hdmi_parents[] = { "pll-video" };
> >> >>>  static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
> >> >>> 
> >> >>> -                                0x150, 0, 4, 24, 2, BIT(31), 0);
> >> >>> +                                0x150, 0, 4, 24, 2, BIT(31),
> >> >>
> >> >>CLK_SET_RATE_PARENT);
> >> >>
> >> >>Line is longer than 80 characters.
> >> >>
> >> >>This looks independent enough so I've merged this for 4.14 with the
> >> >>offending line wrapped and the following tag added:
> >> >>
> >> >>Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
> >> >>
> >> > Please don't merge this now until Jernej send it.
> >> 
> >> (Dropped Rob, devicetree and dri mailing lists)
> >> 
> >> Hi Jernej,
> >> 
> >> Is it OK if we take this patch for the next release? Or rather,
> >> if there anything blocking this patch?
> > 
> > I just made last check now and this patch is indeed OK. Before merging,
> > please read explanation below.
> 
> Ack.
> 
> > Background:
> > According to H3 datasheet and BSP driver, HDMI clock has M factor
> > (divider) to correctly set pixel clock to desired value. However, Jens
> > Kuske discovered that this factor doesn't play any role whatsoever and
> > instead, division factor set in PHY registers is the important one. I
> > confirmed that on BSP kernel by tying M factor to 0. Both, HDMI video and
> > audio, still worked correctly.
> Great. Sounds like what we have on A31 and earlier SoCs.
> 
> > So that flag is necessary to set pll-video to pixel clock * div factor. I
> > can also change HDMI clock type to SUNXI_CCU_GATE (without M factor) and
> > document discrepancy with datasheet in ccu-sun8i-h3.c. Alternatively to
> > this patch, just in case, to be on the safe side, I can add pll-video
> > clock phandle to the dt node. However, as far as I know, that might
> > prevent selecting another parent on SoCs where HDMI clock has multiple
> > parents.
> 
> It could be that the HDMI clock only drives the DW-HDMI sampler and other
> internal logic, while the PHY takes the PLL input directly for the TMDS
> clock? I'm not sure how you could verify this though. Maybe increase M
> to the maximum, and see if there is any tearing or other artifacts?
> Ideally we could just ask Allwinner...

I just made quick test with maximum divider and everything seems to be ok. 
Unfortunately, I don't have time to do extensive test.

I will forward the question to Tl Lim and let's see if he can get the answer, 
since the situation for A64 is completely the same.

> 
> You should change it to SUNXI_CCU_MUX_WITH_GATE if you want to change it.
> If there are mux bits, even if there's only one valid setting, you should
> still have the mux, so the kernel can actually correct any invalid settings
> that may be incorrectly programmed into the hardware by the bootloader or
> user. This would be a separate patch.

I will leave it as it is for now. Will you still merge the patch?

Regards,
Jernej

> 
> How we support other SoCs really depends on whether the TMDS clock bits
> have a mux or not, or whether they are connected to the HDMI mod clock
> in any way.
> 
> Regards
> ChenYu
> 
> > Regards,
> > Jernej
> > 
> >> Thanks
> >> ChenYu
> >> 
> >> >>ChenYu
> >> >>
> >> >>>  static SUNXI_CCU_GATE(hdmi_ddc_clk,    "hdmi-ddc",     "osc24M",
> >> >>>  
> >> >>>                       0x154, BIT(31), 0);
> 
> --
> You received this message because you are subscribed to the Google Groups
> "linux-sunxi" group. To unsubscribe from this group and stop receiving
> emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com.
> For more options, visit https://groups.google.com/d/optout.

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