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[PATCH 00/10] A trial to Allwinner H3 DVFS support

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  [PATCH 00/10] A trial to Allwinner H3 DVFS support Icenowy Zheng <icenowy@aosc.io> - 2017-07-23 12:30 +0200
    [PATCH 07/10] cpufreq: dt: Add support for some new Allwinner SoCs Icenowy Zheng <icenowy@aosc.io> - 2017-07-23 12:30 +0200
      Re: [PATCH 07/10] cpufreq: dt: Add support for some new Allwinner  SoCs Viresh Kumar <viresh.kumar@linaro.org> - 2017-07-24 11:00 +0200
        Re: [PATCH 07/10] cpufreq: dt: Add support for some new Allwinner SoCs "Rafael J. Wysocki" <rjw@rjwysocki.net> - 2017-07-24 14:00 +0200
    [PATCH 04/10] ARM: sunxi: h3/h5: Add r_i2c I2C controller Icenowy Zheng <icenowy@aosc.io> - 2017-07-23 12:30 +0200
      Re: [linux-sunxi] [PATCH 04/10] ARM: sunxi: h3/h5: Add r_i2c I2C controller Chen-Yu Tsai <wens@csie.org> - 2017-07-24 05:20 +0200
    [PATCH 08/10] ARM: sun8i: h3: add operating-points-v2 table for CPU Icenowy Zheng <icenowy@aosc.io> - 2017-07-23 12:30 +0200
    [PATCH 03/10] ARM: sunxi: h3/h5: Add r_i2c pinmux node Icenowy Zheng <icenowy@aosc.io> - 2017-07-23 12:30 +0200
      Re: [linux-sunxi] [PATCH 03/10] ARM: sunxi: h3/h5: Add r_i2c pinmux node Chen-Yu Tsai <wens@csie.org> - 2017-07-24 05:10 +0200
        Re: [linux-sunxi] [PATCH 03/10] ARM: sunxi: h3/h5: Add r_i2c pinmux  node icenowy@aosc.io - 2017-07-24 05:10 +0200
    [PATCH 05/10] clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate change Icenowy Zheng <icenowy@aosc.io> - 2017-07-23 12:30 +0200
      Re: [PATCH 05/10] clk: sunxi-ng: h3: gate then ungate PLL CPU clk  after rate change Stephen Boyd <sboyd@codeaurora.org> - 2017-07-26 02:40 +0200
      Re: [linux-sunxi] [PATCH 05/10] clk: sunxi-ng: h3: gate then ungate  PLL CPU clk after rate change Chen-Yu Tsai <wens@csie.org> - 2017-07-26 09:20 +0200
    [PATCH 09/10] ARM: sun8i: h2+: add SY8113B regulator used by Orange Pi Zero board Icenowy Zheng <icenowy@aosc.io> - 2017-07-23 12:30 +0200
      Re: [linux-sunxi] [PATCH 09/10] ARM: sun8i: h2+: add SY8113B  regulator used by Orange Pi Zero board Chen-Yu Tsai <wens@csie.org> - 2017-07-24 06:10 +0200
    [PATCH 06/10] clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3 Icenowy Zheng <icenowy@aosc.io> - 2017-07-23 12:30 +0200
      Re: [linux-sunxi] [PATCH 06/10] clk: sunxi-ng: allow set parent clock  (PLL_CPUX) for CPUX clock on H3 Chen-Yu Tsai <wens@csie.org> - 2017-07-24 05:20 +0200
      Re: [PATCH 06/10] clk: sunxi-ng: allow set parent clock (PLL_CPUX)  for CPUX clock on H3 Stephen Boyd <sboyd@codeaurora.org> - 2017-07-26 02:40 +0200
    [PATCH 02/10] regulator: add support for SY8106A regulator Icenowy Zheng <icenowy@aosc.io> - 2017-07-23 12:30 +0200
      Re: [linux-sunxi] [PATCH 02/10] regulator: add support for SY8106A regulator Chen-Yu Tsai <wens@csie.org> - 2017-07-24 05:10 +0200
        Re: [linux-sunxi] [PATCH 02/10] regulator: add support for SY8106A  regulator icenowy@aosc.io - 2017-07-24 05:20 +0200
          Re: [linux-sunxi] [PATCH 02/10] regulator: add support for SY8106A  regulator icenowy@aosc.io - 2017-07-24 05:40 +0200
            Re: [linux-sunxi] [PATCH 02/10] regulator: add support for SY8106A regulator Chen-Yu Tsai <wens@csie.org> - 2017-07-24 08:20 +0200
          Re: [linux-sunxi] [PATCH 02/10] regulator: add support for SY8106A regulator Chen-Yu Tsai <wens@csie.org> - 2017-07-24 05:40 +0200
        Re: [linux-sunxi] [PATCH 02/10] regulator: add support for SY8106A  regulator Mark Brown <broonie@kernel.org> - 2017-07-24 17:10 +0200
    [PATCH 10/10] ARM: dts: sun8i: Add SY8106A regulator to Orange Pi PC Icenowy Zheng <icenowy@aosc.io> - 2017-07-23 12:30 +0200
      Re: [linux-sunxi] [PATCH 10/10] ARM: dts: sun8i: Add SY8106A  regulator to Orange Pi PC Chen-Yu Tsai <wens@csie.org> - 2017-07-26 09:10 +0200
        Re: [linux-sunxi] [PATCH 10/10] ARM: dts: sun8i: Add SY8106A regulator to Orange Pi PC Icenowy Zheng <icenowy@aosc.io> - 2017-07-26 09:20 +0200
          Re: [linux-sunxi] [PATCH 10/10] ARM: dts: sun8i: Add SY8106A  regulator to Orange Pi PC Chen-Yu Tsai <wens@csie.org> - 2017-07-26 09:40 +0200
            Re: [linux-sunxi] [PATCH 10/10] ARM: dts: sun8i: Add SY8106A  regulator to Orange Pi PC icenowy@aosc.io - 2017-07-26 09:40 +0200
              Re: [linux-sunxi] [PATCH 10/10] ARM: dts: sun8i: Add SY8106A  regulator to Orange Pi PC Ondřej Jirman <megous@megous.com> - 2017-07-26 12:40 +0200
                Re: [linux-sunxi] [PATCH 10/10] ARM: dts: sun8i: Add SY8106A  regulator to Orange Pi PC Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-07-26 13:50 +0200
                  Re: [linux-sunxi] [PATCH 10/10] ARM: dts: sun8i: Add SY8106A  regulator to Orange Pi PC icenowy@aosc.io - 2017-07-26 14:50 +0200
                  Re: [linux-sunxi] [PATCH 10/10] ARM: dts: sun8i: Add SY8106A  regulator to Orange Pi PC Ondřej Jirman <megous@megous.com> - 2017-07-26 15:00 +0200
    [PATCH 01/10] dt-bindings: add binding for the SY8160A voltage regulator Icenowy Zheng <icenowy@aosc.io> - 2017-07-23 12:30 +0200
      Re: [linux-sunxi] [PATCH 01/10] dt-bindings: add binding for the  SY8160A voltage regulator Chen-Yu Tsai <wens@csie.org> - 2017-07-24 05:10 +0200

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#1694282 — [PATCH 00/10] A trial to Allwinner H3 DVFS support

This patchset is a trial for DVFS support for Allwinner H3 SoC,
considering two kinds of adjustable regulators used on H3 boards:
SY8106A I2C-controlled regulator and SY8113B regulator (controllable
by GPIO with some special designs on the board).

PATCH 1 and PATCH 2 are for the SY8106A regulator, then PATCH 3 and
PATCH 4 are for the r_i2c bus, which is used by boards with SY8106A
to communicate with the regulator.

PATCH 5 and 6 are CCU fixes for H3 DVFS.

PATCH 7 is adding new compatible strings to the cpufreq-dt driver.

PATCH 8 adds the opp-v2 table for H3 SoC (without OPPs higher than
1.008GHz).

PATCH 9 and 10 finally adds DVFS support for two boards, Orange Pi
Zero (SY8113B) and Orange Pi PC (SY8106A).

Tested on these boards mentioned.

PATCH 9 and 10 finally adds DVFS support for two boards, Orange Pi
Zero (SY8113B) and Orange Pi PC (SY8106A).

Tested on these boards mentioned.

Chen-Yu Tsai (1):
  clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate change

Icenowy Zheng (4):
  clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3
  cpufreq: dt: Add support for some new Allwinner SoCs
  ARM: sun8i: h3: add operating-points-v2 table for CPU
  ARM: sun8i: h2+: add SY8113B regulator used by Orange Pi Zero board

Ondrej Jirman (5):
  dt-bindings: add binding for the SY8160A voltage regulator
  regulator: add support for SY8106A regulator
  ARM: sunxi: h3/h5: Add r_i2c pinmux node
  ARM: sunxi: h3/h5: Add r_i2c I2C controller
  ARM: dts: sun8i: Add SY8106A regulator to Orange Pi PC

 .../bindings/regulator/sy8106a-regulator.txt       |  21 +++
 arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts  |  21 +++
 arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts         |  19 +++
 arch/arm/boot/dts/sun8i-h3.dtsi                    |  38 ++++-
 arch/arm/boot/dts/sunxi-h3-h5.dtsi                 |  19 +++
 drivers/clk/sunxi-ng/ccu-sun8i-h3.c                |  13 +-
 drivers/cpufreq/cpufreq-dt-platdev.c               |   6 +
 drivers/regulator/Kconfig                          |   8 +-
 drivers/regulator/Makefile                         |   2 +-
 drivers/regulator/sy8106a-regulator.c              | 163 +++++++++++++++++++++
 10 files changed, 306 insertions(+), 4 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/regulator/sy8106a-regulator.txt
 create mode 100644 drivers/regulator/sy8106a-regulator.c

-- 
2.13.0

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#1694283 — [PATCH 07/10] cpufreq: dt: Add support for some new Allwinner SoCs

Some new Allwinner SoCs get supported in the kernel after the
compatibles are added to cpufreq-dt-platdev driver.

Add their compatible strings in the cpufreq-dt-platdev driver.

Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 drivers/cpufreq/cpufreq-dt-platdev.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index 2eb40d46d357..c3851453e84a 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -24,7 +24,11 @@ static const struct of_device_id machines[] __initconst = {
 	{ .compatible = "allwinner,sun8i-a23", },
 	{ .compatible = "allwinner,sun8i-a33", },
 	{ .compatible = "allwinner,sun8i-a83t", },
+	{ .compatible = "allwinner,sun8i-h2-plus", },
 	{ .compatible = "allwinner,sun8i-h3", },
+	{ .compatible = "allwinner,sun8i-v3s", },
+	{ .compatible = "allwinner,sun50i-a64", },
+	{ .compatible = "allwinner,sun50i-h5", },
 
 	{ .compatible = "apm,xgene-shadowcat", },
 
@@ -43,6 +47,8 @@ static const struct of_device_id machines[] __initconst = {
 	{ .compatible = "marvell,pxa250", },
 	{ .compatible = "marvell,pxa270", },
 
+	{ .compatible = "nextthing,gr8", },
+
 	{ .compatible = "samsung,exynos3250", },
 	{ .compatible = "samsung,exynos4210", },
 	{ .compatible = "samsung,exynos4212", },
-- 
2.13.0

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#1694548 — Re: [PATCH 07/10] cpufreq: dt: Add support for some new Allwinner SoCs

On 23-07-17, 18:27, Icenowy Zheng wrote:
> Some new Allwinner SoCs get supported in the kernel after the
> compatibles are added to cpufreq-dt-platdev driver.
> 
> Add their compatible strings in the cpufreq-dt-platdev driver.
> 
> Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
> Cc: Viresh Kumar <viresh.kumar@linaro.org>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
>  drivers/cpufreq/cpufreq-dt-platdev.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
> index 2eb40d46d357..c3851453e84a 100644
> --- a/drivers/cpufreq/cpufreq-dt-platdev.c
> +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
> @@ -24,7 +24,11 @@ static const struct of_device_id machines[] __initconst = {
>  	{ .compatible = "allwinner,sun8i-a23", },
>  	{ .compatible = "allwinner,sun8i-a33", },
>  	{ .compatible = "allwinner,sun8i-a83t", },
> +	{ .compatible = "allwinner,sun8i-h2-plus", },
>  	{ .compatible = "allwinner,sun8i-h3", },
> +	{ .compatible = "allwinner,sun8i-v3s", },
> +	{ .compatible = "allwinner,sun50i-a64", },
> +	{ .compatible = "allwinner,sun50i-h5", },
>  
>  	{ .compatible = "apm,xgene-shadowcat", },
>  
> @@ -43,6 +47,8 @@ static const struct of_device_id machines[] __initconst = {
>  	{ .compatible = "marvell,pxa250", },
>  	{ .compatible = "marvell,pxa270", },
>  
> +	{ .compatible = "nextthing,gr8", },
> +
>  	{ .compatible = "samsung,exynos3250", },
>  	{ .compatible = "samsung,exynos4210", },
>  	{ .compatible = "samsung,exynos4212", },

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>

-- 
viresh

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#1694663 — Re: [PATCH 07/10] cpufreq: dt: Add support for some new Allwinner SoCs

On Monday, July 24, 2017 02:23:49 PM Viresh Kumar wrote:
> On 23-07-17, 18:27, Icenowy Zheng wrote:
> > Some new Allwinner SoCs get supported in the kernel after the
> > compatibles are added to cpufreq-dt-platdev driver.
> > 
> > Add their compatible strings in the cpufreq-dt-platdev driver.
> > 
> > Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
> > Cc: Viresh Kumar <viresh.kumar@linaro.org>
> > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> > ---
> >  drivers/cpufreq/cpufreq-dt-platdev.c | 6 ++++++
> >  1 file changed, 6 insertions(+)
> > 
> > diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
> > index 2eb40d46d357..c3851453e84a 100644
> > --- a/drivers/cpufreq/cpufreq-dt-platdev.c
> > +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
> > @@ -24,7 +24,11 @@ static const struct of_device_id machines[] __initconst = {
> >  	{ .compatible = "allwinner,sun8i-a23", },
> >  	{ .compatible = "allwinner,sun8i-a33", },
> >  	{ .compatible = "allwinner,sun8i-a83t", },
> > +	{ .compatible = "allwinner,sun8i-h2-plus", },
> >  	{ .compatible = "allwinner,sun8i-h3", },
> > +	{ .compatible = "allwinner,sun8i-v3s", },
> > +	{ .compatible = "allwinner,sun50i-a64", },
> > +	{ .compatible = "allwinner,sun50i-h5", },
> >  
> >  	{ .compatible = "apm,xgene-shadowcat", },
> >  
> > @@ -43,6 +47,8 @@ static const struct of_device_id machines[] __initconst = {
> >  	{ .compatible = "marvell,pxa250", },
> >  	{ .compatible = "marvell,pxa270", },
> >  
> > +	{ .compatible = "nextthing,gr8", },
> > +
> >  	{ .compatible = "samsung,exynos3250", },
> >  	{ .compatible = "samsung,exynos4210", },
> >  	{ .compatible = "samsung,exynos4212", },
> 
> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
> 
> 

OK

I'm assuming this will go in via arm-soc along with the rest of the series.

Thanks,
Rafael

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#1694284 — [PATCH 04/10] ARM: sunxi: h3/h5: Add r_i2c I2C controller

From: Ondrej Jirman <megous@megous.com>

Allwinner H3/H5 SoCs have an I2C controller at PL GPIO bank.

Add support for it in the device tree.

Signed-off-by: Ondrej Jirman <megous@megous.com>
[Icenowy: Change to use r_ccu and change pinmux node name]
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 arch/arm/boot/dts/sunxi-h3-h5.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index b240099bc865..65643c4710a3 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -624,6 +624,20 @@
 			status = "disabled";
 		};
 
+		r_i2c: i2c@01f02400 {
+			compatible = "allwinner,sun6i-a31-i2c";
+			reg = <0x01f02400 0x400>;
+			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&r_i2c_pins>;
+			clocks = <&r_ccu CLK_APB0_I2C>;
+			clock-frequency = <100000>;
+			resets = <&r_ccu RST_APB0_I2C>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		r_pio: pinctrl@01f02c00 {
 			compatible = "allwinner,sun8i-h3-r-pinctrl";
 			reg = <0x01f02c00 0x400>;
-- 
2.13.0

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#1694420 — Re: [linux-sunxi] [PATCH 04/10] ARM: sunxi: h3/h5: Add r_i2c I2C controller

On Sun, Jul 23, 2017 at 6:27 PM, Icenowy Zheng <icenowy@aosc.io> wrote:
> From: Ondrej Jirman <megous@megous.com>
>
> Allwinner H3/H5 SoCs have an I2C controller at PL GPIO bank.
>
> Add support for it in the device tree.
>
> Signed-off-by: Ondrej Jirman <megous@megous.com>
> [Icenowy: Change to use r_ccu and change pinmux node name]
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

Reviewed-by: Chen-Yu Tsai <wens@csie.org>

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#1694285 — [PATCH 08/10] ARM: sun8i: h3: add operating-points-v2 table for CPU

The CPU on Allwinner H3 can do dynamic frequency scaling.

Add a DVFS table based on the one tweaked by Armbian developers, which
are proven to work stably on BSP kernels.

Frequencies higher than 1008MHz are temporarily dropped in the table, as
they may lead to over voltage on boards without proper regulator
settings or over temperature on boards with proper regulator settings.
They will be added back once regulator settings are ready and thermal
sensor driver is merged.

In order to satisfy all different regulators (SY8106A which is 50mV per
level, SY8113B which have two states: 1.1V and 1.3V, and some board with
non-tweakable regulators), all the OPPs are defined with a range which has
the target value as the minimum allowed value, and 1.3V (the highest
VDD-CPUX voltage suggested by the datasheet) as the maximum allowed value.
It's proven to work well with a board with SY8113B.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 arch/arm/boot/dts/sun8i-h3.dtsi | 38 +++++++++++++++++++++++++++++++++++++-
 1 file changed, 37 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index b36f9f423c39..a0cee17fe44b 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -43,32 +43,68 @@
 #include "sunxi-h3-h5.dtsi"
 
 / {
+	cpu0_opp_table: opp_table0 {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@480000000 {
+			opp-hz = /bits/ 64 <480000000>;
+			opp-microvolt = <980000 980000 1300000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@648000000 {
+			opp-hz = /bits/ 64 <816000000>;
+			opp-microvolt = <1020000 1020000 1300000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@912000000 {
+			opp-hz = /bits/ 64 <960000000>;
+			opp-microvolt = <1080000 1080000 1300000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@1008000000 {
+			opp-hz = /bits/ 64 <1008000000>;
+			opp-microvolt = <1140000 1140000 1300000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		cpu@0 {
+		cpu0: cpu@0 {
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			reg = <0>;
+			clocks = <&ccu CLK_CPUX>;
+			clock-names = "cpu";
+			operating-points-v2 = <&cpu0_opp_table>;
+			#cooling-cells = <0x2>;
 		};
 
 		cpu@1 {
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			reg = <1>;
+			operating-points-v2 = <&cpu0_opp_table>;
 		};
 
 		cpu@2 {
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			reg = <2>;
+			operating-points-v2 = <&cpu0_opp_table>;
 		};
 
 		cpu@3 {
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			reg = <3>;
+			operating-points-v2 = <&cpu0_opp_table>;
 		};
 	};
 
-- 
2.13.0

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#1694286 — [PATCH 03/10] ARM: sunxi: h3/h5: Add r_i2c pinmux node

From: Ondrej Jirman <megous@megous.com>

H3/H5 SoCs contain an I2C controller optionally available
on the PL0 and PL1 pins. This patch adds pinmux configuration
for this controller.

Signed-off-by: Ondrej Jirman <megous@megous.com>
[Icenowy: change commit message and node name]
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 arch/arm/boot/dts/sunxi-h3-h5.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 6f2162608006..b240099bc865 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -639,6 +639,11 @@
 				pins = "PL11";
 				function = "s_cir_rx";
 			};
+
+			r_i2c_pins: r-i2c {
+				pins = "PL0", "PL1";
+				function = "s_twi";
+			};
 		};
 	};
 };
-- 
2.13.0

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#1694416 — Re: [linux-sunxi] [PATCH 03/10] ARM: sunxi: h3/h5: Add r_i2c pinmux node

On Sun, Jul 23, 2017 at 6:27 PM, Icenowy Zheng <icenowy@aosc.io> wrote:
> From: Ondrej Jirman <megous@megous.com>
>
> H3/H5 SoCs contain an I2C controller optionally available
> on the PL0 and PL1 pins. This patch adds pinmux configuration
> for this controller.
>
> Signed-off-by: Ondrej Jirman <megous@megous.com>
> [Icenowy: change commit message and node name]
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
>  arch/arm/boot/dts/sunxi-h3-h5.dtsi | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> index 6f2162608006..b240099bc865 100644
> --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> @@ -639,6 +639,11 @@
>                                 pins = "PL11";
>                                 function = "s_cir_rx";
>                         };
> +
> +                       r_i2c_pins: r-i2c {
> +                               pins = "PL0", "PL1";
> +                               function = "s_twi";

Can we fix the pinctrl driver to use standard names first? :(

ChenYu

> +                       };
>                 };
>         };
>  };
> --
> 2.13.0
>
> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com.
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#1694417 — Re: [linux-sunxi] [PATCH 03/10] ARM: sunxi: h3/h5: Add r_i2c pinmux node

在 2017-07-24 11:07，Chen-Yu Tsai 写道：
> On Sun, Jul 23, 2017 at 6:27 PM, Icenowy Zheng <icenowy@aosc.io> wrote:
>> From: Ondrej Jirman <megous@megous.com>
>> 
>> H3/H5 SoCs contain an I2C controller optionally available
>> on the PL0 and PL1 pins. This patch adds pinmux configuration
>> for this controller.
>> 
>> Signed-off-by: Ondrej Jirman <megous@megous.com>
>> [Icenowy: change commit message and node name]
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>> ---
>>  arch/arm/boot/dts/sunxi-h3-h5.dtsi | 5 +++++
>>  1 file changed, 5 insertions(+)
>> 
>> diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi 
>> b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
>> index 6f2162608006..b240099bc865 100644
>> --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
>> +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
>> @@ -639,6 +639,11 @@
>>                                 pins = "PL11";
>>                                 function = "s_cir_rx";
>>                         };
>> +
>> +                       r_i2c_pins: r-i2c {
>> +                               pins = "PL0", "PL1";
>> +                               function = "s_twi";
> 
> Can we fix the pinctrl driver to use standard names first? :(

Oh good problem.

Let me fix it.

> 
> ChenYu
> 
>> +                       };
>>                 };
>>         };
>>  };
>> --
>> 2.13.0
>> 
>> --
>> You received this message because you are subscribed to the Google 
>> Groups "linux-sunxi" group.
>> To unsubscribe from this group and stop receiving emails from it, send 
>> an email to linux-sunxi+unsubscribe@googlegroups.com.
>> For more options, visit https://groups.google.com/d/optout.

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#1694287 — [PATCH 05/10] clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate change

From: Chen-Yu Tsai <wens@csie.org>

This patch utilizes the new PLL clk notifier to gate then ungate the
PLL CPU clock after rate changes. This should prevent any system hangs
resulting from cpufreq changes to the clk.

Reported-by: Ondrej Jirman <megous@megous.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Icenowy Zheng <icenowy@aosc.io>
---
 drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index 62e4f0d2b2fc..406d0aac9fd6 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -1103,6 +1103,13 @@ static const struct sunxi_ccu_desc sun50i_h5_ccu_desc = {
 	.num_resets	= ARRAY_SIZE(sun50i_h5_ccu_resets),
 };
 
+static struct ccu_pll_nb sun8i_h3_pll_cpu_nb = {
+	.common	= &pll_cpux_clk.common,
+	/* copy from pll_cpux_clk */
+	.enable	= BIT(31),
+	.lock	= BIT(28),
+};
+
 static struct ccu_mux_nb sun8i_h3_cpu_nb = {
 	.common		= &cpux_clk.common,
 	.cm		= &cpux_clk.mux,
@@ -1130,6 +1137,10 @@ static void __init sunxi_h3_h5_ccu_init(struct device_node *node,
 
 	sunxi_ccu_probe(node, reg, desc);
 
+	/* Gate then ungate PLL CPU after any rate changes */
+	ccu_pll_notifier_register(&sun8i_h3_pll_cpu_nb);
+
+	/* Reparent CPU during PLL CPU rate changes */
 	ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
 				  &sun8i_h3_cpu_nb);
 }
-- 
2.13.0

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#1696697 — Re: [PATCH 05/10] clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate change

On 07/23, Icenowy Zheng wrote:
> From: Chen-Yu Tsai <wens@csie.org>
> 
> This patch utilizes the new PLL clk notifier to gate then ungate the
> PLL CPU clock after rate changes. This should prevent any system hangs
> resulting from cpufreq changes to the clk.
> 
> Reported-by: Ondrej Jirman <megous@megous.com>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> Tested-by: Icenowy Zheng <icenowy@aosc.io>
> ---

Acked-by: Stephen Boyd <sboyd@codeaurora.org>

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

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#1696837 — Re: [linux-sunxi] [PATCH 05/10] clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate change

On Sun, Jul 23, 2017 at 6:27 PM, Icenowy Zheng <icenowy@aosc.io> wrote:
> From: Chen-Yu Tsai <wens@csie.org>
>
> This patch utilizes the new PLL clk notifier to gate then ungate the
> PLL CPU clock after rate changes. This should prevent any system hangs
> resulting from cpufreq changes to the clk.
>
> Reported-by: Ondrej Jirman <megous@megous.com>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> Tested-by: Icenowy Zheng <icenowy@aosc.io>

This is missing

Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")

ChenYu

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#1694288 — [PATCH 09/10] ARM: sun8i: h2+: add SY8113B regulator used by Orange Pi Zero board

Orange Pi Zero board has a SY8113B regulator, which is controlled via
GPIO and capable of outputing 1.1V when the PL6 GPIO is set to output 0
or 1.3V when the PL6 GPIO is set to input or output 1, and the output is
the power supply of the ARM cores in H2+ SoC.

Add the device tree node of this regulator and set the cpu's cpu-supply
property to it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
index 6713d0f2b3f4..28b4433bd7f7 100644
--- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
+++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
@@ -94,6 +94,27 @@
 		reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>;
 		post-power-on-delay-ms = <200>;
 	};
+
+	reg_sy8113b: gpio-regulator {
+		compatible = "regulator-gpio";
+
+		regulator-name = "vdd-cpux";
+		regulator-type = "voltage";
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-min-microvolt = <1100000>;
+		regulator-max-microvolt = <1300000>;
+		regulator-ramp-delay = <50>; /* 4ms */
+
+		gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
+		gpios-states = <0x1>;
+		states = <1100000 0x0
+			  1300000 0x1>;
+	};
+};
+
+&cpu0 {
+	cpu-supply = <&reg_sy8113b>;
 };
 
 &ehci0 {
-- 
2.13.0

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#1694437 — Re: [linux-sunxi] [PATCH 09/10] ARM: sun8i: h2+: add SY8113B regulator used by Orange Pi Zero board

On Sun, Jul 23, 2017 at 6:27 PM, Icenowy Zheng <icenowy@aosc.io> wrote:
> Orange Pi Zero board has a SY8113B regulator, which is controlled via
> GPIO and capable of outputing 1.1V when the PL6 GPIO is set to output 0
> or 1.3V when the PL6 GPIO is set to input or output 1, and the output is
> the power supply of the ARM cores in H2+ SoC.
>
> Add the device tree node of this regulator and set the cpu's cpu-supply
> property to it.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
>  arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
> index 6713d0f2b3f4..28b4433bd7f7 100644
> --- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
> +++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
> @@ -94,6 +94,27 @@
>                 reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>;
>                 post-power-on-delay-ms = <200>;
>         };
> +
> +       reg_sy8113b: gpio-regulator {
> +               compatible = "regulator-gpio";
> +

No need for the newline.

> +               regulator-name = "vdd-cpux";
> +               regulator-type = "voltage";
> +               regulator-boot-on;
> +               regulator-always-on;
> +               regulator-min-microvolt = <1100000>;
> +               regulator-max-microvolt = <1300000>;
> +               regulator-ramp-delay = <50>; /* 4ms */

You should also add "enable-active-high". The driver might not
honor the GPIO_ACTIVE_HIGH flag. AFAIK this was a problem with
the old GPIO API.

ChenYu

> +
> +               gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
> +               gpios-states = <0x1>;
> +               states = <1100000 0x0
> +                         1300000 0x1>;
> +       };
> +};
> +
> +&cpu0 {
> +       cpu-supply = <&reg_sy8113b>;
>  };
>
>  &ehci0 {
> --
> 2.13.0
>
> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com.
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#1694289 — [PATCH 06/10] clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3

The CPUX clock, which is the main clock of the ARM core on Allwinner H3,
can be adjusted by changing the frequency of the PLL_CPUX clock.

Allowing setting parent clock for the CPUX clock, thus the PLL_CPUX
clock can be adjusted when adjusting the CPUX clock.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index 406d0aac9fd6..4cdbc88f2783 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -135,7 +135,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
 static const char * const cpux_parents[] = { "osc32k", "osc24M",
 					     "pll-cpux" , "pll-cpux" };
 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
-		     0x050, 16, 2, CLK_IS_CRITICAL);
+		     0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
 
 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
 
-- 
2.13.0

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#1694419 — Re: [linux-sunxi] [PATCH 06/10] clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3

On Sun, Jul 23, 2017 at 6:27 PM, Icenowy Zheng <icenowy@aosc.io> wrote:
> The CPUX clock, which is the main clock of the ARM core on Allwinner H3,
> can be adjusted by changing the frequency of the PLL_CPUX clock.
>
> Allowing setting parent clock for the CPUX clock, thus the PLL_CPUX
> clock can be adjusted when adjusting the CPUX clock.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
Reviewed-by: Chen-Yu Tsai <wens@csie.org>

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#1696695 — Re: [PATCH 06/10] clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3

On 07/23, Icenowy Zheng wrote:
> The CPUX clock, which is the main clock of the ARM core on Allwinner H3,
> can be adjusted by changing the frequency of the PLL_CPUX clock.
> 
> Allowing setting parent clock for the CPUX clock, thus the PLL_CPUX
> clock can be adjusted when adjusting the CPUX clock.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---

Acked-by: Stephen Boyd <sboyd@codeaurora.org>

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

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#1694290 — [PATCH 02/10] regulator: add support for SY8106A regulator

From: Ondrej Jirman <megous@megous.com>

SY8106A is an I2C attached single output regulator made by Silergy Corp,
which is used on several Allwinner H3/H5 SBCs to control the power
supply of the ARM cores.

Add a driver for it.

Signed-off-by: Ondrej Jirman <megous@megous.com>
[Icenowy: Change commit message]
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 drivers/regulator/Kconfig             |   8 +-
 drivers/regulator/Makefile            |   2 +-
 drivers/regulator/sy8106a-regulator.c | 163 ++++++++++++++++++++++++++++++++++
 3 files changed, 171 insertions(+), 2 deletions(-)
 create mode 100644 drivers/regulator/sy8106a-regulator.c

diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 99b9362331b5..1efa73e18d07 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -764,6 +764,13 @@ config REGULATOR_STW481X_VMMC
 	  This driver supports the internal VMMC regulator in the STw481x
 	  PMIC chips.
 
+config REGULATOR_SY8106A
+	tristate "Silergy SY8106A regulator"
+	depends on I2C && (OF || COMPILE_TEST)
+	select REGMAP_I2C
+	help
+	  This driver supports SY8106A single output regulator.
+
 config REGULATOR_TPS51632
 	tristate "TI TPS51632 Power Regulator"
 	depends on I2C
@@ -938,4 +945,3 @@ config REGULATOR_WM8994
 	  WM8994 CODEC.
 
 endif
-
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 95b1e86ae692..f5120252f86a 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -95,6 +95,7 @@ obj-$(CONFIG_REGULATOR_S2MPS11) += s2mps11.o
 obj-$(CONFIG_REGULATOR_S5M8767) += s5m8767.o
 obj-$(CONFIG_REGULATOR_SKY81452) += sky81452-regulator.o
 obj-$(CONFIG_REGULATOR_STW481X_VMMC) += stw481x-vmmc.o
+obj-$(CONFIG_REGULATOR_SY8106A) += sy8106a-regulator.o
 obj-$(CONFIG_REGULATOR_TI_ABB) += ti-abb-regulator.o
 obj-$(CONFIG_REGULATOR_TPS6105X) += tps6105x-regulator.o
 obj-$(CONFIG_REGULATOR_TPS62360) += tps62360-regulator.o
@@ -120,5 +121,4 @@ obj-$(CONFIG_REGULATOR_WM8350) += wm8350-regulator.o
 obj-$(CONFIG_REGULATOR_WM8400) += wm8400-regulator.o
 obj-$(CONFIG_REGULATOR_WM8994) += wm8994-regulator.o
 
-
 ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
diff --git a/drivers/regulator/sy8106a-regulator.c b/drivers/regulator/sy8106a-regulator.c
new file mode 100644
index 000000000000..1df889f68b3d
--- /dev/null
+++ b/drivers/regulator/sy8106a-regulator.c
@@ -0,0 +1,163 @@
+/*
+ * sy8106a-regulator.c - Regulator device driver for SY8106A
+ *
+ * Copyright (C) 2016 Ondřej Jirman <megous@megous.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Library General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Library General Public License for more details.
+ */
+
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/of_regulator.h>
+
+#define SY8106A_REG_VOUT1_SEL		0x01
+#define SY8106A_REG_VOUT_COM		0x02
+#define SY8106A_REG_VOUT1_SEL_MASK	0x7f
+#define SY8106A_DISABLE_REG		BIT(0)
+#define SY8106A_GO_BIT			BIT(7)
+
+struct sy8106a {
+	struct regulator_dev *rdev;
+	struct regmap *regmap;
+};
+
+static const struct regmap_config sy8106a_regmap_config = {
+	.reg_bits = 8,
+	.val_bits = 8,
+};
+
+static int sy8106a_set_voltage_sel(struct regulator_dev *rdev, unsigned int sel)
+{
+	/* We use our set_voltage_sel in order to avoid unnecessary I2C
+	 * chatter, because the regulator_get_voltage_sel_regmap using
+	 * apply_bit would perform 4 unnecessary transfers instead of one,
+	 * increasing the chance of error.
+	 */
+	return regmap_write(rdev->regmap, rdev->desc->vsel_reg,
+			    sel | SY8106A_GO_BIT);
+}
+
+static const struct regulator_ops sy8106a_ops = {
+	.is_enabled = regulator_is_enabled_regmap,
+	.set_voltage_sel = sy8106a_set_voltage_sel,
+	.set_voltage_time_sel = regulator_set_voltage_time_sel,
+	.get_voltage_sel = regulator_get_voltage_sel_regmap,
+	.list_voltage = regulator_list_voltage_linear,
+};
+
+/* Default limits measured in millivolts and milliamps */
+#define SY8106A_MIN_MV		680
+#define SY8106A_MAX_MV		1950
+#define SY8106A_STEP_MV		10
+
+static const struct regulator_desc sy8106a_reg = {
+	.name = "SY8106A",
+	.id = 0,
+	.ops = &sy8106a_ops,
+	.type = REGULATOR_VOLTAGE,
+	.n_voltages = ((SY8106A_MAX_MV - SY8106A_MIN_MV) / SY8106A_STEP_MV) + 1,
+	.min_uV = (SY8106A_MIN_MV * 1000),
+	.uV_step = (SY8106A_STEP_MV * 1000),
+	.vsel_reg = SY8106A_REG_VOUT1_SEL,
+	.vsel_mask = SY8106A_REG_VOUT1_SEL_MASK,
+	.enable_reg = SY8106A_REG_VOUT_COM,
+	.enable_mask = SY8106A_DISABLE_REG,
+	.disable_val = SY8106A_DISABLE_REG,
+	.enable_is_inverted = 1,
+	.owner = THIS_MODULE,
+};
+
+/*
+ * I2C driver interface functions
+ */
+static int sy8106a_i2c_probe(struct i2c_client *i2c,
+			    const struct i2c_device_id *id)
+{
+	struct sy8106a *chip;
+	struct device *dev = &i2c->dev;
+	struct regulator_dev *rdev = NULL;
+	struct regulator_config config = { };
+	unsigned int selector;
+	int error;
+
+	chip = devm_kzalloc(&i2c->dev, sizeof(struct sy8106a), GFP_KERNEL);
+	if (!chip)
+		return -ENOMEM;
+
+	chip->regmap = devm_regmap_init_i2c(i2c, &sy8106a_regmap_config);
+	if (IS_ERR(chip->regmap)) {
+		error = PTR_ERR(chip->regmap);
+		dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
+			error);
+		return error;
+	}
+
+	config.dev = &i2c->dev;
+	config.regmap = chip->regmap;
+	config.driver_data = chip;
+
+	config.of_node = dev->of_node;
+	config.init_data = of_get_regulator_init_data(dev, dev->of_node,
+						      &sy8106a_reg);
+
+	if (!config.init_data)
+		return -ENOMEM;
+
+	/* Probe regulator */
+	error = regmap_read(chip->regmap, SY8106A_REG_VOUT1_SEL, &selector);
+	if (error) {
+		dev_err(&i2c->dev, "Failed to read voltage at probe time: %d\n", error);
+		return error;
+	}
+
+	rdev = devm_regulator_register(&i2c->dev, &sy8106a_reg, &config);
+	if (IS_ERR(rdev)) {
+		error = PTR_ERR(rdev);
+		dev_err(&i2c->dev, "Failed to register SY8106A regulator: %d\n", error);
+		return error;
+	}
+
+	chip->rdev = rdev;
+
+	i2c_set_clientdata(i2c, chip);
+
+	return 0;
+}
+
+static const struct of_device_id sy8106a_i2c_of_match[] = {
+	{ .compatible = "silergy,sy8106a" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, sy8106a_i2c_of_match);
+
+static const struct i2c_device_id sy8106a_i2c_id[] = {
+	{ "sy8106a", 0 },
+	{ },
+};
+MODULE_DEVICE_TABLE(i2c, sy8106a_i2c_id);
+
+static struct i2c_driver sy8106a_regulator_driver = {
+	.driver = {
+		.name = "sy8106a",
+		.of_match_table	= of_match_ptr(sy8106a_i2c_of_match),
+	},
+	.probe = sy8106a_i2c_probe,
+	.id_table = sy8106a_i2c_id,
+};
+
+module_i2c_driver(sy8106a_regulator_driver);
+
+MODULE_AUTHOR("Ondřej Jirman <megous@megous.com>");
+MODULE_DESCRIPTION("Regulator device driver for Silergy SY8106A");
+MODULE_LICENSE("GPL v2");
-- 
2.13.0

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#1694415 — Re: [linux-sunxi] [PATCH 02/10] regulator: add support for SY8106A regulator

On Sun, Jul 23, 2017 at 6:27 PM, Icenowy Zheng <icenowy@aosc.io> wrote:
> From: Ondrej Jirman <megous@megous.com>
>
> SY8106A is an I2C attached single output regulator made by Silergy Corp,
> which is used on several Allwinner H3/H5 SBCs to control the power
> supply of the ARM cores.
>
> Add a driver for it.
>
> Signed-off-by: Ondrej Jirman <megous@megous.com>
> [Icenowy: Change commit message]
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
>  drivers/regulator/Kconfig             |   8 +-
>  drivers/regulator/Makefile            |   2 +-
>  drivers/regulator/sy8106a-regulator.c | 163 ++++++++++++++++++++++++++++++++++
>  3 files changed, 171 insertions(+), 2 deletions(-)
>  create mode 100644 drivers/regulator/sy8106a-regulator.c
>
> diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
> index 99b9362331b5..1efa73e18d07 100644
> --- a/drivers/regulator/Kconfig
> +++ b/drivers/regulator/Kconfig
> @@ -764,6 +764,13 @@ config REGULATOR_STW481X_VMMC
>           This driver supports the internal VMMC regulator in the STw481x
>           PMIC chips.
>
> +config REGULATOR_SY8106A
> +       tristate "Silergy SY8106A regulator"
> +       depends on I2C && (OF || COMPILE_TEST)
> +       select REGMAP_I2C
> +       help
> +         This driver supports SY8106A single output regulator.
> +
>  config REGULATOR_TPS51632
>         tristate "TI TPS51632 Power Regulator"
>         depends on I2C
> @@ -938,4 +945,3 @@ config REGULATOR_WM8994
>           WM8994 CODEC.
>
>  endif
> -
> diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
> index 95b1e86ae692..f5120252f86a 100644
> --- a/drivers/regulator/Makefile
> +++ b/drivers/regulator/Makefile
> @@ -95,6 +95,7 @@ obj-$(CONFIG_REGULATOR_S2MPS11) += s2mps11.o
>  obj-$(CONFIG_REGULATOR_S5M8767) += s5m8767.o
>  obj-$(CONFIG_REGULATOR_SKY81452) += sky81452-regulator.o
>  obj-$(CONFIG_REGULATOR_STW481X_VMMC) += stw481x-vmmc.o
> +obj-$(CONFIG_REGULATOR_SY8106A) += sy8106a-regulator.o
>  obj-$(CONFIG_REGULATOR_TI_ABB) += ti-abb-regulator.o
>  obj-$(CONFIG_REGULATOR_TPS6105X) += tps6105x-regulator.o
>  obj-$(CONFIG_REGULATOR_TPS62360) += tps62360-regulator.o
> @@ -120,5 +121,4 @@ obj-$(CONFIG_REGULATOR_WM8350) += wm8350-regulator.o
>  obj-$(CONFIG_REGULATOR_WM8400) += wm8400-regulator.o
>  obj-$(CONFIG_REGULATOR_WM8994) += wm8994-regulator.o
>
> -
>  ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
> diff --git a/drivers/regulator/sy8106a-regulator.c b/drivers/regulator/sy8106a-regulator.c
> new file mode 100644
> index 000000000000..1df889f68b3d
> --- /dev/null
> +++ b/drivers/regulator/sy8106a-regulator.c
> @@ -0,0 +1,163 @@
> +/*
> + * sy8106a-regulator.c - Regulator device driver for SY8106A
> + *
> + * Copyright (C) 2016 Ondřej Jirman <megous@megous.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Library General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * Library General Public License for more details.
> + */
> +
> +#include <linux/err.h>
> +#include <linux/i2c.h>
> +#include <linux/module.h>
> +#include <linux/regmap.h>
> +#include <linux/regulator/driver.h>
> +#include <linux/regulator/of_regulator.h>
> +
> +#define SY8106A_REG_VOUT1_SEL          0x01
> +#define SY8106A_REG_VOUT_COM           0x02
> +#define SY8106A_REG_VOUT1_SEL_MASK     0x7f
> +#define SY8106A_DISABLE_REG            BIT(0)
> +#define SY8106A_GO_BIT                 BIT(7)
> +
> +struct sy8106a {
> +       struct regulator_dev *rdev;
> +       struct regmap *regmap;
> +};
> +
> +static const struct regmap_config sy8106a_regmap_config = {
> +       .reg_bits = 8,
> +       .val_bits = 8,
> +};
> +
> +static int sy8106a_set_voltage_sel(struct regulator_dev *rdev, unsigned int sel)
> +{
> +       /* We use our set_voltage_sel in order to avoid unnecessary I2C
> +        * chatter, because the regulator_get_voltage_sel_regmap using
> +        * apply_bit would perform 4 unnecessary transfers instead of one,
> +        * increasing the chance of error.
> +        */
> +       return regmap_write(rdev->regmap, rdev->desc->vsel_reg,
> +                           sel | SY8106A_GO_BIT);

There should also be an explanation of what the "go bit" does.
In this case it enables control of the voltage over I2C.

> +}
> +
> +static const struct regulator_ops sy8106a_ops = {
> +       .is_enabled = regulator_is_enabled_regmap,
> +       .set_voltage_sel = sy8106a_set_voltage_sel,
> +       .set_voltage_time_sel = regulator_set_voltage_time_sel,
> +       .get_voltage_sel = regulator_get_voltage_sel_regmap,
> +       .list_voltage = regulator_list_voltage_linear,

No enable/disable ops?

> +};
> +
> +/* Default limits measured in millivolts and milliamps */
> +#define SY8106A_MIN_MV         680
> +#define SY8106A_MAX_MV         1950
> +#define SY8106A_STEP_MV                10
> +
> +static const struct regulator_desc sy8106a_reg = {
> +       .name = "SY8106A",
> +       .id = 0,
> +       .ops = &sy8106a_ops,
> +       .type = REGULATOR_VOLTAGE,
> +       .n_voltages = ((SY8106A_MAX_MV - SY8106A_MIN_MV) / SY8106A_STEP_MV) + 1,
> +       .min_uV = (SY8106A_MIN_MV * 1000),
> +       .uV_step = (SY8106A_STEP_MV * 1000),
> +       .vsel_reg = SY8106A_REG_VOUT1_SEL,
> +       .vsel_mask = SY8106A_REG_VOUT1_SEL_MASK,
> +       .enable_reg = SY8106A_REG_VOUT_COM,
> +       .enable_mask = SY8106A_DISABLE_REG,
> +       .disable_val = SY8106A_DISABLE_REG,
> +       .enable_is_inverted = 1,

As the regulator core helpers currently are, there is no way to disable
this regulator. regulator_disable_regmap looks like:

        if (rdev->desc->enable_is_inverted) {
                val = rdev->desc->enable_val;
                if (!val)
                        val = rdev->desc->enable_mask;
        } else {
                val = rdev->desc->disable_val;
        }

        return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg,
                                  rdev->desc->enable_mask, val);

Note the fallback to enable_mask if enable_val is not set. The enable
helper has a similar structure. This regulator uses an enable value
of 0, and disable value of 1, it is impossible to get it right. As
it is now, it doesn't really make sense to me.

The code was introduced in ca5d1b3524b4 ("regulator: helpers: Modify
helpers enabling multi-bit control"). I wonder if it was an unintended
consequence of the change? (original author CC-ed)

> +       .owner = THIS_MODULE,
> +};
> +
> +/*
> + * I2C driver interface functions
> + */
> +static int sy8106a_i2c_probe(struct i2c_client *i2c,
> +                           const struct i2c_device_id *id)
> +{
> +       struct sy8106a *chip;
> +       struct device *dev = &i2c->dev;
> +       struct regulator_dev *rdev = NULL;
> +       struct regulator_config config = { };
> +       unsigned int selector;
> +       int error;
> +
> +       chip = devm_kzalloc(&i2c->dev, sizeof(struct sy8106a), GFP_KERNEL);
> +       if (!chip)
> +               return -ENOMEM;
> +
> +       chip->regmap = devm_regmap_init_i2c(i2c, &sy8106a_regmap_config);
> +       if (IS_ERR(chip->regmap)) {
> +               error = PTR_ERR(chip->regmap);
> +               dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
> +                       error);
> +               return error;
> +       }
> +
> +       config.dev = &i2c->dev;
> +       config.regmap = chip->regmap;
> +       config.driver_data = chip;
> +
> +       config.of_node = dev->of_node;
> +       config.init_data = of_get_regulator_init_data(dev, dev->of_node,
> +                                                     &sy8106a_reg);
> +
> +       if (!config.init_data)
> +               return -ENOMEM;
> +
> +       /* Probe regulator */
> +       error = regmap_read(chip->regmap, SY8106A_REG_VOUT1_SEL, &selector);
> +       if (error) {
> +               dev_err(&i2c->dev, "Failed to read voltage at probe time: %d\n", error);
> +               return error;
> +       }
> +
> +       rdev = devm_regulator_register(&i2c->dev, &sy8106a_reg, &config);
> +       if (IS_ERR(rdev)) {
> +               error = PTR_ERR(rdev);
> +               dev_err(&i2c->dev, "Failed to register SY8106A regulator: %d\n", error);
> +               return error;
> +       }
> +
> +       chip->rdev = rdev;
> +
> +       i2c_set_clientdata(i2c, chip);
> +
> +       return 0;
> +}
> +
> +static const struct of_device_id sy8106a_i2c_of_match[] = {
> +       { .compatible = "silergy,sy8106a" },
> +       { },
> +};
> +MODULE_DEVICE_TABLE(of, sy8106a_i2c_of_match);
> +
> +static const struct i2c_device_id sy8106a_i2c_id[] = {
> +       { "sy8106a", 0 },
> +       { },
> +};
> +MODULE_DEVICE_TABLE(i2c, sy8106a_i2c_id);
> +
> +static struct i2c_driver sy8106a_regulator_driver = {
> +       .driver = {
> +               .name = "sy8106a",
> +               .of_match_table = of_match_ptr(sy8106a_i2c_of_match),
> +       },
> +       .probe = sy8106a_i2c_probe,
> +       .id_table = sy8106a_i2c_id,
> +};
> +
> +module_i2c_driver(sy8106a_regulator_driver);
> +
> +MODULE_AUTHOR("Ondřej Jirman <megous@megous.com>");
> +MODULE_DESCRIPTION("Regulator device driver for Silergy SY8106A");
> +MODULE_LICENSE("GPL v2");

This should be "GPL", to match what the license at the very top says.

Regards
ChenYu

> --
> 2.13.0
>
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