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[PATCH 0/3] ARM: dts: am335x-evm: am437xx: dra7xx: Enable NAND DMA prefetch by default

Started byFranklin S Cooper Jr <fcooper@ti.com>
First post2017-07-26 04:20 +0200
Last post2017-07-26 04:20 +0200
Articles 4 — 1 participant

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  [PATCH 0/3] ARM: dts: am335x-evm: am437xx: dra7xx: Enable NAND DMA prefetch by default Franklin S Cooper Jr <fcooper@ti.com> - 2017-07-26 04:20 +0200
    [PATCH 1/3] ARM: dts: am335x-evm: Enable NAND dma prefetch by default Franklin S Cooper Jr <fcooper@ti.com> - 2017-07-26 04:20 +0200
    [PATCH 2/3] ARM: dts: am437xx: Enable NAND dma prefetch by default Franklin S Cooper Jr <fcooper@ti.com> - 2017-07-26 04:20 +0200
    [PATCH 3/3] ARM: dts: dra7xx: Enable NAND dma prefetch by default Franklin S Cooper Jr <fcooper@ti.com> - 2017-07-26 04:20 +0200

#1696727 — [PATCH 0/3] ARM: dts: am335x-evm: am437xx: dra7xx: Enable NAND DMA prefetch by default

FromFranklin S Cooper Jr <fcooper@ti.com>
Date2017-07-26 04:20 +0200
Subject[PATCH 0/3] ARM: dts: am335x-evm: am437xx: dra7xx: Enable NAND DMA prefetch by default
Message-ID<u7k5z-2Jt-1@gated-at.bofh.it>
Enable NAND DMA prefetch by default for AM335x, AM437x and DRA7x evms that
include NAND.

The below commit went into additional details regarding performance numbers
seen between the two modes.

commit aa7abd312c11 ("mtd: nand: omap2: Support parsing dma channel information from DT")

Franklin S Cooper Jr (3):
  ARM: dts: am335x-evm: Enable NAND dma prefetch by default
  ARM: dts: am437xx: Enable NAND dma prefetch by default
  ARM: dts: dra7xx: Enable NAND dma prefetch by default

 arch/arm/boot/dts/am335x-evm.dts        | 1 +
 arch/arm/boot/dts/am437x-gp-evm.dts     | 1 +
 arch/arm/boot/dts/am43x-epos-evm.dts    | 1 +
 arch/arm/boot/dts/dra7-evm.dts          | 1 +
 arch/arm/boot/dts/dra72-evm-common.dtsi | 1 +
 5 files changed, 5 insertions(+)

-- 
2.10.0

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#1696728 — [PATCH 1/3] ARM: dts: am335x-evm: Enable NAND dma prefetch by default

FromFranklin S Cooper Jr <fcooper@ti.com>
Date2017-07-26 04:20 +0200
Subject[PATCH 1/3] ARM: dts: am335x-evm: Enable NAND dma prefetch by default
Message-ID<u7k5A-2Jt-3@gated-at.bofh.it>
In reply to#1696727
Currently the default method of prefetch polled shows the highest
possible read and write speed when minimal non NAND background
activity is being done. But it is also very CPU intensive to reach
these high speeds (CPU load of 99% via mtd performance tests). While
DMA prefetch only uses 50% of the CPU to achieve around 23% less in
top read and write performance.

However, as the non NAND CPU load increases the read and write
performance takes a large hit when using polled prefetch. Therefore,
prefetch dma mode ends up outperforming prefetch polled in general
"system level" test. So switch to using dma prefetch by default since
it is likely what most users would prefer.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
---
 arch/arm/boot/dts/am335x-evm.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 1c37a7c..ddd8975 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -531,6 +531,7 @@
 		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
 			     <1 IRQ_TYPE_NONE>;	/* termcount */
 		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
+		ti,nand-xfer-type = "prefetch-dma";
 		ti,nand-ecc-opt = "bch8";
 		ti,elm-id = <&elm>;
 		nand-bus-width = <8>;
-- 
2.10.0

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#1696730 — [PATCH 2/3] ARM: dts: am437xx: Enable NAND dma prefetch by default

FromFranklin S Cooper Jr <fcooper@ti.com>
Date2017-07-26 04:20 +0200
Subject[PATCH 2/3] ARM: dts: am437xx: Enable NAND dma prefetch by default
Message-ID<u7k5A-2Jt-9@gated-at.bofh.it>
In reply to#1696727
Currently the default method of prefetch polled shows the highest
possible read and write speed when minimal non NAND background
activity is being done. But it is also very CPU intensive to reach
these high speeds (CPU load of 99% via mtd performance tests). While
DMA prefetch only uses 50% of the CPU to achieve around 23% less in
top read and write performance.

However, as the non NAND CPU load increases the read and write
performance takes a large hit when using polled prefetch. Therefore,
prefetch dma mode ends up outperforming prefetch polled in general
"system level" test. So switch to using dma prefetch by default since
it is likely what most users would prefer.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
---
 arch/arm/boot/dts/am437x-gp-evm.dts  | 1 +
 arch/arm/boot/dts/am43x-epos-evm.dts | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index 29a538e..a0a4ed0 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -842,6 +842,7 @@
 		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
 			     <1 IRQ_TYPE_NONE>;	/* termcount */
 		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>;	/* gpmc_wait0 */
+		ti,nand-xfer-type = "prefetch-dma";
 		ti,nand-ecc-opt = "bch16";
 		ti,elm-id = <&elm>;
 		nand-bus-width = <8>;
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index 54f40f3..9d276af 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -564,6 +564,7 @@
 		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
 			     <1 IRQ_TYPE_NONE>;	/* termcount */
 		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>;	/* gpmc_wait0 */
+		ti,nand-xfer-type = "prefetch-dma";
 		ti,nand-ecc-opt = "bch16";
 		ti,elm-id = <&elm>;
 		nand-bus-width = <8>;
-- 
2.10.0

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#1696731 — [PATCH 3/3] ARM: dts: dra7xx: Enable NAND dma prefetch by default

FromFranklin S Cooper Jr <fcooper@ti.com>
Date2017-07-26 04:20 +0200
Subject[PATCH 3/3] ARM: dts: dra7xx: Enable NAND dma prefetch by default
Message-ID<u7k5A-2Jt-5@gated-at.bofh.it>
In reply to#1696727
Currently the default method of prefetch polled shows the highest
possible read and write speed when minimal non NAND background
activity is being done. But it is also very CPU intensive to reach
these high speeds (CPU load of 99% via mtd performance tests). While
DMA prefetch only uses 50% of the CPU to achieve around 23% less in
top read and write performance.

However, as the non NAND CPU load increases the read and write
performance takes a large hit when using polled prefetch. Therefore,
prefetch dma mode ends up outperforming prefetch polled in general
"system level" test. So switch to using dma prefetch by default since
it is likely what most users would prefer.

Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
---
 arch/arm/boot/dts/dra7-evm.dts          | 1 +
 arch/arm/boot/dts/dra72-evm-common.dtsi | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index f47fc4d..7d55af9 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -556,6 +556,7 @@
 		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
 			     <1 IRQ_TYPE_NONE>; /* termcount */
 		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
+		ti,nand-xfer-type = "prefetch-dma";
 		ti,nand-ecc-opt = "bch8";
 		ti,elm-id = <&elm>;
 		nand-bus-width = <16>;
diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi
index 8578054..1830483 100644
--- a/arch/arm/boot/dts/dra72-evm-common.dtsi
+++ b/arch/arm/boot/dts/dra72-evm-common.dtsi
@@ -311,6 +311,7 @@
 		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
 			     <1 IRQ_TYPE_NONE>;	/* termcount */
 		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
+		ti,nand-xfer-type = "prefetch-dma";
 		ti,nand-ecc-opt = "bch8";
 		ti,elm-id = <&elm>;
 		nand-bus-width = <16>;
-- 
2.10.0

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