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Groups > linux.kernel > #1689092 > unrolled thread
| Started by | Jacob Chen <jacob-chen@iotwrt.com> |
|---|---|
| First post | 2017-07-17 16:20 +0200 |
| Last post | 2017-07-17 16:20 +0200 |
| Articles | 3 — 1 participant |
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[PATCH v2 0/5] arm64: dts: add rk3399 display-related nodes Jacob Chen <jacob-chen@iotwrt.com> - 2017-07-17 16:20 +0200
[PATCH v2 4/5] arm64: dts: rockchip: add rk3399 mipi nodes Jacob Chen <jacob-chen@iotwrt.com> - 2017-07-17 16:20 +0200
[PATCH v2 1/5] arm64: dts: rockchip: Add rk3399 vop and display-subsystem Jacob Chen <jacob-chen@iotwrt.com> - 2017-07-17 16:20 +0200
| From | Jacob Chen <jacob-chen@iotwrt.com> |
|---|---|
| Date | 2017-07-17 16:20 +0200 |
| Subject | [PATCH v2 0/5] arm64: dts: add rk3399 display-related nodes |
| Message-ID | <u4f2p-69R-13@gated-at.bofh.it> |
This series patches add the display-related nodes for rk3399. Tested with kernel base on drm-misc and below patches. https://cgit.freedesktop.org/drm/drm-misc/ "drm: bridge: synopsys/dw-hdmi: Provide default configuration function for HDMI 2.0 PHY" "iommu/rockchip: Enable Rockchip IOMMU on ARM64" HDMI could work and have a display output. eDP could link with panel but i didn't get a display(Maybe something wrong in power things). For convenience, i think we should have those nodes in kernel now. changes in V2: - remove unused clock and reg for VOP. - correct author. Mark Yao (1): arm64: dts: rockchip: Add rk3399 vop and display-subsystem Elaine Zhang (1): arm64: dts: rockchip: add pd_edp node for rk3399 Yakir Yang (1): arm64: dts: rockchip: add rk3399 edp nodes Jacob Chen (2): arm64: dts: rockchip: add rk3399 mipi nodes arm64: dts: rockchip: add rk3399 hdmi nodes arch/arm64/boot/dts/rockchip/rk3399.dtsi | 198 +++++++++++++++++++++++++++++++ 1 file changed, 198 insertions(+) -- 2.7.4
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| From | Jacob Chen <jacob-chen@iotwrt.com> |
|---|---|
| Date | 2017-07-17 16:20 +0200 |
| Subject | [PATCH v2 4/5] arm64: dts: rockchip: add rk3399 mipi nodes |
| Message-ID | <u4f2q-69R-31@gated-at.bofh.it> |
| In reply to | #1689092 |
Add an mipi node, and also add mipi endpoints to vopb and vopl
output port nodes.
Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 44 ++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index c0371af..5c5c9d9 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1475,6 +1475,11 @@
#address-cells = <1>;
#size-cells = <0>;
+ vopl_out_mipi: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&mipi_in_vopl>;
+ };
+
vopl_out_edp: endpoint@1 {
reg = <1>;
remote-endpoint = <&edp_in_vopl>;
@@ -1516,6 +1521,11 @@
remote-endpoint = <&edp_in_vopb>;
};
+ vopb_out_mipi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&mipi_in_vopb>;
+ };
+
};
};
@@ -1531,6 +1541,40 @@
status = "disabled";
};
+ mipi_dsi: mipi@ff960000 {
+ compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0x0 0xff960000 0x0 0x8000>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
+ <&cru SCLK_DPHY_TX0_CFG>;
+ clock-names = "ref", "pclk", "phy_cfg";
+ power-domains = <&power RK3399_PD_VIO>;
+ rockchip,grf = <&grf>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mipi_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_in_vopb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_mipi>;
+ };
+ mipi_in_vopl: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_mipi>;
+ };
+ };
+ };
+ };
+
edp: edp@ff970000 {
compatible = "rockchip,rk3399-edp";
reg = <0x0 0xff970000 0x0 0x8000>;
--
2.7.4
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| From | Jacob Chen <jacob-chen@iotwrt.com> |
|---|---|
| Date | 2017-07-17 16:20 +0200 |
| Subject | [PATCH v2 1/5] arm64: dts: rockchip: Add rk3399 vop and display-subsystem |
| Message-ID | <u4f2q-69R-35@gated-at.bofh.it> |
| In reply to | #1689092 |
From: Mark Yao <mark.yao@rock-chips.com>
Add devicetree nodes for rk3399 VOP (Video Output Processors), and the
top level display-subsystem root node.
Later patches add endpoints (eDP, HDMI, MIPI, etc) that attach to the
VOPs' output ports.
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 65 ++++++++++++++++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index e795135..978057d 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1455,6 +1455,71 @@
status = "disabled";
};
+ vopl: vop@ff8f0000 {
+ compatible = "rockchip,rk3399-vop-lit";
+ reg = <0x0 0xff8f0000 0x0 0x3efc>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+ resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
+ reset-names = "axi", "ahb", "dclk";
+ power-domains = <&power RK3399_PD_VOPL>;
+ iommus = <&vopl_mmu>;
+ status = "disabled";
+
+ vopl_out: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ vopl_mmu: iommu@ff8f3f00 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff8f3f00 0x0 0x100>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "vopl_mmu";
+ clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
+ clock-names = "aclk", "hclk";
+ power-domains = <&power RK3399_PD_VOPL>;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ vopb: vop@ff900000 {
+ compatible = "rockchip,rk3399-vop-big";
+ reg = <0x0 0xff900000 0x0 0x3efc>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+ resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
+ reset-names = "axi", "ahb", "dclk";
+ power-domains = <&power RK3399_PD_VOPB>;
+ iommus = <&vopb_mmu>;
+ status = "disabled";
+
+ vopb_out: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ vopb_mmu: iommu@ff903f00 {
+ compatible = "rockchip,iommu";
+ reg = <0x0 0xff903f00 0x0 0x100>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "vopb_mmu";
+ clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
+ clock-names = "aclk", "hclk";
+ power-domains = <&power RK3399_PD_VOPB>;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ display-subsystem {
+ compatible = "rockchip,display-subsystem";
+ ports = <&vopl_out>, <&vopb_out>;
+ };
+
pinctrl: pinctrl {
compatible = "rockchip,rk3399-pinctrl";
rockchip,grf = <&grf>;
--
2.7.4
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