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Re: [PATCH 2/7] staging: fsl-mc: use generic memory barriers

Started byRobin Murphy <robin.murphy@arm.com>
First post2017-07-17 15:40 +0200
Last post2017-07-17 15:50 +0200
Articles 2 — 2 participants

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  Re: [PATCH 2/7] staging: fsl-mc: use generic memory barriers Robin Murphy <robin.murphy@arm.com> - 2017-07-17 15:40 +0200
    Re: [PATCH 2/7] staging: fsl-mc: use generic memory barriers Laurentiu Tudor <laurentiu.tudor@nxp.com> - 2017-07-17 15:50 +0200

#1689045 — Re: [PATCH 2/7] staging: fsl-mc: use generic memory barriers

FromRobin Murphy <robin.murphy@arm.com>
Date2017-07-17 15:40 +0200
SubjectRe: [PATCH 2/7] staging: fsl-mc: use generic memory barriers
Message-ID<u4epJ-5H0-33@gated-at.bofh.it>
On 17/07/17 14:26, laurentiu.tudor@nxp.com wrote:
> From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
> 
> No need to use arch-specific memory barriers; switch to using generic
> ones. The rmb()s were useless so drop them.
> 
> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
> ---
>  drivers/staging/fsl-mc/bus/mc-sys.c | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/staging/fsl-mc/bus/mc-sys.c b/drivers/staging/fsl-mc/bus/mc-sys.c
> index a1704c3..012abd5 100644
> --- a/drivers/staging/fsl-mc/bus/mc-sys.c
> +++ b/drivers/staging/fsl-mc/bus/mc-sys.c
> @@ -127,7 +127,8 @@ static inline void mc_write_command(struct mc_command __iomem *portal,
>  	/* copy command parameters into the portal */
>  	for (i = 0; i < MC_CMD_NUM_OF_PARAMS; i++)
>  		__raw_writeq(cmd->params[i], &portal->params[i]);
> -	__iowmb();
> +	/* ensure command params are committed before submitting it */
> +	wmb();
>  
>  	/* submit the command by writing the header */
>  	__raw_writeq(cmd->header, &portal->header);

AFAICS, just using writeq() here should ensure sufficient order against
the previous iomem accessors, without the need for explicit barriers.

Also, note that the __raw_*() variants aren't endian-safe, so consider
updating things to *_relaxed() where ordering doesn't matter.

Robin.

> @@ -150,9 +151,7 @@ static inline enum mc_cmd_status mc_read_response(struct mc_command __iomem *
>  	enum mc_cmd_status status;
>  
>  	/* Copy command response header from MC portal: */
> -	__iormb();
>  	resp->header = __raw_readq(&portal->header);
> -	__iormb();
>  	status = mc_cmd_hdr_read_status(resp);
>  	if (status != MC_CMD_STATUS_OK)
>  		return status;
> @@ -160,7 +159,6 @@ static inline enum mc_cmd_status mc_read_response(struct mc_command __iomem *
>  	/* Copy command response data from MC portal: */
>  	for (i = 0; i < MC_CMD_NUM_OF_PARAMS; i++)
>  		resp->params[i] = __raw_readq(&portal->params[i]);
> -	__iormb();
>  
>  	return status;
>  }
> 

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#1689064

FromLaurentiu Tudor <laurentiu.tudor@nxp.com>
Date2017-07-17 15:50 +0200
Message-ID<u4ezp-5Kj-45@gated-at.bofh.it>
In reply to#1689045
On 07/17/2017 04:38 PM, Robin Murphy wrote:
> On 17/07/17 14:26, laurentiu.tudor@nxp.com wrote:
>> From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
>>
>> No need to use arch-specific memory barriers; switch to using generic
>> ones. The rmb()s were useless so drop them.
>>
>> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
>> ---
>>   drivers/staging/fsl-mc/bus/mc-sys.c | 6 ++----
>>   1 file changed, 2 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/staging/fsl-mc/bus/mc-sys.c b/drivers/staging/fsl-mc/bus/mc-sys.c
>> index a1704c3..012abd5 100644
>> --- a/drivers/staging/fsl-mc/bus/mc-sys.c
>> +++ b/drivers/staging/fsl-mc/bus/mc-sys.c
>> @@ -127,7 +127,8 @@ static inline void mc_write_command(struct mc_command __iomem *portal,
>>   	/* copy command parameters into the portal */
>>   	for (i = 0; i < MC_CMD_NUM_OF_PARAMS; i++)
>>   		__raw_writeq(cmd->params[i], &portal->params[i]);
>> -	__iowmb();
>> +	/* ensure command params are committed before submitting it */
>> +	wmb();
>>
>>   	/* submit the command by writing the header */
>>   	__raw_writeq(cmd->header, &portal->header);
>
> AFAICS, just using writeq() here should ensure sufficient order against
> the previous iomem accessors, without the need for explicit barriers.

Endianess is handled in the callers, this function should leave the raw 
data unchanged. So the raw version was chosen on purpose.

> Also, note that the __raw_*() variants aren't endian-safe, so consider
> updating things to *_relaxed() where ordering doesn't matter.
>

That's what i tried in the first place but encountered compilation 
errors on 32-bit powerpc & 32-bit x86 having to do with writeq/readq 
variants not being available (IIRC). So that's why i switched to the 
32-bit variants in the end.

---
Thanks & Best Regards, Laurentiu

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