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Groups > linux.kernel > #1682983 > unrolled thread
| Started by | Ludovic Barre <ludovic.Barre@st.com> |
|---|---|
| First post | 2017-07-07 09:30 +0200 |
| Last post | 2017-07-07 09:30 +0200 |
| Articles | 5 — 2 participants |
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[PATCH 0/8] irqchip: stm32: add stm32h7 support Ludovic Barre <ludovic.Barre@st.com> - 2017-07-07 09:30 +0200
[PATCH 8/8] ARM: dts: stm32: add support of exti on stm32h743 pinctrl Ludovic Barre <ludovic.Barre@st.com> - 2017-07-07 09:30 +0200
Re: [PATCH 8/8] ARM: dts: stm32: add support of exti on stm32h743 pinctrl Alexandre Torgue <alexandre.torgue@st.com> - 2017-07-07 10:20 +0200
[PATCH 4/8] irqchip: stm32: add stm32h7 support Ludovic Barre <ludovic.Barre@st.com> - 2017-07-07 09:30 +0200
[PATCH 2/8] irqchip: stm32: add multi-bank management Ludovic Barre <ludovic.Barre@st.com> - 2017-07-07 09:30 +0200
| From | Ludovic Barre <ludovic.Barre@st.com> |
|---|---|
| Date | 2017-07-07 09:30 +0200 |
| Subject | [PATCH 0/8] irqchip: stm32: add stm32h7 support |
| Message-ID | <u0vS9-Am-3@gated-at.bofh.it> |
From: Ludovic Barre <ludovic.barre@st.com> This series adds: -management of multi-bank of external interrupts stm32h7 has up to 96 inputs (3 banks of 32 inputs) -fix initial value after cold/hot boot (wakeup issue) Ludovic Barre (8): irqchip: stm32: select GENERIC_IRQ_CHIP irqchip: stm32: add multi-bank management dt-bindings: interrupt-controllers: add compatible string for stm32h7 irqchip: stm32: add stm32h7 support irqchip: stm32: fix initial values irqchip: stm32: move the wakeup on interrupt mask ARM: dts: stm32: add exti support for stm32h743 ARM: dts: stm32: add support of exti on stm32h743 pinctrl .../interrupt-controller/st,stm32-exti.txt | 4 +- arch/arm/boot/dts/stm32h743-pinctrl.dtsi | 24 +++ arch/arm/boot/dts/stm32h743.dtsi | 8 + drivers/irqchip/Kconfig | 1 + drivers/irqchip/irq-stm32-exti.c | 194 +++++++++++++++------ 5 files changed, 181 insertions(+), 50 deletions(-) -- 2.7.4
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| From | Ludovic Barre <ludovic.Barre@st.com> |
|---|---|
| Date | 2017-07-07 09:30 +0200 |
| Subject | [PATCH 8/8] ARM: dts: stm32: add support of exti on stm32h743 pinctrl |
| Message-ID | <u0vSa-Am-25@gated-at.bofh.it> |
| In reply to | #1682983 |
From: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
---
arch/arm/boot/dts/stm32h743-pinctrl.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
index fcc1e06..8854d26 100644
--- a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
@@ -49,6 +49,8 @@
#size-cells = <1>;
compatible = "st,stm32h743-pinctrl";
ranges = <0 0x58020000 0x3000>;
+ interrupt-parent = <&exti>;
+ st,syscfg = <&syscfg 0x8>;
pins-are-numbered;
gpioa: gpio@58020000 {
@@ -57,6 +59,8 @@
reg = <0x0 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOA";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpiob: gpio@58020400 {
@@ -65,6 +69,8 @@
reg = <0x400 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOB";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpioc: gpio@58020800 {
@@ -73,6 +79,8 @@
reg = <0x800 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOC";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpiod: gpio@58020c00 {
@@ -81,6 +89,8 @@
reg = <0xc00 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOD";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpioe: gpio@58021000 {
@@ -89,6 +99,8 @@
reg = <0x1000 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOE";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpiof: gpio@58021400 {
@@ -97,6 +109,8 @@
reg = <0x1400 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOF";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpiog: gpio@58021800 {
@@ -105,6 +119,8 @@
reg = <0x1800 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOG";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpioh: gpio@58021c00 {
@@ -113,6 +129,8 @@
reg = <0x1c00 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOH";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpioi: gpio@58022000 {
@@ -121,6 +139,8 @@
reg = <0x2000 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOI";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpioj: gpio@58022400 {
@@ -129,6 +149,8 @@
reg = <0x2400 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOJ";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpiok: gpio@58022800 {
@@ -137,6 +159,8 @@
reg = <0x2800 0x400>;
clocks = <&timer_clk>;
st,bank-name = "GPIOK";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
usart1_pins: usart1@0 {
--
2.7.4
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| From | Alexandre Torgue <alexandre.torgue@st.com> |
|---|---|
| Date | 2017-07-07 10:20 +0200 |
| Subject | Re: [PATCH 8/8] ARM: dts: stm32: add support of exti on stm32h743 pinctrl |
| Message-ID | <u0wEy-1dx-11@gated-at.bofh.it> |
| In reply to | #1682986 |
Hi Ludovic
On 07/07/2017 09:26 AM, Ludovic Barre wrote:
> From: Ludovic Barre <ludovic.barre@st.com>
>
> Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
> ---
Can you fill commit message please
> arch/arm/boot/dts/stm32h743-pinctrl.dtsi | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
> index fcc1e06..8854d26 100644
> --- a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
> +++ b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi
> @@ -49,6 +49,8 @@
> #size-cells = <1>;
> compatible = "st,stm32h743-pinctrl";
> ranges = <0 0x58020000 0x3000>;
> + interrupt-parent = <&exti>;
> + st,syscfg = <&syscfg 0x8>;
> pins-are-numbered;
>
> gpioa: gpio@58020000 {
> @@ -57,6 +59,8 @@
> reg = <0x0 0x400>;
> clocks = <&timer_clk>;
> st,bank-name = "GPIOA";
> + interrupt-controller;
> + #interrupt-cells = <2>;
> };
>
> gpiob: gpio@58020400 {
> @@ -65,6 +69,8 @@
> reg = <0x400 0x400>;
> clocks = <&timer_clk>;
> st,bank-name = "GPIOB";
> + interrupt-controller;
> + #interrupt-cells = <2>;
> };
>
> gpioc: gpio@58020800 {
> @@ -73,6 +79,8 @@
> reg = <0x800 0x400>;
> clocks = <&timer_clk>;
> st,bank-name = "GPIOC";
> + interrupt-controller;
> + #interrupt-cells = <2>;
> };
>
> gpiod: gpio@58020c00 {
> @@ -81,6 +89,8 @@
> reg = <0xc00 0x400>;
> clocks = <&timer_clk>;
> st,bank-name = "GPIOD";
> + interrupt-controller;
> + #interrupt-cells = <2>;
> };
>
> gpioe: gpio@58021000 {
> @@ -89,6 +99,8 @@
> reg = <0x1000 0x400>;
> clocks = <&timer_clk>;
> st,bank-name = "GPIOE";
> + interrupt-controller;
> + #interrupt-cells = <2>;
> };
>
> gpiof: gpio@58021400 {
> @@ -97,6 +109,8 @@
> reg = <0x1400 0x400>;
> clocks = <&timer_clk>;
> st,bank-name = "GPIOF";
> + interrupt-controller;
> + #interrupt-cells = <2>;
> };
>
> gpiog: gpio@58021800 {
> @@ -105,6 +119,8 @@
> reg = <0x1800 0x400>;
> clocks = <&timer_clk>;
> st,bank-name = "GPIOG";
> + interrupt-controller;
> + #interrupt-cells = <2>;
> };
>
> gpioh: gpio@58021c00 {
> @@ -113,6 +129,8 @@
> reg = <0x1c00 0x400>;
> clocks = <&timer_clk>;
> st,bank-name = "GPIOH";
> + interrupt-controller;
> + #interrupt-cells = <2>;
> };
>
> gpioi: gpio@58022000 {
> @@ -121,6 +139,8 @@
> reg = <0x2000 0x400>;
> clocks = <&timer_clk>;
> st,bank-name = "GPIOI";
> + interrupt-controller;
> + #interrupt-cells = <2>;
> };
>
> gpioj: gpio@58022400 {
> @@ -129,6 +149,8 @@
> reg = <0x2400 0x400>;
> clocks = <&timer_clk>;
> st,bank-name = "GPIOJ";
> + interrupt-controller;
> + #interrupt-cells = <2>;
> };
>
> gpiok: gpio@58022800 {
> @@ -137,6 +159,8 @@
> reg = <0x2800 0x400>;
> clocks = <&timer_clk>;
> st,bank-name = "GPIOK";
> + interrupt-controller;
> + #interrupt-cells = <2>;
> };
>
> usart1_pins: usart1@0 {
>
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| From | Ludovic Barre <ludovic.Barre@st.com> |
|---|---|
| Date | 2017-07-07 09:30 +0200 |
| Subject | [PATCH 4/8] irqchip: stm32: add stm32h7 support |
| Message-ID | <u0vSa-Am-31@gated-at.bofh.it> |
| In reply to | #1682983 |
From: Ludovic Barre <ludovic.barre@st.com>
stm32h7 has up to 96 input
(3 banks of 32 input max)
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
---
drivers/irqchip/irq-stm32-exti.c | 42 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
index 308cef5..69ae09d 100644
--- a/drivers/irqchip/irq-stm32-exti.c
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -38,6 +38,39 @@ static struct stm32_exti_bank *stm32f4xx_exti_banks[] = {
&stm32f4xx_exti_b1,
};
+static struct stm32_exti_bank stm32h7xx_exti_b1 = {
+ .imr_ofst = 0x80,
+ .emr_ofst = 0x84,
+ .rtsr_ofst = 0x00,
+ .ftsr_ofst = 0x04,
+ .swier_ofst = 0x08,
+ .pr_ofst = 0x88,
+};
+
+static struct stm32_exti_bank stm32h7xx_exti_b2 = {
+ .imr_ofst = 0x90,
+ .emr_ofst = 0x94,
+ .rtsr_ofst = 0x20,
+ .ftsr_ofst = 0x24,
+ .swier_ofst = 0x28,
+ .pr_ofst = 0x98,
+};
+
+static struct stm32_exti_bank stm32h7xx_exti_b3 = {
+ .imr_ofst = 0xA0,
+ .emr_ofst = 0xA4,
+ .rtsr_ofst = 0x40,
+ .ftsr_ofst = 0x44,
+ .swier_ofst = 0x48,
+ .pr_ofst = 0xA8,
+};
+
+static struct stm32_exti_bank *stm32h7xx_exti_banks[] = {
+ &stm32h7xx_exti_b1,
+ &stm32h7xx_exti_b2,
+ &stm32h7xx_exti_b3,
+};
+
static void stm32_irq_handler(struct irq_desc *desc)
{
struct irq_domain *domain = irq_desc_get_handler_data(desc);
@@ -244,3 +277,12 @@ static int __init stm32f4_exti_of_init(struct device_node *np,
}
IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init);
+
+static int __init stm32h7_exti_of_init(struct device_node *np,
+ struct device_node *parent)
+{
+ return stm32_exti_init(stm32h7xx_exti_banks,
+ ARRAY_SIZE(stm32h7xx_exti_banks), np);
+}
+
+IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init);
--
2.7.4
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| From | Ludovic Barre <ludovic.Barre@st.com> |
|---|---|
| Date | 2017-07-07 09:30 +0200 |
| Subject | [PATCH 2/8] irqchip: stm32: add multi-bank management |
| Message-ID | <u0vSa-Am-33@gated-at.bofh.it> |
| In reply to | #1682983 |
From: Ludovic Barre <ludovic.barre@st.com>
-prepare to manage multi-bank
-prepare to manage registers offset by compatible
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
---
drivers/irqchip/irq-stm32-exti.c | 137 ++++++++++++++++++++++++++-------------
1 file changed, 91 insertions(+), 46 deletions(-)
diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
index 491568c..308cef5 100644
--- a/drivers/irqchip/irq-stm32-exti.c
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -14,27 +14,52 @@
#include <linux/of_address.h>
#include <linux/of_irq.h>
-#define EXTI_IMR 0x0
-#define EXTI_EMR 0x4
-#define EXTI_RTSR 0x8
-#define EXTI_FTSR 0xc
-#define EXTI_SWIER 0x10
-#define EXTI_PR 0x14
+struct stm32_exti_bank {
+ u32 imr_ofst;
+ u32 emr_ofst;
+ u32 rtsr_ofst;
+ u32 ftsr_ofst;
+ u32 swier_ofst;
+ u32 pr_ofst;
+
+ u32 irqs_mask;
+};
+
+static struct stm32_exti_bank stm32f4xx_exti_b1 = {
+ .imr_ofst = 0x00,
+ .emr_ofst = 0x04,
+ .rtsr_ofst = 0x08,
+ .ftsr_ofst = 0x0C,
+ .swier_ofst = 0x10,
+ .pr_ofst = 0x14,
+};
+
+static struct stm32_exti_bank *stm32f4xx_exti_banks[] = {
+ &stm32f4xx_exti_b1,
+};
static void stm32_irq_handler(struct irq_desc *desc)
{
struct irq_domain *domain = irq_desc_get_handler_data(desc);
- struct irq_chip_generic *gc = domain->gc->gc[0];
struct irq_chip *chip = irq_desc_get_chip(desc);
+ unsigned int virq, nbanks = domain->gc->num_chips;
+ struct irq_chip_generic *gc;
+ struct stm32_exti_bank *stm32_bank;
unsigned long pending;
- int n;
+ int n, i, irq_base = 0;
chained_irq_enter(chip, desc);
- while ((pending = irq_reg_readl(gc, EXTI_PR))) {
- for_each_set_bit(n, &pending, BITS_PER_LONG) {
- generic_handle_irq(irq_find_mapping(domain, n));
- irq_reg_writel(gc, BIT(n), EXTI_PR);
+ for (i = 0; i < nbanks; i++, irq_base += BITS_PER_LONG) {
+ gc = irq_get_domain_generic_chip(domain, irq_base);
+ stm32_bank = gc->private;
+
+ while ((pending = irq_reg_readl(gc, stm32_bank->pr_ofst))) {
+ for_each_set_bit(n, &pending, BITS_PER_LONG) {
+ virq = irq_find_mapping(domain, irq_base + n);
+ generic_handle_irq(virq);
+ irq_reg_writel(gc, BIT(n), stm32_bank->pr_ofst);
+ }
}
}
@@ -44,13 +69,14 @@ static void stm32_irq_handler(struct irq_desc *desc)
static int stm32_irq_set_type(struct irq_data *data, unsigned int type)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
- int pin = data->hwirq;
+ struct stm32_exti_bank *stm32_bank = gc->private;
+ int pin = data->hwirq % BITS_PER_LONG;
u32 rtsr, ftsr;
irq_gc_lock(gc);
- rtsr = irq_reg_readl(gc, EXTI_RTSR);
- ftsr = irq_reg_readl(gc, EXTI_FTSR);
+ rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
+ ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
switch (type) {
case IRQ_TYPE_EDGE_RISING:
@@ -70,8 +96,8 @@ static int stm32_irq_set_type(struct irq_data *data, unsigned int type)
return -EINVAL;
}
- irq_reg_writel(gc, rtsr, EXTI_RTSR);
- irq_reg_writel(gc, ftsr, EXTI_FTSR);
+ irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst);
+ irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst);
irq_gc_unlock(gc);
@@ -81,17 +107,18 @@ static int stm32_irq_set_type(struct irq_data *data, unsigned int type)
static int stm32_irq_set_wake(struct irq_data *data, unsigned int on)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
- int pin = data->hwirq;
+ struct stm32_exti_bank *stm32_bank = gc->private;
+ int pin = data->hwirq % BITS_PER_LONG;
u32 emr;
irq_gc_lock(gc);
- emr = irq_reg_readl(gc, EXTI_EMR);
+ emr = irq_reg_readl(gc, stm32_bank->emr_ofst);
if (on)
emr |= BIT(pin);
else
emr &= ~BIT(pin);
- irq_reg_writel(gc, emr, EXTI_EMR);
+ irq_reg_writel(gc, emr, stm32_bank->emr_ofst);
irq_gc_unlock(gc);
@@ -101,11 +128,12 @@ static int stm32_irq_set_wake(struct irq_data *data, unsigned int on)
static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
unsigned int nr_irqs, void *data)
{
- struct irq_chip_generic *gc = d->gc->gc[0];
+ struct irq_chip_generic *gc;
struct irq_fwspec *fwspec = data;
irq_hw_number_t hwirq;
hwirq = fwspec->param[0];
+ gc = irq_get_domain_generic_chip(d, hwirq);
irq_map_generic_chip(d, virq, hwirq);
irq_domain_set_info(d, virq, hwirq, &gc->chip_types->chip, gc,
@@ -129,8 +157,8 @@ struct irq_domain_ops irq_exti_domain_ops = {
.free = stm32_exti_free,
};
-static int __init stm32_exti_init(struct device_node *node,
- struct device_node *parent)
+static int __init stm32_exti_init(struct stm32_exti_bank **stm32_exti_banks,
+ int bank_nr, struct device_node *node)
{
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
int nr_irqs, nr_exti, ret, i;
@@ -144,23 +172,16 @@ static int __init stm32_exti_init(struct device_node *node,
return -ENOMEM;
}
- /* Determine number of irqs supported */
- writel_relaxed(~0UL, base + EXTI_RTSR);
- nr_exti = fls(readl_relaxed(base + EXTI_RTSR));
- writel_relaxed(0, base + EXTI_RTSR);
-
- pr_info("%s: %d External IRQs detected\n", node->full_name, nr_exti);
-
- domain = irq_domain_add_linear(node, nr_exti,
+ domain = irq_domain_add_linear(node, bank_nr * BITS_PER_LONG,
&irq_exti_domain_ops, NULL);
if (!domain) {
pr_err("%s: Could not register interrupt domain.\n",
- node->name);
+ node->name);
ret = -ENOMEM;
goto out_unmap;
}
- ret = irq_alloc_domain_generic_chips(domain, nr_exti, 1, "exti",
+ ret = irq_alloc_domain_generic_chips(domain, BITS_PER_LONG, 1, "exti",
handle_edge_irq, clr, 0, 0);
if (ret) {
pr_err("%s: Could not allocate generic interrupt chip.\n",
@@ -168,18 +189,35 @@ static int __init stm32_exti_init(struct device_node *node,
goto out_free_domain;
}
- gc = domain->gc->gc[0];
- gc->reg_base = base;
- gc->chip_types->type = IRQ_TYPE_EDGE_BOTH;
- gc->chip_types->chip.name = gc->chip_types[0].chip.name;
- gc->chip_types->chip.irq_ack = irq_gc_ack_set_bit;
- gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit;
- gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit;
- gc->chip_types->chip.irq_set_type = stm32_irq_set_type;
- gc->chip_types->chip.irq_set_wake = stm32_irq_set_wake;
- gc->chip_types->regs.ack = EXTI_PR;
- gc->chip_types->regs.mask = EXTI_IMR;
- gc->chip_types->handler = handle_edge_irq;
+ for (i = 0; i < bank_nr; i++) {
+ struct stm32_exti_bank *stm32_bank = stm32_exti_banks[i];
+ u32 irqs_mask;
+
+ gc = irq_get_domain_generic_chip(domain, i * BITS_PER_LONG);
+
+ gc->reg_base = base;
+ gc->chip_types->type = IRQ_TYPE_EDGE_BOTH;
+ gc->chip_types->chip.name = gc->chip_types[0].chip.name;
+ gc->chip_types->chip.irq_ack = irq_gc_ack_set_bit;
+ gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit;
+ gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit;
+ gc->chip_types->chip.irq_set_type = stm32_irq_set_type;
+ gc->chip_types->chip.irq_set_wake = stm32_irq_set_wake;
+ gc->chip_types->regs.ack = stm32_bank->pr_ofst;
+ gc->chip_types->regs.mask = stm32_bank->imr_ofst;
+ gc->chip_types->handler = handle_edge_irq;
+ gc->private = stm32_bank;
+
+ /* Determine number of irqs supported */
+ writel_relaxed(~0UL, base + stm32_bank->rtsr_ofst);
+ irqs_mask = readl_relaxed(base + stm32_bank->rtsr_ofst);
+ stm32_bank->irqs_mask = irqs_mask;
+ nr_exti = fls(readl_relaxed(base + stm32_bank->rtsr_ofst));
+ writel_relaxed(0, base + stm32_bank->rtsr_ofst);
+
+ pr_info("%s: bank%d, External IRQs available:%#x\n",
+ node->full_name, i, irqs_mask);
+ }
nr_irqs = of_irq_count(node);
for (i = 0; i < nr_irqs; i++) {
@@ -198,4 +236,11 @@ static int __init stm32_exti_init(struct device_node *node,
return ret;
}
-IRQCHIP_DECLARE(stm32_exti, "st,stm32-exti", stm32_exti_init);
+static int __init stm32f4_exti_of_init(struct device_node *np,
+ struct device_node *parent)
+{
+ return stm32_exti_init(stm32f4xx_exti_banks,
+ ARRAY_SIZE(stm32f4xx_exti_banks), np);
+}
+
+IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init);
--
2.7.4
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