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| Started by | Florian Fainelli <f.fainelli@gmail.com> |
|---|---|
| First post | 2017-04-20 21:10 +0200 |
| Last post | 2017-04-20 21:10 +0200 |
| Articles | 2 — 1 participant |
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[PATCH 0/2] arm64: perf: Add L2 cache events for ARMv8 PMuv3 and A53 Florian Fainelli <f.fainelli@gmail.com> - 2017-04-20 21:10 +0200
[PATCH 2/2] arm64: pmu: Wire-up L2 cache events for ARMv8 PMUv3 Florian Fainelli <f.fainelli@gmail.com> - 2017-04-20 21:10 +0200
| From | Florian Fainelli <f.fainelli@gmail.com> |
|---|---|
| Date | 2017-04-20 21:10 +0200 |
| Subject | [PATCH 0/2] arm64: perf: Add L2 cache events for ARMv8 PMuv3 and A53 |
| Message-ID | <typCO-4oW-11@gated-at.bofh.it> |
Hi, While investigating why there were no L2 cache events generated for a Cortex A53-like PMU, it turned out that none of the L2 cache events were mapped. This is also the case for ARMv8 PMUv3, which seems a little odd considering they are defined. Thanks! Florian Fainelli (2): arm64: perf: Wire-up Cortex A53 L2 cache events and DTLB refills arm64: pmu: Wire-up L2 cache events for ARMv8 PMUv3 arch/arm64/kernel/perf_event.c | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.9.3
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| From | Florian Fainelli <f.fainelli@gmail.com> |
|---|---|
| Date | 2017-04-20 21:10 +0200 |
| Subject | [PATCH 2/2] arm64: pmu: Wire-up L2 cache events for ARMv8 PMUv3 |
| Message-ID | <typCO-4oW-23@gated-at.bofh.it> |
| In reply to | #1627752 |
The ARMv8 PMUv3 cache map did not include the L2 cache events, add them. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> --- arch/arm64/kernel/perf_event.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 4f011cdd756d..a664c575f3fd 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -264,6 +264,11 @@ static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE, [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL, + [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE, + [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL, + [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE, + [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL, + [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL, [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB, -- 2.9.3
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