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[PATCH 1/2] arm64: allwinner: a64: add EHCI0/OHCI0 nodes to A64 DTSI

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  [PATCH 1/2] arm64: allwinner: a64: add EHCI0/OHCI0 nodes to A64 DTSI Icenowy Zheng <icenowy@aosc.io> - 2017-04-14 15:20 +0200
    [PATCH 2/2] arm64: allwinner: a64: enable EHCI0/OHCI0 for Pine64 Icenowy Zheng <icenowy@aosc.io> - 2017-04-14 15:30 +0200
      Re: [PATCH 2/2] arm64: allwinner: a64: enable EHCI0/OHCI0 for Pine64 Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-04-17 10:00 +0200

#1623660 — [PATCH 1/2] arm64: allwinner: a64: add EHCI0/OHCI0 nodes to A64 DTSI

Allwinner A64 SoC features a pair of EHCI/OHCI controllers that can be
set to wire to USB0 port (the OTG-capable one), which can be used to
provide a better performance in host mode.

Add their device tree nodes.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index c7f669f5884f..65a344d9cea4 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -204,6 +204,28 @@
 			#phy-cells = <1>;
 		};
 
+		ehci0: usb@01c1a000 {
+			compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
+			reg = <0x01c1a000 0x100>;
+			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI0>,
+				 <&ccu CLK_BUS_EHCI0>,
+				 <&ccu CLK_USB_OHCI0>;
+			resets = <&ccu RST_BUS_OHCI0>,
+				 <&ccu RST_BUS_EHCI0>;
+			status = "disabled";
+		};
+
+		ohci0: usb@01c1a400 {
+			compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
+			reg = <0x01c1a400 0x100>;
+			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI0>,
+				 <&ccu CLK_USB_OHCI0>;
+			resets = <&ccu RST_BUS_OHCI0>;
+			status = "disabled";
+		};
+
 		ehci1: usb@01c1b000 {
 			compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
 			reg = <0x01c1b000 0x100>;
-- 
2.12.2

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#1623662 — [PATCH 2/2] arm64: allwinner: a64: enable EHCI0/OHCI0 for Pine64

As we have USB0 controller switch available on A64, we should now enable
the EHCI0/OHCI0 controllers for Pine64.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index c680ed385da3..4782add50b94 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -66,6 +66,10 @@
 	};
 };
 
+&ehci0 {
+	status = "okay";
+};
+
 &ehci1 {
 	status = "okay";
 };
@@ -91,6 +95,10 @@
 	status = "okay";
 };
 
+&ohci0 {
+	status = "okay";
+};
+
 &ohci1 {
 	status = "okay";
 };
-- 
2.12.2

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#1624587 — Re: [PATCH 2/2] arm64: allwinner: a64: enable EHCI0/OHCI0 for Pine64

[Multipart message — attachments visible in raw view] — view raw

On Fri, Apr 14, 2017 at 09:15:55PM +0800, Icenowy Zheng wrote:
> As we have USB0 controller switch available on A64, we should now enable
> the EHCI0/OHCI0 controllers for Pine64.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

Applied both, thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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