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[PATCH 0/8] i.MX7 PCIe related device tree changes

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  [PATCH 0/8] i.MX7 PCIe related device tree changes Andrey Smirnov <andrew.smirnov@gmail.com> - 2017-04-13 15:40 +0200
    [PATCH 1/8] Revert "ARM: dts: imx: Remove unexistant property" Andrey Smirnov <andrew.smirnov@gmail.com> - 2017-04-13 15:40 +0200
    [PATCH 4/8] ARM: dts: imx7s: Add node for GPC Andrey Smirnov <andrew.smirnov@gmail.com> - 2017-04-13 15:40 +0200
      Re: [PATCH 4/8] ARM: dts: imx7s: Add node for GPC Tyler Baker <tyler.baker@linaro.org> - 2017-04-13 21:10 +0200
        Re: [PATCH 4/8] ARM: dts: imx7s: Add node for GPC Tyler Baker <tyler.baker@linaro.org> - 2017-04-13 21:30 +0200
          Re: [PATCH 4/8] ARM: dts: imx7s: Add node for GPC Fabio Estevam <festevam@gmail.com> - 2017-04-13 22:00 +0200
            Re: [PATCH 4/8] ARM: dts: imx7s: Add node for GPC Tyler Baker <tyler.baker@linaro.org> - 2017-04-13 22:20 +0200
              Re: [PATCH 4/8] ARM: dts: imx7s: Add node for GPC Fabio Estevam <festevam@gmail.com> - 2017-04-13 23:00 +0200
                Re: [PATCH 4/8] ARM: dts: imx7s: Add node for GPC Andrey Smirnov <andrew.smirnov@gmail.com> - 2017-04-13 23:30 +0200
                Re: [PATCH 4/8] ARM: dts: imx7s: Add node for GPC Tyler Baker <tyler.baker@linaro.org> - 2017-04-13 23:40 +0200
                  Re: [PATCH 4/8] ARM: dts: imx7s: Add node for GPC Fabio Estevam <festevam@gmail.com> - 2017-04-14 00:10 +0200
        Re: [PATCH 4/8] ARM: dts: imx7s: Add node for GPC Fabio Estevam <festevam@gmail.com> - 2017-04-13 21:30 +0200
        Re: [PATCH 4/8] ARM: dts: imx7s: Add node for GPC Andrey Smirnov <andrew.smirnov@gmail.com> - 2017-04-13 23:30 +0200
      Re: [PATCH 4/8] ARM: dts: imx7s: Add node for GPC Shawn Guo <shawnguo@kernel.org> - 2017-04-14 05:50 +0200
        Re: [PATCH 4/8] ARM: dts: imx7s: Add node for GPC Andrey Smirnov <andrew.smirnov@gmail.com> - 2017-04-14 17:30 +0200
          Re: [PATCH 4/8] ARM: dts: imx7s: Add node for GPC Dong Aisheng <dongas86@gmail.com> - 2017-04-14 18:00 +0200
            Re: [PATCH 4/8] ARM: dts: imx7s: Add node for GPC Andrey Smirnov <andrew.smirnov@gmail.com> - 2017-04-14 18:00 +0200
    [PATCH 3/8] ARM: dts: imx7s: Adjust anatop-enable-bit for 'reg_1p0d' Andrey Smirnov <andrew.smirnov@gmail.com> - 2017-04-13 15:40 +0200
      Re: [PATCH 3/8] ARM: dts: imx7s: Adjust anatop-enable-bit for  'reg_1p0d' Shawn Guo <shawnguo@kernel.org> - 2017-04-14 05:30 +0200
        Re: [PATCH 3/8] ARM: dts: imx7s: Adjust anatop-enable-bit for 'reg_1p0d' Andrey Smirnov <andrew.smirnov@gmail.com> - 2017-04-14 16:40 +0200
      Re: [PATCH 3/8] ARM: dts: imx7s: Adjust anatop-enable-bit for  'reg_1p0d' Dong Aisheng <dongas86@gmail.com> - 2017-04-14 17:40 +0200
        Re: [PATCH 3/8] ARM: dts: imx7s: Adjust anatop-enable-bit for 'reg_1p0d' Andrey Smirnov <andrew.smirnov@gmail.com> - 2017-04-14 18:10 +0200
    [PATCH 2/8] ARM: dts: imx6: Specify 'anatop-enable-bit' where appropriate Andrey Smirnov <andrew.smirnov@gmail.com> - 2017-04-13 15:40 +0200
    Re: [PATCH 0/8] i.MX7 PCIe related device tree changes Tyler Baker <tyler.baker@linaro.org> - 2017-04-19 20:30 +0200

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#1623019 — [PATCH 0/8] i.MX7 PCIe related device tree changes

Shawn, everyone:

This series includes changes made to device-tree in order to support
PCIe on i.MX7 platform. They include:

     - Bringing 'anatop-enable-bit' property of ANATOP regulators back
       and extending it to all of the HW it is applicable to

     - Adding GPCv2 node for i.MX7 (which was missing, despite the
       irqchip driver for it being in the tree for quite some time)

     - Adding a PCIe node for i.MX7

     - Adding GPIO expander used by PCIe and enabling PCIe node from
       above on i.MX7 based Sabre board

As usual, feedback is welcome.

Thanks,
Andrey Smrinov

Andrey Smirnov (8):
  Revert "ARM: dts: imx: Remove unexistant property"
  ARM: dts: imx6: Specify 'anatop-enable-bit' where appropriate
  ARM: dts: imx7s: Adjust anatop-enable-bit for 'reg_1p0d'
  ARM: dts: imx7s: Add node for GPC
  ARM: dts: imx7s: Mark 'gpr' compatible with i.MX6 variant
  ARM: dts: imx7d-sdb: Add GPIO expander node
  ARM: dts: imx7d: Add node for PCIe controller
  ARM: dts: imx7d-sdb: Enable PCIe peripheral

 arch/arm/boot/dts/imx6qdl.dtsi  |  3 +++
 arch/arm/boot/dts/imx6sl.dtsi   |  3 +++
 arch/arm/boot/dts/imx6sx.dtsi   |  3 +++
 arch/arm/boot/dts/imx6ul.dtsi   |  1 +
 arch/arm/boot/dts/imx7d-sdb.dts | 39 +++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/imx7d.dtsi    | 38 ++++++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/imx7s.dtsi    | 31 +++++++++++++++++++++++++++++--
 7 files changed, 116 insertions(+), 2 deletions(-)

-- 
2.9.3

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#1623021 — [PATCH 1/8] Revert "ARM: dts: imx: Remove unexistant property"

Commit ca7734a ("regulator: anatop: Add support for
"anatop-enable-bit"") added code to support this particular binding
and 'anatop-enable-bit' is no longer an unused property.

This reverts commit 27958ccdf29e9971732e02494b48be54b0691269.

Cc: yurovsky@gmail.com
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/boot/dts/imx6ul.dtsi | 1 +
 arch/arm/boot/dts/imx7s.dtsi  | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index b9d7d2d..6da2b77 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -542,6 +542,7 @@
 					anatop-min-bit-val = <0>;
 					anatop-min-voltage = <2625000>;
 					anatop-max-voltage = <3400000>;
+					anatop-enable-bit = <0>;
 				};
 
 				reg_arm: regulator-vddcore {
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index c4f12fd..22c9788 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -516,6 +516,7 @@
 					anatop-min-bit-val = <8>;
 					anatop-min-voltage = <800000>;
 					anatop-max-voltage = <1200000>;
+					anatop-enable-bit = <31>;
 				};
 			};
 
-- 
2.9.3

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#1623025 — [PATCH 4/8] ARM: dts: imx7s: Add node for GPC

Add node for GPC and specify as a parent interrupt controller for SoC bus.

Cc: yurovsky@gmail.com
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/boot/dts/imx7s.dtsi | 27 ++++++++++++++++++++++++++-
 1 file changed, 26 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index 8fee299..1a7058f 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -42,6 +42,7 @@
  */
 
 #include <dt-bindings/clock/imx7d-clock.h>
+#include <dt-bindings/power/imx7-power.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -119,7 +120,7 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "simple-bus";
-		interrupt-parent = <&intc>;
+		interrupt-parent = <&gpc>;
 		ranges;
 
 		funnel@30041000 {
@@ -301,6 +302,7 @@
 			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 			#interrupt-cells = <3>;
 			interrupt-controller;
+			interrupt-parent = <&intc>;
 			reg = <0x31001000 0x1000>,
 			      <0x31002000 0x2000>,
 			      <0x31004000 0x2000>,
@@ -309,6 +311,7 @@
 
 		timer {
 			compatible = "arm,armv7-timer";
+			interrupt-parent = <&intc>;
 			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 				     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 				     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
@@ -564,6 +567,28 @@
 				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 				#reset-cells = <1>;
 			};
+
+			gpc: gpc@303a0000 {
+				compatible = "fsl,imx7d-gpc";
+				reg = <0x303a0000 0x10000>;
+				interrupt-controller;
+				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+				#interrupt-cells = <3>;
+				interrupt-parent = <&intc>;
+				#power-domain-cells = <1>;
+
+				pgc {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pgc_pcie_phy: pgc-pcie-phy-domain {
+						#power-domain-cells = <0>;
+
+						reg = <IMX7_POWER_DOMAIN_PCIE_PHY>;
+						power-supply = <&reg_1p0d>;
+					};
+				};
+			};
 		};
 
 		aips2: aips-bus@30400000 {
-- 
2.9.3

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#1623280 — Re: [PATCH 4/8] ARM: dts: imx7s: Add node for GPC

Hi Andrey,

On 13 April 2017 at 06:32, Andrey Smirnov <andrew.smirnov@gmail.com> wrote:
> Add node for GPC and specify as a parent interrupt controller for SoC bus.
>
> Cc: yurovsky@gmail.com
> Cc: Sascha Hauer <kernel@pengutronix.de>
> Cc: Fabio Estevam <fabio.estevam@nxp.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Russell King <linux@armlinux.org.uk>
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> ---
>  arch/arm/boot/dts/imx7s.dtsi | 27 ++++++++++++++++++++++++++-
>  1 file changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
> index 8fee299..1a7058f 100644
> --- a/arch/arm/boot/dts/imx7s.dtsi
> +++ b/arch/arm/boot/dts/imx7s.dtsi
> @@ -42,6 +42,7 @@
>   */
>[0
>  #include <dt-bindings/clock/imx7d-clock.h>
> +#include <dt-bindings/power/imx7-power.h>
>  #include <dt-bindings/gpio/gpio.h>
>  #include <dt-bindings/input/input.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -119,7 +120,7 @@
>                 #address-cells = <1>;
>                 #size-cells = <1>;
>                 compatible = "simple-bus";
> -               interrupt-parent = <&intc>;
> +               interrupt-parent = <&gpc>;

I've been testing your GPC/PCIe patch sets against v4.11-rc5 on my
imx7d-cl-som-imx7, but hit a bit of a wall. When gpc is set as the
interrupt-parent for the soc, the kernel seems to hang and not produce
any output on the serial port[0]. I tried to enable earlyprintk, but
no luck getting a trace. Reversing this change, gets the board
booting[1], but obviously isn't using the gpc which is needed for PCIe
support as I understand it. I assume you've tested these changes on a
imx7d-sdb and are not seeing a similar issue? You can find the patches
I've picked on top of v4.11-rc5 here[2], any idea what might be the
issue?

Cheers,

Tyler

[0] https://hastebin.com/zetohetuwi.coffeescript
[1] https://hastebin.com/uvacuyicuh.sql
[2] https://github.com/EmbeddedAndroid/linux/commits/tracking-ltd-imx-dev

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#1623283 — Re: [PATCH 4/8] ARM: dts: imx7s: Add node for GPC

On 13 April 2017 at 12:18, Fabio Estevam <festevam@gmail.com> wrote:
> On Thu, Apr 13, 2017 at 4:03 PM, Tyler Baker <tyler.baker@linaro.org> wrote:
>
>> I've been testing your GPC/PCIe patch sets against v4.11-rc5 on my
>> imx7d-cl-som-imx7, but hit a bit of a wall. When gpc is set as the
>> interrupt-parent for the soc, the kernel seems to hang and not produce
>> any output on the serial port[0]. I tried to enable earlyprintk, but
>> no luck getting a trace. Reversing this change, gets the board
>> booting[1], but obviously isn't using the gpc which is needed for PCIe
>> support as I understand it. I assume you've tested these changes on a
>> imx7d-sdb and are not seeing a similar issue? You can find the patches
>> I've picked on top of v4.11-rc5 here[2], any idea what might be the
>> issue?
>
> Thanks for the report.

No problem.

> It seems this series depends on the drivers/soc/imx/gpcv2.c patches
> that landed into linux-next.

Are you referring to the following patches?

"dt-bindings: Add GPCv2 power gating driver"
"soc: imx: Add GPCv2 power gating driver"

I've pulled these patches from Shawn's tree to test with, but still
not able to get anything functional. Is there another series I should
be looking at?

Thanks,

Tyler

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#1623315 — Re: [PATCH 4/8] ARM: dts: imx7s: Add node for GPC

On Thu, Apr 13, 2017 at 4:24 PM, Tyler Baker <tyler.baker@linaro.org> wrote:


> Are you referring to the following patches?
>
> "dt-bindings: Add GPCv2 power gating driver"
> "soc: imx: Add GPCv2 power gating driver"
>
> I've pulled these patches from Shawn's tree to test with, but still
> not able to get anything functional. Is there another series I should
> be looking at?

Yes, these are the ones I was thinking about. Maybe Andrey can help to
clarify then.

Thanks

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#1623325 — Re: [PATCH 4/8] ARM: dts: imx7s: Add node for GPC

On 13 April 2017 at 12:55, Fabio Estevam <festevam@gmail.com> wrote:
> On Thu, Apr 13, 2017 at 4:24 PM, Tyler Baker <tyler.baker@linaro.org> wrote:
>
>
>> Are you referring to the following patches?
>>
>> "dt-bindings: Add GPCv2 power gating driver"
>> "soc: imx: Add GPCv2 power gating driver"
>>
>> I've pulled these patches from Shawn's tree to test with, but still
>> not able to get anything functional. Is there another series I should
>> be looking at?
>
> Yes, these are the ones I was thinking about. Maybe Andrey can help to
> clarify then.

I've rebased this series on the next-20170413 for sanity sake, and
realized there doesn't appear to be a way to select CONFIG_IMX_GPCV2.
I forced it using 'default y' and configured with imx_v6_v7_defconfig.
Now my board is booting. Before this series is applied, it may be good
to have CONFIG_IMX_GPCV2 selected specifically for iMX7 platform,
otherwise there will be boot regressions.

I'd encounter a backtrace with next-20170413 +  imx_v6_v7_defconfig +
CONFIG_IMX_GPCV2=y

Backtrace:
[<c010c364>] (dump_backtrace) from [<c010c610>] (show_stack+0x18/0x1c)
  r7:00000000 r6:600000d3 r5:00000000 r4:c0e273dc
[<c010c5f8>] (show_stack) from [<c04070a4>] (dump_stack+0xb4/0xe8)
[<c0406ff0>] (dump_stack) from [<c0169e04>] (register_lock_class+0x208/0x5ec)
 r9:ef00d010 r8:ef00d010 r7:c1606448 r6:00000000 r5:00000000 r4:ffffe000
[<c0169bfc>] (register_lock_class) from [<c016da48>]
(__lock_acquire+0x7c/0x18d0)
 r10:c0e0af40 r9:ef00d010 r8:c0e274cc r7:00000001 r6:600000d3 r5:c1606448
 r4:ffffe000
[<c016d9cc>] (__lock_acquire) from [<c016fa4c>] (lock_acquire+0x70/0x90)
 r10:00000000 r9:ef007e38 r8:00000001 r7:00000001 r6:600000d3 r5:00000000
 r4:ffffe000
[<c016f9dc>] (lock_acquire) from [<c09accc8>] (_raw_spin_lock+0x30/0x40)
 r8:600000d3 r7:ef007e10 r6:00000001 r5:ef007e10 r4:ef00d000
[<c09acc98>] (_raw_spin_lock) from [<c04403a4>] (imx_gpcv2_irq_unmask+0x1c/0x5c)
 r4:ef00d000
[<c0440388>] (imx_gpcv2_irq_unmask) from [<c017e838>] (irq_enable+0x38/0x4c)
 r5:00000000 r4:ef007e00
[<c017e800>] (irq_enable) from [<c017e8d0>] (irq_startup+0x84/0x88)
 r5:00000000 r4:ef007e00
[<c017e84c>] (irq_startup) from [<c017cd7c>] (__setup_irq+0x538/0x5f4)
 r7:ef007e60 r6:00000015 r5:ef007e00 r4:ef007d00
[<c017c844>] (__setup_irq) from [<c017ce98>] (setup_irq+0x60/0xd0)
 r10:c0d5fa48 r9:efffcbc0 r8:ef007d00 r7:00000015 r6:ef007e10 r5:00000000
 r4:ef007e00
[<c017ce38>] (setup_irq) from [<c0d4dfdc>] (_mxc_timer_init+0x1f8/0x248)
 r9:efffcbc0 r8:00000003 r7:016e3600 r6:c0c69bbc r5:ef007c40 r4:ef007c00
[<c0d4dde4>] (_mxc_timer_init) from [<c0d4e0dc>] (mxc_timer_init_dt+0xb0/0xf8)
 r7:00000000 r6:c1669e48 r5:ef7ebf7c r4:ef007c00
[<c0d4e02c>] (mxc_timer_init_dt) from [<c0d4e168>]
(imx6dl_timer_init_dt+0x14/0x18)
 r9:efffcbc0 r8:c0e7b000 r7:c0c695c0 r6:c0d6fe18 r5:00000001 r4:ef7ebf7c
[<c0d4e154>] (imx6dl_timer_init_dt) from [<c0d4d158>]
(clocksource_probe+0x54/0xb0)
[<c0d4d104>] (clocksource_probe) from [<c0d04a2c>] (time_init+0x30/0x38)
 r7:c0e07900 r6:c0e7b000 r5:ffffffff r4:00000000
[<c0d049fc>] (time_init) from [<c0d00bc8>] (start_kernel+0x220/0x3a0)
[<c0d009a8>] (start_kernel) from [<8000807c>] (0x8000807c)
 r10:00000000 r9:410fc075 r8:8000406a r7:c0e0c958 r6:c0d5fa44 r5:c0e07918
 r4:c0e7b294


Cheers,

Tyler

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#1623350 — Re: [PATCH 4/8] ARM: dts: imx7s: Add node for GPC

On Thu, Apr 13, 2017 at 5:13 PM, Tyler Baker <tyler.baker@linaro.org> wrote:

> I've rebased this series on the next-20170413 for sanity sake, and
> realized there doesn't appear to be a way to select CONFIG_IMX_GPCV2.
> I forced it using 'default y' and configured with imx_v6_v7_defconfig.
> Now my board is booting. Before this series is applied, it may be good
> to have CONFIG_IMX_GPCV2 selected specifically for iMX7 platform,
> otherwise there will be boot regressions.

Something like this?

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index f03ef43..fe99a48 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -253,6 +253,7 @@ config RENESAS_H8S_INTC

 config IMX_GPCV2
  bool
+ def_bool y if SOC_IMX7D
  select IRQ_DOMAIN
  help
   Enables the wakeup IRQs for IMX platforms with GPCv2 block

>
> I'd encounter a backtrace with next-20170413 +  imx_v6_v7_defconfig +
> CONFIG_IMX_GPCV2=y
>
> Backtrace:
> [<c010c364>] (dump_backtrace) from [<c010c610>] (show_stack+0x18/0x1c)

but prior to fixing the Kconfig we need to fix this backtrace you reported.

Thanks

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#1623361 — Re: [PATCH 4/8] ARM: dts: imx7s: Add node for GPC

On Thu, Apr 13, 2017 at 1:49 PM, Fabio Estevam <festevam@gmail.com> wrote:
> On Thu, Apr 13, 2017 at 5:13 PM, Tyler Baker <tyler.baker@linaro.org> wrote:
>
>> I've rebased this series on the next-20170413 for sanity sake, and
>> realized there doesn't appear to be a way to select CONFIG_IMX_GPCV2.
>> I forced it using 'default y' and configured with imx_v6_v7_defconfig.
>> Now my board is booting. Before this series is applied, it may be good
>> to have CONFIG_IMX_GPCV2 selected specifically for iMX7 platform,
>> otherwise there will be boot regressions.
>
> Something like this?
>
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index f03ef43..fe99a48 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -253,6 +253,7 @@ config RENESAS_H8S_INTC
>
>  config IMX_GPCV2
>   bool
> + def_bool y if SOC_IMX7D
>   select IRQ_DOMAIN
>   help
>    Enables the wakeup IRQs for IMX platforms with GPCv2 block
>

FWIW, there's a patch for this that I haven't submitted yet (I plan to
submit it tomorrow):

https://github.com/ndreys/linux/commit/bd2de5be5c74bb35a0b8090f473862c9298a48b3

Thanks,
Andrey Smirnov

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#1623364 — Re: [PATCH 4/8] ARM: dts: imx7s: Add node for GPC

On 13 April 2017 at 13:49, Fabio Estevam <festevam@gmail.com> wrote:
> On Thu, Apr 13, 2017 at 5:13 PM, Tyler Baker <tyler.baker@linaro.org> wrote:
>
>> I've rebased this series on the next-20170413 for sanity sake, and
>> realized there doesn't appear to be a way to select CONFIG_IMX_GPCV2.
>> I forced it using 'default y' and configured with imx_v6_v7_defconfig.
>> Now my board is booting. Before this series is applied, it may be good
>> to have CONFIG_IMX_GPCV2 selected specifically for iMX7 platform,
>> otherwise there will be boot regressions.
>
> Something like this?
>
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index f03ef43..fe99a48 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -253,6 +253,7 @@ config RENESAS_H8S_INTC
>
>  config IMX_GPCV2
>   bool
> + def_bool y if SOC_IMX7D
>   select IRQ_DOMAIN
>   help
>    Enables the wakeup IRQs for IMX platforms with GPCv2 block

Exactly. LGTM.

>> I'd encounter a backtrace with next-20170413 +  imx_v6_v7_defconfig +
>> CONFIG_IMX_GPCV2=y
>>
>> Backtrace:
>> [<c010c364>] (dump_backtrace) from [<c010c610>] (show_stack+0x18/0x1c)
>
> but prior to fixing the Kconfig we need to fix this backtrace you reported.

I dug into this a bit, and lockdep is unhappy about spin locks not
being initialized before use.

The following patch fixes the backtrace on my board. I'll submit this
patch in a moment.

From: Tyler Baker <tyler.baker@linaro.org>
Date: Thu, 13 Apr 2017 14:29:49 -0700
Subject: [PATCH] irqchip/irq-imx-gpcv2: fix spinlock initialization

Call raw_spin_lock_init() before the spinlocks are used to prevent a
lockdep splat.

Signed-off-by: Tyler Baker <tyler.baker@linaro.org>
---
 drivers/irqchip/irq-imx-gpcv2.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/irqchip/irq-imx-gpcv2.c b/drivers/irqchip/irq-imx-gpcv2.c
index e13236f..9463f35 100644
--- a/drivers/irqchip/irq-imx-gpcv2.c
+++ b/drivers/irqchip/irq-imx-gpcv2.c
@@ -230,6 +230,8 @@ static int __init imx_gpcv2_irqchip_init(struct
device_node *node,
  return -ENOMEM;
  }

+ raw_spin_lock_init(&cd->rlock);
+
  cd->gpc_base = of_iomap(node, 0);
  if (!cd->gpc_base) {
  pr_err("fsl-gpcv2: unable to map gpc registers\n");
-- 
2.9.3

Cheers,

Tyler

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#1623376 — Re: [PATCH 4/8] ARM: dts: imx7s: Add node for GPC

On Thu, Apr 13, 2017 at 6:35 PM, Tyler Baker <tyler.baker@linaro.org> wrote:

> The following patch fixes the backtrace on my board. I'll submit this
> patch in a moment.
>
> From: Tyler Baker <tyler.baker@linaro.org>
> Date: Thu, 13 Apr 2017 14:29:49 -0700
> Subject: [PATCH] irqchip/irq-imx-gpcv2: fix spinlock initialization
>
> Call raw_spin_lock_init() before the spinlocks are used to prevent a
> lockdep splat.
>
> Signed-off-by: Tyler Baker <tyler.baker@linaro.org>

Yes, it makes sense:

Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

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#1623288 — Re: [PATCH 4/8] ARM: dts: imx7s: Add node for GPC

On Thu, Apr 13, 2017 at 4:03 PM, Tyler Baker <tyler.baker@linaro.org> wrote:

> I've been testing your GPC/PCIe patch sets against v4.11-rc5 on my
> imx7d-cl-som-imx7, but hit a bit of a wall. When gpc is set as the
> interrupt-parent for the soc, the kernel seems to hang and not produce
> any output on the serial port[0]. I tried to enable earlyprintk, but
> no luck getting a trace. Reversing this change, gets the board
> booting[1], but obviously isn't using the gpc which is needed for PCIe
> support as I understand it. I assume you've tested these changes on a
> imx7d-sdb and are not seeing a similar issue? You can find the patches
> I've picked on top of v4.11-rc5 here[2], any idea what might be the
> issue?

Thanks for the report.

It seems this series depends on the drivers/soc/imx/gpcv2.c patches
that landed into linux-next.

In this case, it would be better to re-send this series after
4.12-rc11 is out to avoid the breakage.

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#1623362 — Re: [PATCH 4/8] ARM: dts: imx7s: Add node for GPC

On Thu, Apr 13, 2017 at 12:03 PM, Tyler Baker <tyler.baker@linaro.org> wrote:
> Hi Andrey,
>
> On 13 April 2017 at 06:32, Andrey Smirnov <andrew.smirnov@gmail.com> wrote:
>> Add node for GPC and specify as a parent interrupt controller for SoC bus.
>>
>> Cc: yurovsky@gmail.com
>> Cc: Sascha Hauer <kernel@pengutronix.de>
>> Cc: Fabio Estevam <fabio.estevam@nxp.com>
>> Cc: Rob Herring <robh+dt@kernel.org>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Cc: Russell King <linux@armlinux.org.uk>
>> Cc: devicetree@vger.kernel.org
>> Cc: linux-kernel@vger.kernel.org
>> Cc: linux-arm-kernel@lists.infradead.org
>> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
>> ---
>>  arch/arm/boot/dts/imx7s.dtsi | 27 ++++++++++++++++++++++++++-
>>  1 file changed, 26 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
>> index 8fee299..1a7058f 100644
>> --- a/arch/arm/boot/dts/imx7s.dtsi
>> +++ b/arch/arm/boot/dts/imx7s.dtsi
>> @@ -42,6 +42,7 @@
>>   */
>>[0
>>  #include <dt-bindings/clock/imx7d-clock.h>
>> +#include <dt-bindings/power/imx7-power.h>
>>  #include <dt-bindings/gpio/gpio.h>
>>  #include <dt-bindings/input/input.h>
>>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>> @@ -119,7 +120,7 @@
>>                 #address-cells = <1>;
>>                 #size-cells = <1>;
>>                 compatible = "simple-bus";
>> -               interrupt-parent = <&intc>;
>> +               interrupt-parent = <&gpc>;
>
> I've been testing your GPC/PCIe patch sets against v4.11-rc5 on my
> imx7d-cl-som-imx7, but hit a bit of a wall. When gpc is set as the
> interrupt-parent for the soc, the kernel seems to hang and not produce
> any output on the serial port[0]. I tried to enable earlyprintk, but
> no luck getting a trace. Reversing this change, gets the board
> booting[1], but obviously isn't using the gpc which is needed for PCIe
> support as I understand it. I assume you've tested these changes on a
> imx7d-sdb and are not seeing a similar issue? You can find the patches
> I've picked on top of v4.11-rc5 here[2], any idea what might be the
> issue?

Hmm, this is something new and I don't think I've seen it(neither that
nor the backtrace from your following e-mail). Here's the kernel tree
as I've been testing it:

https://github.com/ndreys/linux/commits/imx7d/pcie-support-v8

note, however, that it is based on d0ec4e6 (tip of pci/next when I was
rebasing) of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git,
which is not exactly v4.11-rc5

I'll rebase on top v4.11-r5 and see if I can get the same backtrace
you are getting and see if I can fix it.

Thanks and sorry for breaking things for you,
Andrey Smirnov

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#1623495 — Re: [PATCH 4/8] ARM: dts: imx7s: Add node for GPC

On Thu, Apr 13, 2017 at 06:32:38AM -0700, Andrey Smirnov wrote:
> Add node for GPC and specify as a parent interrupt controller for SoC bus.
> 
> Cc: yurovsky@gmail.com
> Cc: Sascha Hauer <kernel@pengutronix.de>
> Cc: Fabio Estevam <fabio.estevam@nxp.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Russell King <linux@armlinux.org.uk>
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> ---
>  arch/arm/boot/dts/imx7s.dtsi | 27 ++++++++++++++++++++++++++-
>  1 file changed, 26 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
> index 8fee299..1a7058f 100644
> --- a/arch/arm/boot/dts/imx7s.dtsi
> +++ b/arch/arm/boot/dts/imx7s.dtsi
> @@ -42,6 +42,7 @@
>   */
>  
>  #include <dt-bindings/clock/imx7d-clock.h>
> +#include <dt-bindings/power/imx7-power.h>
>  #include <dt-bindings/gpio/gpio.h>
>  #include <dt-bindings/input/input.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -119,7 +120,7 @@
>  		#address-cells = <1>;
>  		#size-cells = <1>;
>  		compatible = "simple-bus";
> -		interrupt-parent = <&intc>;
> +		interrupt-parent = <&gpc>;
>  		ranges;
>  
>  		funnel@30041000 {
> @@ -301,6 +302,7 @@
>  			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>  			#interrupt-cells = <3>;
>  			interrupt-controller;
> +			interrupt-parent = <&intc>;
>  			reg = <0x31001000 0x1000>,
>  			      <0x31002000 0x2000>,
>  			      <0x31004000 0x2000>,
> @@ -309,6 +311,7 @@
>  
>  		timer {
>  			compatible = "arm,armv7-timer";
> +			interrupt-parent = <&intc>;
>  			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>  				     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>  				     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> @@ -564,6 +567,28 @@
>  				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
>  				#reset-cells = <1>;
>  			};
> +
> +			gpc: gpc@303a0000 {
> +				compatible = "fsl,imx7d-gpc";
> +				reg = <0x303a0000 0x10000>;
> +				interrupt-controller;
> +				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> +				#interrupt-cells = <3>;
> +				interrupt-parent = <&intc>;
> +				#power-domain-cells = <1>;
> +
> +				pgc {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					pgc_pcie_phy: pgc-pcie-phy-domain {

The node name should be something generic and has a unit-address when
there is a 'reg' property in the node.

> +						#power-domain-cells = <0>;
> +

Drop this newline.

Shawn

> +						reg = <IMX7_POWER_DOMAIN_PCIE_PHY>;
> +						power-supply = <&reg_1p0d>;
> +					};
> +				};
> +			};
>  		};
>  
>  		aips2: aips-bus@30400000 {
> -- 
> 2.9.3
> 

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#1623718 — Re: [PATCH 4/8] ARM: dts: imx7s: Add node for GPC

On Thu, Apr 13, 2017 at 8:40 PM, Shawn Guo <shawnguo@kernel.org> wrote:
> On Thu, Apr 13, 2017 at 06:32:38AM -0700, Andrey Smirnov wrote:
>> Add node for GPC and specify as a parent interrupt controller for SoC bus.
>>
>> Cc: yurovsky@gmail.com
>> Cc: Sascha Hauer <kernel@pengutronix.de>
>> Cc: Fabio Estevam <fabio.estevam@nxp.com>
>> Cc: Rob Herring <robh+dt@kernel.org>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Cc: Russell King <linux@armlinux.org.uk>
>> Cc: devicetree@vger.kernel.org
>> Cc: linux-kernel@vger.kernel.org
>> Cc: linux-arm-kernel@lists.infradead.org
>> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
>> ---
>>  arch/arm/boot/dts/imx7s.dtsi | 27 ++++++++++++++++++++++++++-
>>  1 file changed, 26 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
>> index 8fee299..1a7058f 100644
>> --- a/arch/arm/boot/dts/imx7s.dtsi
>> +++ b/arch/arm/boot/dts/imx7s.dtsi
>> @@ -42,6 +42,7 @@
>>   */
>>
>>  #include <dt-bindings/clock/imx7d-clock.h>
>> +#include <dt-bindings/power/imx7-power.h>
>>  #include <dt-bindings/gpio/gpio.h>
>>  #include <dt-bindings/input/input.h>
>>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>> @@ -119,7 +120,7 @@
>>               #address-cells = <1>;
>>               #size-cells = <1>;
>>               compatible = "simple-bus";
>> -             interrupt-parent = <&intc>;
>> +             interrupt-parent = <&gpc>;
>>               ranges;
>>
>>               funnel@30041000 {
>> @@ -301,6 +302,7 @@
>>                       interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>>                       #interrupt-cells = <3>;
>>                       interrupt-controller;
>> +                     interrupt-parent = <&intc>;
>>                       reg = <0x31001000 0x1000>,
>>                             <0x31002000 0x2000>,
>>                             <0x31004000 0x2000>,
>> @@ -309,6 +311,7 @@
>>
>>               timer {
>>                       compatible = "arm,armv7-timer";
>> +                     interrupt-parent = <&intc>;
>>                       interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>>                                    <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>>                                    <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> @@ -564,6 +567,28 @@
>>                               interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
>>                               #reset-cells = <1>;
>>                       };
>> +
>> +                     gpc: gpc@303a0000 {
>> +                             compatible = "fsl,imx7d-gpc";
>> +                             reg = <0x303a0000 0x10000>;
>> +                             interrupt-controller;
>> +                             interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
>> +                             #interrupt-cells = <3>;
>> +                             interrupt-parent = <&intc>;
>> +                             #power-domain-cells = <1>;
>> +
>> +                             pgc {
>> +                                     #address-cells = <1>;
>> +                                     #size-cells = <0>;
>> +
>> +                                     pgc_pcie_phy: pgc-pcie-phy-domain {
>
> The node name should be something generic and has a unit-address when
> there is a 'reg' property in the node.
>

I'll change it to pgc-power-domain@0, let me know if you want
something different.

>> +                                             #power-domain-cells = <0>;
>> +
>
> Drop this newline.
>

OK. Will do in v2.

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#1623747 — Re: [PATCH 4/8] ARM: dts: imx7s: Add node for GPC

On Fri, Apr 14, 2017 at 08:19:44AM -0700, Andrey Smirnov wrote:
...
> >> +                     gpc: gpc@303a0000 {
> >> +                             compatible = "fsl,imx7d-gpc";
> >> +                             reg = <0x303a0000 0x10000>;
> >> +                             interrupt-controller;
> >> +                             interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> >> +                             #interrupt-cells = <3>;
> >> +                             interrupt-parent = <&intc>;
> >> +                             #power-domain-cells = <1>;
> >> +
> >> +                             pgc {
> >> +                                     #address-cells = <1>;
> >> +                                     #size-cells = <0>;
> >> +
> >> +                                     pgc_pcie_phy: pgc-pcie-phy-domain {
> >
> > The node name should be something generic and has a unit-address when
> > there is a 'reg' property in the node.
> >
> 
> I'll change it to pgc-power-domain@0, let me know if you want
> something different.
> 

I think just power-domain@0 is ok.
And also better replace unit-address by macro.

Regards
Dong Aisheng

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#1623748 — Re: [PATCH 4/8] ARM: dts: imx7s: Add node for GPC

On Fri, Apr 14, 2017 at 8:49 AM, Dong Aisheng <dongas86@gmail.com> wrote:
> On Fri, Apr 14, 2017 at 08:19:44AM -0700, Andrey Smirnov wrote:
> ...
>> >> +                     gpc: gpc@303a0000 {
>> >> +                             compatible = "fsl,imx7d-gpc";
>> >> +                             reg = <0x303a0000 0x10000>;
>> >> +                             interrupt-controller;
>> >> +                             interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
>> >> +                             #interrupt-cells = <3>;
>> >> +                             interrupt-parent = <&intc>;
>> >> +                             #power-domain-cells = <1>;
>> >> +
>> >> +                             pgc {
>> >> +                                     #address-cells = <1>;
>> >> +                                     #size-cells = <0>;
>> >> +
>> >> +                                     pgc_pcie_phy: pgc-pcie-phy-domain {
>> >
>> > The node name should be something generic and has a unit-address when
>> > there is a 'reg' property in the node.
>> >
>>
>> I'll change it to pgc-power-domain@0, let me know if you want
>> something different.
>>
>
> I think just power-domain@0 is ok.

Fair enough. I'll do that.

> And also better replace unit-address by macro.
>

Good point. Will do.

Thanks,
Andrey Smirnov

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#1623027 — [PATCH 3/8] ARM: dts: imx7s: Adjust anatop-enable-bit for 'reg_1p0d'

In PMU_REG_1P0Dn ENABLE_LINREG is bit 0. Bit 31 is called OVERRIDE and
it serves the function of granting permission to GPC IP block to alter
various bit-fields of the register. The reason why this property, that
trickeld here from Freescale BSP, is set to 31 is because in the code
it came from it is used in conjunction with a notifier handler for
REGULATOR_EVENT_PRE_DO_ENABLE and REGULATOR_EVENT_PRE_DO_DISABLE
events (not found in upstream kernel) that triggers GPC to start
manipulating aforementioned other bitfields.

Since:
	a) none of the aforementioned machinery is implemented by
	   upstream
	b) using 'anatop-enable-bit' in that capacity is a bit of a
	   semantic stretch

simplify the situation by setting the value of 'anatop-enable-bit' to
point to ENABLE_LINREG (same as i.MX6).

Cc: yurovsky@gmail.com
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/boot/dts/imx7s.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index 22c9788..8fee299 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -516,7 +516,7 @@
 					anatop-min-bit-val = <8>;
 					anatop-min-voltage = <800000>;
 					anatop-max-voltage = <1200000>;
-					anatop-enable-bit = <31>;
+					anatop-enable-bit = <0>;
 				};
 			};
 
-- 
2.9.3

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#1623490 — Re: [PATCH 3/8] ARM: dts: imx7s: Adjust anatop-enable-bit for 'reg_1p0d'

On Thu, Apr 13, 2017 at 06:32:37AM -0700, Andrey Smirnov wrote:
> In PMU_REG_1P0Dn ENABLE_LINREG is bit 0. Bit 31 is called OVERRIDE and
> it serves the function of granting permission to GPC IP block to alter
> various bit-fields of the register. The reason why this property, that
> trickeld here from Freescale BSP, is set to 31 is because in the code
> it came from it is used in conjunction with a notifier handler for
> REGULATOR_EVENT_PRE_DO_ENABLE and REGULATOR_EVENT_PRE_DO_DISABLE
> events (not found in upstream kernel) that triggers GPC to start
> manipulating aforementioned other bitfields.
> 
> Since:
> 	a) none of the aforementioned machinery is implemented by
> 	   upstream
> 	b) using 'anatop-enable-bit' in that capacity is a bit of a
> 	   semantic stretch
> 
> simplify the situation by setting the value of 'anatop-enable-bit' to
> point to ENABLE_LINREG (same as i.MX6).
> 
> Cc: yurovsky@gmail.com
> Cc: Sascha Hauer <kernel@pengutronix.de>
> Cc: Fabio Estevam <fabio.estevam@nxp.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Russell King <linux@armlinux.org.uk>
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>

Since patch 1 ~ 3 are all about adding anatop-enable-bit, can we squash
them into one patch?

Shawn

> ---
>  arch/arm/boot/dts/imx7s.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
> index 22c9788..8fee299 100644
> --- a/arch/arm/boot/dts/imx7s.dtsi
> +++ b/arch/arm/boot/dts/imx7s.dtsi
> @@ -516,7 +516,7 @@
>  					anatop-min-bit-val = <8>;
>  					anatop-min-voltage = <800000>;
>  					anatop-max-voltage = <1200000>;
> -					anatop-enable-bit = <31>;
> +					anatop-enable-bit = <0>;
>  				};
>  			};
>  
> -- 
> 2.9.3
> 

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#1623699 — Re: [PATCH 3/8] ARM: dts: imx7s: Adjust anatop-enable-bit for 'reg_1p0d'

On Thu, Apr 13, 2017 at 8:28 PM, Shawn Guo <shawnguo@kernel.org> wrote:
> On Thu, Apr 13, 2017 at 06:32:37AM -0700, Andrey Smirnov wrote:
>> In PMU_REG_1P0Dn ENABLE_LINREG is bit 0. Bit 31 is called OVERRIDE and
>> it serves the function of granting permission to GPC IP block to alter
>> various bit-fields of the register. The reason why this property, that
>> trickeld here from Freescale BSP, is set to 31 is because in the code
>> it came from it is used in conjunction with a notifier handler for
>> REGULATOR_EVENT_PRE_DO_ENABLE and REGULATOR_EVENT_PRE_DO_DISABLE
>> events (not found in upstream kernel) that triggers GPC to start
>> manipulating aforementioned other bitfields.
>>
>> Since:
>>       a) none of the aforementioned machinery is implemented by
>>          upstream
>>       b) using 'anatop-enable-bit' in that capacity is a bit of a
>>          semantic stretch
>>
>> simplify the situation by setting the value of 'anatop-enable-bit' to
>> point to ENABLE_LINREG (same as i.MX6).
>>
>> Cc: yurovsky@gmail.com
>> Cc: Sascha Hauer <kernel@pengutronix.de>
>> Cc: Fabio Estevam <fabio.estevam@nxp.com>
>> Cc: Rob Herring <robh+dt@kernel.org>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Cc: Russell King <linux@armlinux.org.uk>
>> Cc: devicetree@vger.kernel.org
>> Cc: linux-kernel@vger.kernel.org
>> Cc: linux-arm-kernel@lists.infradead.org
>> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
>
> Since patch 1 ~ 3 are all about adding anatop-enable-bit, can we squash
> them into one patch?

OK. Will do in v2.

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