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[PATCH 2/5] clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3

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  [PATCH 2/5] clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3 Icenowy Zheng <icenowy@aosc.io> - 2017-04-08 21:00 +0200
    Re: [linux-sunxi] [PATCH 2/5] clk: sunxi-ng: allow set parent clock  (PLL_CPUX) for CPUX clock on H3 Chen-Yu Tsai <wens@csie.org> - 2017-04-09 03:10 +0200

#1619363 — [PATCH 2/5] clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3

The CPUX clock, which is the main clock of the ARM core on Allwinner H3,
can be adjusted by changing the frequency of the PLL_CPUX clock.

Allowing setting parent clock for the CPUX clock, thus the PLL_CPUX
clock can be adjusted when adjusting the CPUX clock.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index 4cbc1b701b7c..90b4e26a70bc 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -135,7 +135,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
 static const char * const cpux_parents[] = { "osc32k", "osc24M",
 					     "pll-cpux" , "pll-cpux" };
 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
-		     0x050, 16, 2, CLK_IS_CRITICAL);
+		     0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
 
 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
 
-- 
2.12.2

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#1619412 — Re: [linux-sunxi] [PATCH 2/5] clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3

Hi,

On Sun, Apr 9, 2017 at 2:50 AM, Icenowy Zheng <icenowy@aosc.io> wrote:

The subject can just say "set CLK_SET_RATE_PARENT for CPUX clock on H3".

> The CPUX clock, which is the main clock of the ARM core on Allwinner H3,
> can be adjusted by changing the frequency of the PLL_CPUX clock.
>
> Allowing setting parent clock for the CPUX clock, thus the PLL_CPUX
> clock can be adjusted when adjusting the CPUX clock.
>

This paragraph needs some work, particularly the verbs you chose. In the
clk subsystem "setting parent clock" actually refers to re-parenting.

From include/linux/clk-provider.h:

#define CLK_SET_RATE_PARENT     BIT(2) /* propagate rate change up one level */

So what you want to say is to propagate rate changes to CPUX up one
level, so PLL_CPUX gets changed as well.

The precise wording could be something like:

    The CPUX clock is the clock source for the ARM cores on the H3 SoC.
    It is a mux clock fed by, amongst other fixed clock sources, the
    configurable PLL_CPUX.

    Set CLK_SET_RATE_PARENT on the CPUX clock, so rate changes to it
    are propagated up one level to the PLL_CPUX clock.

ChenYu

> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
>  drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
> index 4cbc1b701b7c..90b4e26a70bc 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
> @@ -135,7 +135,7 @@ static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
>  static const char * const cpux_parents[] = { "osc32k", "osc24M",
>                                              "pll-cpux" , "pll-cpux" };
>  static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
> -                    0x050, 16, 2, CLK_IS_CRITICAL);
> +                    0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
>
>  static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
>
> --
> 2.12.2
>
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