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Re: [PATCH] Revert "arm64: Increase the max granular size"

Started byImran Khan <kimran@codeaurora.org>
First post2017-04-06 09:30 +0200
Last post2017-04-07 11:00 +0200
Articles 4 — 3 participants

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  Re: [PATCH] Revert "arm64: Increase the max granular size" Imran Khan <kimran@codeaurora.org> - 2017-04-06 09:30 +0200
    Re: [PATCH] Revert "arm64: Increase the max granular size" Catalin Marinas <catalin.marinas@arm.com> - 2017-04-06 18:00 +0200
      Re: [PATCH] Revert "arm64: Increase the max granular size" Ganesh Mahendran <opensource.ganesh@gmail.com> - 2017-04-07 04:10 +0200
        Re: [PATCH] Revert "arm64: Increase the max granular size" Catalin Marinas <catalin.marinas@arm.com> - 2017-04-07 11:00 +0200

#1617564 — Re: [PATCH] Revert "arm64: Increase the max granular size"

FromImran Khan <kimran@codeaurora.org>
Date2017-04-06 09:30 +0200
SubjectRe: [PATCH] Revert "arm64: Increase the max granular size"
Message-ID<tta1I-5sD-21@gated-at.bofh.it>
On 4/5/2017 10:13 AM, Imran Khan wrote:
Hi Catalin,

> Hi Catalin,
> 
>> From: Catalin Marinas <catalin.marinas@arm.com>
>> Date: Mon, Mar 21, 2016 at 10:44 PM
>> Subject: Re: [PATCH] Revert "arm64: Increase the max granular size"
>> To: "Chalamarla, Tirumalesh" <Tirumalesh.Chalamarla@caviumnetworks.com>
>> Cc: Ganesh Mahendran <opensource.ganesh@gmail.com>, "will.deacon@arm.com" <
>> will.deacon@arm.com>, "linux-arm-kernel@lists.infradead.org" <
>> linux-arm-kernel@lists.infradead.org>, "linux-kernel@vger.kernel.org" <
>>> , "stable@vger.kernel.org" <
>> stable@vger.kernel.org>
>>
>>
>> On Fri, Mar 18, 2016 at 09:05:37PM +0000, Chalamarla, Tirumalesh wrote:
>>> On 3/16/16, 2:32 AM, "linux-arm-kernel on behalf of Ganesh Mahendran" <
>> linux-arm-kernel-bounces@lists.infradead.org on behalf of
>> opensource.ganesh@gmail.com> wrote:
>>>> Reverts commit 97303480753e ("arm64: Increase the max granular size").
>>>>
>>>> The commit 97303480753e ("arm64: Increase the max granular size") will
>>>> degrade system performente in some cpus.
>>>>
>>>> We test wifi network throughput with iperf on Qualcomm msm8996 CPU:
>>>> ----------------
>>>> run on host:
>>>>  # iperf -s
>>>> run on device:
>>>>  # iperf -c <device-ip-addr> -t 100 -i 1
>>>> ----------------
>>>>
>>>> Test result:
>>>> ----------------
>>>> with commit 97303480753e ("arm64: Increase the max granular size"):
>>>>    172MBits/sec
>>>>
>>>> without commit 97303480753e ("arm64: Increase the max granular size"):
>>>>    230MBits/sec
>>>> ----------------
>>>>
>>>> Some module like slab/net will use the L1_CACHE_SHIFT, so if we do not
>>>> set the parameter correctly, it may affect the system performance.
>>>>
>>>> So revert the commit.
>>>
>>> Is there any explanation why is this so? May be there is an
>>> alternative to this, apart from reverting the commit.
>>
>> I agree we need an explanation but in the meantime, this patch has
>> caused a regression on certain systems.
>>
>>> Until now it seems L1_CACHE_SHIFT is the max of supported chips. But
>>> now we are making it 64byte, is there any reason why not 32.
>>
>> We may have to revisit this logic and consider L1_CACHE_BYTES the
>> _minimum_ of cache line sizes in arm64 systems supported by the kernel.
>> Do you have any benchmarks on Cavium boards that would show significant
>> degradation with 64-byte L1_CACHE_BYTES vs 128?
>>
>> For non-coherent DMA, the simplest is to make ARCH_DMA_MINALIGN the
>> _maximum_ of the supported systems:
>>
>> diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h
>> index 5082b30bc2c0..4b5d7b27edaf 100644
>> --- a/arch/arm64/include/asm/cache.h
>> +++ b/arch/arm64/include/asm/cache.h
>> @@ -18,17 +18,17 @@
>>
>>  #include <asm/cachetype.h>
>>
>> -#define L1_CACHE_SHIFT         7
>> +#define L1_CACHE_SHIFT         6
>>  #define L1_CACHE_BYTES         (1 << L1_CACHE_SHIFT)
>>
>>  /*
>>   * Memory returned by kmalloc() may be used for DMA, so we must make
>> - * sure that all such allocations are cache aligned. Otherwise,
>> - * unrelated code may cause parts of the buffer to be read into the
>> - * cache before the transfer is done, causing old data to be seen by
>> - * the CPU.
>> + * sure that all such allocations are aligned to the maximum *known*
>> + * cache line size on ARMv8 systems. Otherwise, unrelated code may cause
>> + * parts of the buffer to be read into the cache before the transfer is
>> + * done, causing old data to be seen by the CPU.
>>   */
>> -#define ARCH_DMA_MINALIGN      L1_CACHE_BYTES
>> +#define ARCH_DMA_MINALIGN      (128)
>>
>>  #ifndef __ASSEMBLY__
>>
>> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
>> index 392c67eb9fa6..30bafca1aebf 100644
>> --- a/arch/arm64/kernel/cpufeature.c
>> +++ b/arch/arm64/kernel/cpufeature.c
>> @@ -976,9 +976,9 @@ void __init setup_cpu_features(void)
>>         if (!cwg)
>>                 pr_warn("No Cache Writeback Granule information, assuming
>> cache line size %d\n",
>>                         cls);
>> -       if (L1_CACHE_BYTES < cls)
>> -               pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback
>> Granule (%d < %d)\n",
>> -                       L1_CACHE_BYTES, cls);
>> +       if (ARCH_DMA_MINALIGN < cls)
>> +               pr_warn("ARCH_DMA_MINALIGN smaller than the Cache Writeback
>> Granule (%d < %d)\n",
>> +                       ARCH_DMA_MINALIGN, cls);
>>  }
>>
>>  static bool __maybe_unused
>>
>>
>>
> 
> This change was discussed at: [1] but was not concluded as apparently no one
> came back with test report and numbers. After including this change in our 
> local kernel we are seeing significant throughput improvement. For example with:
> 
> iperf -c 192.168.1.181 -i 1 -w 128K -t 60
> 
> The average throughput is improving by about 30% (230Mbps from 180Mbps).
> Could you please let us know if this change can be included in upstream kernel.
> 
> [1]: https://groups.google.com/forum/#!topic/linux.kernel/P40yDB90ePs
> 

Could you please provide some feedback about the above mentioned query ?


> Thanks and Regards,
> Imran
> 
> 
> 
> 


-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a\nmember of the Code Aurora Forum, hosted by The Linux Foundation

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#1618131

FromCatalin Marinas <catalin.marinas@arm.com>
Date2017-04-06 18:00 +0200
Message-ID<tthZh-2Gn-21@gated-at.bofh.it>
In reply to#1617564
On Thu, Apr 06, 2017 at 12:52:13PM +0530, Imran Khan wrote:
> On 4/5/2017 10:13 AM, Imran Khan wrote:
> >> We may have to revisit this logic and consider L1_CACHE_BYTES the
> >> _minimum_ of cache line sizes in arm64 systems supported by the kernel.
> >> Do you have any benchmarks on Cavium boards that would show significant
> >> degradation with 64-byte L1_CACHE_BYTES vs 128?
> >>
> >> For non-coherent DMA, the simplest is to make ARCH_DMA_MINALIGN the
> >> _maximum_ of the supported systems:
> >>
> >> diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h
> >> index 5082b30bc2c0..4b5d7b27edaf 100644
> >> --- a/arch/arm64/include/asm/cache.h
> >> +++ b/arch/arm64/include/asm/cache.h
> >> @@ -18,17 +18,17 @@
> >>
> >>  #include <asm/cachetype.h>
> >>
> >> -#define L1_CACHE_SHIFT         7
> >> +#define L1_CACHE_SHIFT         6
> >>  #define L1_CACHE_BYTES         (1 << L1_CACHE_SHIFT)
> >>
> >>  /*
> >>   * Memory returned by kmalloc() may be used for DMA, so we must make
> >> - * sure that all such allocations are cache aligned. Otherwise,
> >> - * unrelated code may cause parts of the buffer to be read into the
> >> - * cache before the transfer is done, causing old data to be seen by
> >> - * the CPU.
> >> + * sure that all such allocations are aligned to the maximum *known*
> >> + * cache line size on ARMv8 systems. Otherwise, unrelated code may cause
> >> + * parts of the buffer to be read into the cache before the transfer is
> >> + * done, causing old data to be seen by the CPU.
> >>   */
> >> -#define ARCH_DMA_MINALIGN      L1_CACHE_BYTES
> >> +#define ARCH_DMA_MINALIGN      (128)
> >>
> >>  #ifndef __ASSEMBLY__
> >>
> >> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> >> index 392c67eb9fa6..30bafca1aebf 100644
> >> --- a/arch/arm64/kernel/cpufeature.c
> >> +++ b/arch/arm64/kernel/cpufeature.c
> >> @@ -976,9 +976,9 @@ void __init setup_cpu_features(void)
> >>         if (!cwg)
> >>                 pr_warn("No Cache Writeback Granule information, assuming
> >> cache line size %d\n",
> >>                         cls);
> >> -       if (L1_CACHE_BYTES < cls)
> >> -               pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
> >> -                       L1_CACHE_BYTES, cls);
> >> +       if (ARCH_DMA_MINALIGN < cls)
> >> +               pr_warn("ARCH_DMA_MINALIGN smaller than the Cache Writeback Granule (%d < %d)\n",
> >> +                       ARCH_DMA_MINALIGN, cls);
> >>  }
> >>
> >>  static bool __maybe_unused
> > 
> > This change was discussed at: [1] but was not concluded as apparently no one
> > came back with test report and numbers. After including this change in our 
> > local kernel we are seeing significant throughput improvement. For example with:
> > 
> > iperf -c 192.168.1.181 -i 1 -w 128K -t 60
> > 
> > The average throughput is improving by about 30% (230Mbps from 180Mbps).
> > Could you please let us know if this change can be included in upstream kernel.
> > 
> > [1]: https://groups.google.com/forum/#!topic/linux.kernel/P40yDB90ePs
> 
> Could you please provide some feedback about the above mentioned query ?

Do you have an explanation on the performance variation when
L1_CACHE_BYTES is changed? We'd need to understand how the network stack
is affected by L1_CACHE_BYTES, in which context it uses it (is it for
non-coherent DMA?).

The Cavium guys haven't shown any numbers (IIUC) to back the
L1_CACHE_BYTES performance improvement but I would not revert the
original commit since ARCH_DMA_MINALIGN definitely needs to cover the
maximum available cache line size, which is 128 for them.

-- 
Catalin

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#1618446

FromGanesh Mahendran <opensource.ganesh@gmail.com>
Date2017-04-07 04:10 +0200
Message-ID<ttrvA-NV-7@gated-at.bofh.it>
In reply to#1618131
2017-04-06 23:58 GMT+08:00 Catalin Marinas <catalin.marinas@arm.com>:
> On Thu, Apr 06, 2017 at 12:52:13PM +0530, Imran Khan wrote:
>> On 4/5/2017 10:13 AM, Imran Khan wrote:
>> >> We may have to revisit this logic and consider L1_CACHE_BYTES the
>> >> _minimum_ of cache line sizes in arm64 systems supported by the kernel.
>> >> Do you have any benchmarks on Cavium boards that would show significant
>> >> degradation with 64-byte L1_CACHE_BYTES vs 128?
>> >>
>> >> For non-coherent DMA, the simplest is to make ARCH_DMA_MINALIGN the
>> >> _maximum_ of the supported systems:
>> >>
>> >> diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h
>> >> index 5082b30bc2c0..4b5d7b27edaf 100644
>> >> --- a/arch/arm64/include/asm/cache.h
>> >> +++ b/arch/arm64/include/asm/cache.h
>> >> @@ -18,17 +18,17 @@
>> >>
>> >>  #include <asm/cachetype.h>
>> >>
>> >> -#define L1_CACHE_SHIFT         7
>> >> +#define L1_CACHE_SHIFT         6
>> >>  #define L1_CACHE_BYTES         (1 << L1_CACHE_SHIFT)
>> >>
>> >>  /*
>> >>   * Memory returned by kmalloc() may be used for DMA, so we must make
>> >> - * sure that all such allocations are cache aligned. Otherwise,
>> >> - * unrelated code may cause parts of the buffer to be read into the
>> >> - * cache before the transfer is done, causing old data to be seen by
>> >> - * the CPU.
>> >> + * sure that all such allocations are aligned to the maximum *known*
>> >> + * cache line size on ARMv8 systems. Otherwise, unrelated code may cause
>> >> + * parts of the buffer to be read into the cache before the transfer is
>> >> + * done, causing old data to be seen by the CPU.
>> >>   */
>> >> -#define ARCH_DMA_MINALIGN      L1_CACHE_BYTES
>> >> +#define ARCH_DMA_MINALIGN      (128)
>> >>
>> >>  #ifndef __ASSEMBLY__
>> >>
>> >> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
>> >> index 392c67eb9fa6..30bafca1aebf 100644
>> >> --- a/arch/arm64/kernel/cpufeature.c
>> >> +++ b/arch/arm64/kernel/cpufeature.c
>> >> @@ -976,9 +976,9 @@ void __init setup_cpu_features(void)
>> >>         if (!cwg)
>> >>                 pr_warn("No Cache Writeback Granule information, assuming
>> >> cache line size %d\n",
>> >>                         cls);
>> >> -       if (L1_CACHE_BYTES < cls)
>> >> -               pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
>> >> -                       L1_CACHE_BYTES, cls);
>> >> +       if (ARCH_DMA_MINALIGN < cls)
>> >> +               pr_warn("ARCH_DMA_MINALIGN smaller than the Cache Writeback Granule (%d < %d)\n",
>> >> +                       ARCH_DMA_MINALIGN, cls);
>> >>  }
>> >>
>> >>  static bool __maybe_unused
>> >
>> > This change was discussed at: [1] but was not concluded as apparently no one
>> > came back with test report and numbers. After including this change in our
>> > local kernel we are seeing significant throughput improvement. For example with:
>> >
>> > iperf -c 192.168.1.181 -i 1 -w 128K -t 60
>> >
>> > The average throughput is improving by about 30% (230Mbps from 180Mbps).
>> > Could you please let us know if this change can be included in upstream kernel.
>> >
>> > [1]: https://groups.google.com/forum/#!topic/linux.kernel/P40yDB90ePs
>>
>> Could you please provide some feedback about the above mentioned query ?
>
> Do you have an explanation on the performance variation when
> L1_CACHE_BYTES is changed? We'd need to understand how the network stack
> is affected by L1_CACHE_BYTES, in which context it uses it (is it for
> non-coherent DMA?).

network stack use SKB_DATA_ALIGN to align.
---
#define SKB_DATA_ALIGN(X) (((X) + (SMP_CACHE_BYTES - 1)) & \
~(SMP_CACHE_BYTES - 1))

#define SMP_CACHE_BYTES L1_CACHE_BYTES
---
I think this is the reason of performance regression.

>
> The Cavium guys haven't shown any numbers (IIUC) to back the
> L1_CACHE_BYTES performance improvement but I would not revert the
> original commit since ARCH_DMA_MINALIGN definitely needs to cover the
> maximum available cache line size, which is 128 for them.

how about define L1_CACHE_SHIFT like below:
---
#ifdef CONFIG_ARM64_L1_CACHE_SHIFT
#define L1_CACHE_SHIFT CONFIG_ARM64_L1_CACHE_SHIFT
#else
#define L1_CACHE_SHIFT 7
endif
---

Thanks

>
> --
> Catalin

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#1618608

FromCatalin Marinas <catalin.marinas@arm.com>
Date2017-04-07 11:00 +0200
Message-ID<ttxUl-4RH-1@gated-at.bofh.it>
In reply to#1618446
On Fri, Apr 07, 2017 at 10:06:31AM +0800, Ganesh Mahendran wrote:
> 2017-04-06 23:58 GMT+08:00 Catalin Marinas <catalin.marinas@arm.com>:
> > On Thu, Apr 06, 2017 at 12:52:13PM +0530, Imran Khan wrote:
> >> On 4/5/2017 10:13 AM, Imran Khan wrote:
> >> >> We may have to revisit this logic and consider L1_CACHE_BYTES the
> >> >> _minimum_ of cache line sizes in arm64 systems supported by the kernel.
> >> >> Do you have any benchmarks on Cavium boards that would show significant
> >> >> degradation with 64-byte L1_CACHE_BYTES vs 128?
> >> >>
> >> >> For non-coherent DMA, the simplest is to make ARCH_DMA_MINALIGN the
> >> >> _maximum_ of the supported systems:
> >> >>
> >> >> diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h
> >> >> index 5082b30bc2c0..4b5d7b27edaf 100644
> >> >> --- a/arch/arm64/include/asm/cache.h
> >> >> +++ b/arch/arm64/include/asm/cache.h
> >> >> @@ -18,17 +18,17 @@
> >> >>
> >> >>  #include <asm/cachetype.h>
> >> >>
> >> >> -#define L1_CACHE_SHIFT         7
> >> >> +#define L1_CACHE_SHIFT         6
> >> >>  #define L1_CACHE_BYTES         (1 << L1_CACHE_SHIFT)
> >> >>
> >> >>  /*
> >> >>   * Memory returned by kmalloc() may be used for DMA, so we must make
> >> >> - * sure that all such allocations are cache aligned. Otherwise,
> >> >> - * unrelated code may cause parts of the buffer to be read into the
> >> >> - * cache before the transfer is done, causing old data to be seen by
> >> >> - * the CPU.
> >> >> + * sure that all such allocations are aligned to the maximum *known*
> >> >> + * cache line size on ARMv8 systems. Otherwise, unrelated code may cause
> >> >> + * parts of the buffer to be read into the cache before the transfer is
> >> >> + * done, causing old data to be seen by the CPU.
> >> >>   */
> >> >> -#define ARCH_DMA_MINALIGN      L1_CACHE_BYTES
> >> >> +#define ARCH_DMA_MINALIGN      (128)
> >> >>
> >> >>  #ifndef __ASSEMBLY__
> >> >>
> >> >> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> >> >> index 392c67eb9fa6..30bafca1aebf 100644
> >> >> --- a/arch/arm64/kernel/cpufeature.c
> >> >> +++ b/arch/arm64/kernel/cpufeature.c
> >> >> @@ -976,9 +976,9 @@ void __init setup_cpu_features(void)
> >> >>         if (!cwg)
> >> >>                 pr_warn("No Cache Writeback Granule information, assuming
> >> >> cache line size %d\n",
> >> >>                         cls);
> >> >> -       if (L1_CACHE_BYTES < cls)
> >> >> -               pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
> >> >> -                       L1_CACHE_BYTES, cls);
> >> >> +       if (ARCH_DMA_MINALIGN < cls)
> >> >> +               pr_warn("ARCH_DMA_MINALIGN smaller than the Cache Writeback Granule (%d < %d)\n",
> >> >> +                       ARCH_DMA_MINALIGN, cls);
> >> >>  }
> >> >>
> >> >>  static bool __maybe_unused
> >> >
> >> > This change was discussed at: [1] but was not concluded as apparently no one
> >> > came back with test report and numbers. After including this change in our
> >> > local kernel we are seeing significant throughput improvement. For example with:
> >> >
> >> > iperf -c 192.168.1.181 -i 1 -w 128K -t 60
> >> >
> >> > The average throughput is improving by about 30% (230Mbps from 180Mbps).
> >> > Could you please let us know if this change can be included in upstream kernel.
> >> >
> >> > [1]: https://groups.google.com/forum/#!topic/linux.kernel/P40yDB90ePs
> >>
> >> Could you please provide some feedback about the above mentioned query ?
> >
> > Do you have an explanation on the performance variation when
> > L1_CACHE_BYTES is changed? We'd need to understand how the network stack
> > is affected by L1_CACHE_BYTES, in which context it uses it (is it for
> > non-coherent DMA?).
> 
> network stack use SKB_DATA_ALIGN to align.
> ---
> #define SKB_DATA_ALIGN(X) (((X) + (SMP_CACHE_BYTES - 1)) & \
> ~(SMP_CACHE_BYTES - 1))
> 
> #define SMP_CACHE_BYTES L1_CACHE_BYTES
> ---
> I think this is the reason of performance regression.

And is this alignment required for DMA coherency? (I hope not since
SMP_CACHE_BYTES doesn't give this).

Anyway, to be sure, it's worth changing SKB_DATA_ALIGN to use 64 bytes
(hard-coded) and check the results again.

> > The Cavium guys haven't shown any numbers (IIUC) to back the
> > L1_CACHE_BYTES performance improvement but I would not revert the
> > original commit since ARCH_DMA_MINALIGN definitely needs to cover the
> > maximum available cache line size, which is 128 for them.
> 
> how about define L1_CACHE_SHIFT like below:
> ---
> #ifdef CONFIG_ARM64_L1_CACHE_SHIFT
> #define L1_CACHE_SHIFT CONFIG_ARM64_L1_CACHE_SHIFT
> #else
> #define L1_CACHE_SHIFT 7
> endif
> ---

I'd very much like to avoid this, still aiming for a single kernel
image.

My suggestion is to check whether L1_CACHE_BYTES is wrongly used for DMA
buffer alignment in the network code and, if not, move it back to 64
bytes while keeping ARCH_DMA_MINALIGN to 128 (as per my patch above). If
the performance on the Cavium system is affected by the L1_CACHE_BYTES
change, further patches would need to be backed by some numbers.

-- 
Catalin

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