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Groups > linux.kernel > #1618084 > unrolled thread

[PATCH V2 0/4] pwm: tegra: Pin configuration in suspend/resume and cleanups

Started byLaxman Dewangan <ldewangan@nvidia.com>
First post2017-04-06 16:50 +0200
Last post2017-04-06 18:30 +0200
Articles 4 — 2 participants

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  [PATCH V2 0/4] pwm: tegra: Pin configuration in suspend/resume and cleanups Laxman Dewangan <ldewangan@nvidia.com> - 2017-04-06 16:50 +0200
    [PATCH V2 2/4] pwm: tegra: Increase precision in pwm rate calculation Laxman Dewangan <ldewangan@nvidia.com> - 2017-04-06 16:50 +0200
      Re: [PATCH V2 2/4] pwm: tegra: Increase precision in pwm rate  calculation Thierry Reding <thierry.reding@gmail.com> - 2017-04-06 18:30 +0200
      Re: [PATCH V2 2/4] pwm: tegra: Increase precision in pwm rate  calculation Thierry Reding <thierry.reding@gmail.com> - 2017-04-06 18:30 +0200

#1618084 — [PATCH V2 0/4] pwm: tegra: Pin configuration in suspend/resume and cleanups

FromLaxman Dewangan <ldewangan@nvidia.com>
Date2017-04-06 16:50 +0200
Subject[PATCH V2 0/4] pwm: tegra: Pin configuration in suspend/resume and cleanups
Message-ID<ttgTv-1Cx-3@gated-at.bofh.it>
This patch series have following fixes:
- Add more precession in PWM period register value calculation
  for lower pwm frequency.
- Add support to configure PWM pins in different state in the
  suspend/resume.

Changes from v1:
- Use standard pinctrl names for sleep and active state.
- Use API pinctrl_pm_select_*()

Laxman Dewangan (4):
  pwm: tegra: Use DIV_ROUND_CLOSEST_ULL() instead of local
    implementation
  pwm: tegra: Increase precision in pwm rate calculation
  pwm: tegra: Add DT binding details to configure pin in suspends/resume
  pwm: tegra: Add support to configure pin state in suspends/resume

 .../devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 43 ++++++++++++
 drivers/pwm/pwm-tegra.c                            | 77 ++++++++++++++++++++--
 2 files changed, 116 insertions(+), 4 deletions(-)

-- 
2.1.4

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#1618090 — [PATCH V2 2/4] pwm: tegra: Increase precision in pwm rate calculation

FromLaxman Dewangan <ldewangan@nvidia.com>
Date2017-04-06 16:50 +0200
Subject[PATCH V2 2/4] pwm: tegra: Increase precision in pwm rate calculation
Message-ID<ttgTw-1Cx-37@gated-at.bofh.it>
In reply to#1618084
The rate of the PWM calculated as follows:
	hz = NSEC_PER_SEC / period_ns;
 	rate = (rate + (hz / 2)) / hz;

This has the precision loss in lower PWM rate.
Changing this to have more precision as:
	hz = DIV_ROUND_CLOSE(NSEC_PER_SEC * 100, period_ns);
	rate = DIV_ROUND_CLOSE(rate * 100, hz)

Example:
1. period_ns = 16672000, PWM clock rate is 200KHz.
	Based on old formula
		hz = NSEC_PER_SEC / period_ns
		   = 1000000000ul/16672000
		   = 59 (59.98)
		rate = (200K + 59/2)/59 = 3390

	Based on new method:
		hz = 5998
		rate = DIV_ROUND_CLOSE(200000*100, 5998) = 3334

	If we measure the PWM signal rate, we will get more accurate period
	with rate value of 3334 instead of 3390.

2.  period_ns = 16803898, PWM clock rate is 200KHz.
	Based on old formula:
		hz = 60, rate = 3333
	Based on new formula:
		hz = 5951, rate = 3360

	The rate of 3360 is more near to requested period then the 3333.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
Changes from V1:
- None

 drivers/pwm/pwm-tegra.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
index 0a688da..e9c4de5 100644
--- a/drivers/pwm/pwm-tegra.c
+++ b/drivers/pwm/pwm-tegra.c
@@ -76,6 +76,8 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
 	unsigned long long c = duty_ns;
 	unsigned long rate, hz;
+	unsigned long long ns100 = NSEC_PER_SEC;
+	unsigned long precision = 100; /* Consider 2 digit precision */
 	u32 val = 0;
 	int err;
 
@@ -94,9 +96,11 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
 	 * cycles at the PWM clock rate will take period_ns nanoseconds.
 	 */
 	rate = clk_get_rate(pc->clk) >> PWM_DUTY_WIDTH;
-	hz = NSEC_PER_SEC / period_ns;
 
-	rate = (rate + (hz / 2)) / hz;
+	/* Consider precision in PWM_SCALE_WIDTH rate calculation */
+	ns100 *= precision;
+	hz = DIV_ROUND_CLOSEST_ULL(ns100, period_ns);
+	rate = DIV_ROUND_CLOSEST(rate * precision, hz);
 
 	/*
 	 * Since the actual PWM divider is the register's frequency divider
-- 
2.1.4

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#1618163 — Re: [PATCH V2 2/4] pwm: tegra: Increase precision in pwm rate calculation

FromThierry Reding <thierry.reding@gmail.com>
Date2017-04-06 18:30 +0200
SubjectRe: [PATCH V2 2/4] pwm: tegra: Increase precision in pwm rate calculation
Message-ID<ttisi-3fg-11@gated-at.bofh.it>
In reply to#1618090

[Multipart message — attachments visible in raw view] — view raw

On Thu, Apr 06, 2017 at 07:50:59PM +0530, Laxman Dewangan wrote:
> The rate of the PWM calculated as follows:
> 	hz = NSEC_PER_SEC / period_ns;
>  	rate = (rate + (hz / 2)) / hz;
> 
> This has the precision loss in lower PWM rate.
> Changing this to have more precision as:
> 	hz = DIV_ROUND_CLOSE(NSEC_PER_SEC * 100, period_ns);
> 	rate = DIV_ROUND_CLOSE(rate * 100, hz)

DIV_ROUND_CLOSEST(). And I much prefer this to the actual code below. I
don't think it's necessary to have a local variable for the precision.

Thierry

> Example:
> 1. period_ns = 16672000, PWM clock rate is 200KHz.
> 	Based on old formula
> 		hz = NSEC_PER_SEC / period_ns
> 		   = 1000000000ul/16672000
> 		   = 59 (59.98)
> 		rate = (200K + 59/2)/59 = 3390
> 
> 	Based on new method:
> 		hz = 5998
> 		rate = DIV_ROUND_CLOSE(200000*100, 5998) = 3334
> 
> 	If we measure the PWM signal rate, we will get more accurate period
> 	with rate value of 3334 instead of 3390.
> 
> 2.  period_ns = 16803898, PWM clock rate is 200KHz.
> 	Based on old formula:
> 		hz = 60, rate = 3333
> 	Based on new formula:
> 		hz = 5951, rate = 3360
> 
> 	The rate of 3360 is more near to requested period then the 3333.
> 
> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
> ---
> Changes from V1:
> - None
> 
>  drivers/pwm/pwm-tegra.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
> index 0a688da..e9c4de5 100644
> --- a/drivers/pwm/pwm-tegra.c
> +++ b/drivers/pwm/pwm-tegra.c
> @@ -76,6 +76,8 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
>  	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
>  	unsigned long long c = duty_ns;
>  	unsigned long rate, hz;
> +	unsigned long long ns100 = NSEC_PER_SEC;
> +	unsigned long precision = 100; /* Consider 2 digit precision */
>  	u32 val = 0;
>  	int err;
>  
> @@ -94,9 +96,11 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
>  	 * cycles at the PWM clock rate will take period_ns nanoseconds.
>  	 */
>  	rate = clk_get_rate(pc->clk) >> PWM_DUTY_WIDTH;
> -	hz = NSEC_PER_SEC / period_ns;
>  
> -	rate = (rate + (hz / 2)) / hz;
> +	/* Consider precision in PWM_SCALE_WIDTH rate calculation */
> +	ns100 *= precision;
> +	hz = DIV_ROUND_CLOSEST_ULL(ns100, period_ns);
> +	rate = DIV_ROUND_CLOSEST(rate * precision, hz);
>  
>  	/*
>  	 * Since the actual PWM divider is the register's frequency divider
> -- 
> 2.1.4
>

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#1618164 — Re: [PATCH V2 2/4] pwm: tegra: Increase precision in pwm rate calculation

FromThierry Reding <thierry.reding@gmail.com>
Date2017-04-06 18:30 +0200
SubjectRe: [PATCH V2 2/4] pwm: tegra: Increase precision in pwm rate calculation
Message-ID<ttisi-3fg-19@gated-at.bofh.it>
In reply to#1618090

[Multipart message — attachments visible in raw view] — view raw

On Thu, Apr 06, 2017 at 07:50:59PM +0530, Laxman Dewangan wrote:
> The rate of the PWM calculated as follows:
> 	hz = NSEC_PER_SEC / period_ns;
>  	rate = (rate + (hz / 2)) / hz;
> 
> This has the precision loss in lower PWM rate.
> Changing this to have more precision as:
> 	hz = DIV_ROUND_CLOSE(NSEC_PER_SEC * 100, period_ns);
> 	rate = DIV_ROUND_CLOSE(rate * 100, hz)

DIV_ROUND_CLOSEST(). Also I very much prefer this notation over the
actual code below. I don't think we need a local variable to hold the
precision.

Thierry

> Example:
> 1. period_ns = 16672000, PWM clock rate is 200KHz.
> 	Based on old formula
> 		hz = NSEC_PER_SEC / period_ns
> 		   = 1000000000ul/16672000
> 		   = 59 (59.98)
> 		rate = (200K + 59/2)/59 = 3390
> 
> 	Based on new method:
> 		hz = 5998
> 		rate = DIV_ROUND_CLOSE(200000*100, 5998) = 3334
> 
> 	If we measure the PWM signal rate, we will get more accurate period
> 	with rate value of 3334 instead of 3390.
> 
> 2.  period_ns = 16803898, PWM clock rate is 200KHz.
> 	Based on old formula:
> 		hz = 60, rate = 3333
> 	Based on new formula:
> 		hz = 5951, rate = 3360
> 
> 	The rate of 3360 is more near to requested period then the 3333.
> 
> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
> ---
> Changes from V1:
> - None
> 
>  drivers/pwm/pwm-tegra.c | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
> index 0a688da..e9c4de5 100644
> --- a/drivers/pwm/pwm-tegra.c
> +++ b/drivers/pwm/pwm-tegra.c
> @@ -76,6 +76,8 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
>  	struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
>  	unsigned long long c = duty_ns;
>  	unsigned long rate, hz;
> +	unsigned long long ns100 = NSEC_PER_SEC;
> +	unsigned long precision = 100; /* Consider 2 digit precision */
>  	u32 val = 0;
>  	int err;
>  
> @@ -94,9 +96,11 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
>  	 * cycles at the PWM clock rate will take period_ns nanoseconds.
>  	 */
>  	rate = clk_get_rate(pc->clk) >> PWM_DUTY_WIDTH;
> -	hz = NSEC_PER_SEC / period_ns;
>  
> -	rate = (rate + (hz / 2)) / hz;
> +	/* Consider precision in PWM_SCALE_WIDTH rate calculation */
> +	ns100 *= precision;
> +	hz = DIV_ROUND_CLOSEST_ULL(ns100, period_ns);
> +	rate = DIV_ROUND_CLOSEST(rate * precision, hz);
>  
>  	/*
>  	 * Since the actual PWM divider is the register's frequency divider
> -- 
> 2.1.4
>

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