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[PATCH V8 0/4] phy: USB and PCIe phy drivers for Qcom chipsets

Started byVivek Gautam <vivek.gautam@codeaurora.org>
First post2017-04-06 08:00 +0200
Last post2017-04-06 14:20 +0200
Articles 5 — 2 participants

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  [PATCH V8 0/4] phy: USB and PCIe phy drivers for Qcom chipsets Vivek Gautam <vivek.gautam@codeaurora.org> - 2017-04-06 08:00 +0200
    [PATCH V8 1/4] dt-bindings: phy: Add support for QUSB2 phy Vivek Gautam <vivek.gautam@codeaurora.org> - 2017-04-06 08:00 +0200
    [PATCH V8 3/4] dt-bindings: phy: Add support for QMP phy Vivek Gautam <vivek.gautam@codeaurora.org> - 2017-04-06 08:00 +0200
    Re: [PATCH V8 0/4] phy: USB and PCIe phy drivers for Qcom chipsets Kishon Vijay Abraham I <kishon@ti.com> - 2017-04-06 12:20 +0200
      Re: [PATCH V8 0/4] phy: USB and PCIe phy drivers for Qcom chipsets Vivek Gautam <vivek.gautam@codeaurora.org> - 2017-04-06 14:20 +0200

#1617516 — [PATCH V8 0/4] phy: USB and PCIe phy drivers for Qcom chipsets

FromVivek Gautam <vivek.gautam@codeaurora.org>
Date2017-04-06 08:00 +0200
Subject[PATCH V8 0/4] phy: USB and PCIe phy drivers for Qcom chipsets
Message-ID<tt8CB-4qU-3@gated-at.bofh.it>
Hi Kishon,
Here's the series with fixed checkpatch warnings/checks.
Please pick it for phy/next.

This patch series adds couple of PHY drivers for Qualcomm chipsets.
a) qcom-qusb2 phy driver: that provides High Speed USB functionality.
b) qcom-qmp phy driver: that is a combo phy providing support for
   USB3, PCIe, UFS and few other controllers.

The patches are based on next branch of linux-phy tree.

These patches have been tested on Dragon board db820c hardware with
required set of dt patches.
The tested branch[3] is based on torvald's master with greg's usb/usb-next
merged. Additionally the patches to get rpm up on msm8996 are also pulled
in.

Changes since v7:
 - Fixed 'checkpatch --strict' alignment warnings/checks, and
   added Stephen's Reviewed-by tag.

Changes since v6:
 - Rebased on phy/next and *not* including phy grouping series[4].
 - qusb2-phy: addressed Stephen's comment.
   - Dropped pm8994_s2 corner regulator from QUSB2 phy bindings.
 - qmp-phy: none on functionality side.
 
Changes since v5:
 - Addressed review comments from Bjorn:
   - Removed instances of readl/wirtel_relaxed calls from the drivers.
     Instead, using simple readl/writel. Inserting a readl after a writel
     to ensure the write is through to the device.
   - Replaced regulator handling with regulator_bulk_** apis. This helps
     in cutting down a lot of regulator handling code.
   - Fixed minor return statements.

Changes since v4:
 - Addressed comment to add child nodes for qmp phy driver. Each phy lane
   now has a separate child node under the main qmp node.
 - Modified the clock and reset initialization and enable methods.
   Different phys - pcie, usb and later ufs, have varying number of clocks
   and resets that are mandatory. So adding provision for clocks and reset
   lists helps in requesting all mandatory resources for individual phys
   and handle their failure cases accordingly.

Changes since v3:
 - Addressed review comments given by Rob and Stephen for qusb2 phy
   and qmp phy bindings respectively.
 - Addressed review comments given by Stephen and Bjorn for qmp phy driver.

Changes since v2:
 - Addressed review comments given by Rob and Stephen for bindings.
 - Addressed the review comments given by Stephen for the qusb2 and qmp
   phy drivers.

Changes since v1:
 - Moved device tree binding documentation to separate patches, as suggested
   by Rob.
 - Addressed review comment regarding qfprom accesses by qusb2 phy driver,
   given by Rob.
 - Addressed review comments from Kishon.
 - Addressed review comments from Srinivas for QMP phy driver.
 - Addressed kbuild warning.

Please see individual patches for detailed changelogs.

[1] https://patchwork.kernel.org/patch/9567767/
[2] https://patchwork.kernel.org/patch/9567779/
[3] https://github.com/vivekgautam1/linux/tree/linux-v4.11-rc5-qmp-phy-db820c
[4] https://lkml.org/lkml/2017/3/20/407

Vivek Gautam (4):
  dt-bindings: phy: Add support for QUSB2 phy
  phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips
  dt-bindings: phy: Add support for QMP phy
  phy: qcom-qmp: new qmp phy driver for qcom-chipsets

 .../devicetree/bindings/phy/qcom-qmp-phy.txt       |  106 ++
 .../devicetree/bindings/phy/qcom-qusb2-phy.txt     |   43 +
 drivers/phy/Kconfig                                |   18 +
 drivers/phy/Makefile                               |    2 +
 drivers/phy/phy-qcom-qmp.c                         | 1153 ++++++++++++++++++++
 drivers/phy/phy-qcom-qusb2.c                       |  493 +++++++++
 6 files changed, 1815 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
 create mode 100644 Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
 create mode 100644 drivers/phy/phy-qcom-qmp.c
 create mode 100644 drivers/phy/phy-qcom-qusb2.c

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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#1617517 — [PATCH V8 1/4] dt-bindings: phy: Add support for QUSB2 phy

FromVivek Gautam <vivek.gautam@codeaurora.org>
Date2017-04-06 08:00 +0200
Subject[PATCH V8 1/4] dt-bindings: phy: Add support for QUSB2 phy
Message-ID<tt8CC-4qU-9@gated-at.bofh.it>
In reply to#1617516
Qualcomm chipsets have QUSB2 phy controller that provides
HighSpeed functionality for DWC3 controller.
Adding dt binding information for the same.

Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
---

Changes since v7:
 - None, just added Stephen's Reviewed-by tag.

Changes since v6:
 - Dropped 'vdd-phy-supply' that used pm8994_s2 regulator, from bindings.
   As Stephen said, the pm8994_s2 is a 'corner' regulator and it shouldn't
   be right to put it as a regulator supply.
   Work is in progress to handle these sort of power supplies.

Changes since v5:
 - Removed leading 0 from the address in 'reg' property.

Changes since v4:
 - None.

Changes since v3:
 - Added 'Acked-by' from Rob.
 - Removed 'reset-names' and 'nvmem-cell-names' from the bindings
   since we use only one cell.

Changes since v2:
 - Removed binding for "ref_clk_src" since we don't request this
   clock in the driver.
 - Addressed s/vdda-phy-dpdm/vdda-phy-dpdm-supply.
 - Addressed s/ref_clk/ref. Don't need to add '_clk' suffix to clock names.
 - Addressed s/tune2_hstx_trim_efuse/tune2_hstx_trim. Don't need to add
   'efuse' suffix to nvmem cell.
 - Addressed s/qusb2phy/phy for the node name.

Changes since v1:
 - New patch, forked out of the original driver patch:
   "phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips"
 - Updated dt bindings to remove 'hstx-trim-bit-offset' and
   'hstx-trim-bit-len' bindings.

 .../devicetree/bindings/phy/qcom-qusb2-phy.txt     | 43 ++++++++++++++++++++++
 1 file changed, 43 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt

diff --git a/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
new file mode 100644
index 000000000000..aa0fcb05acb3
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
@@ -0,0 +1,43 @@
+Qualcomm QUSB2 phy controller
+=============================
+
+QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
+
+Required properties:
+ - compatible: compatible list, contains "qcom,msm8996-qusb2-phy".
+ - reg: offset and length of the PHY register set.
+ - #phy-cells: must be 0.
+
+ - clocks: a list of phandles and clock-specifier pairs,
+	   one for each entry in clock-names.
+ - clock-names: must be "cfg_ahb" for phy config clock,
+			"ref" for 19.2 MHz ref clk,
+			"iface" for phy interface clock (Optional).
+
+ - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
+ - vdda-phy-dpdm-supply: Phandle to 3.1V regulator supply to Dp/Dm port signals.
+
+ - resets: Phandle to reset to phy block.
+
+Optional properties:
+ - nvmem-cells: Phandle to nvmem cell that contains 'HS Tx trim'
+		tuning parameter value for qusb2 phy.
+
+ - qcom,tcsr-syscon: Phandle to TCSR syscon register region.
+
+Example:
+	hsusb_phy: phy@7411000 {
+		compatible = "qcom,msm8996-qusb2-phy";
+		reg = <0x7411000 0x180>;
+		#phy-cells = <0>;
+
+		clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+			<&gcc GCC_RX1_USB2_CLKREF_CLK>,
+		clock-names = "cfg_ahb", "ref";
+
+		vdda-pll-supply = <&pm8994_l12>;
+		vdda-phy-dpdm-supply = <&pm8994_l24>;
+
+		resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+		nvmem-cells = <&qusb2p_hstx_trim>;
+        };
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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#1617518 — [PATCH V8 3/4] dt-bindings: phy: Add support for QMP phy

FromVivek Gautam <vivek.gautam@codeaurora.org>
Date2017-04-06 08:00 +0200
Subject[PATCH V8 3/4] dt-bindings: phy: Add support for QMP phy
Message-ID<tt8CC-4qU-15@gated-at.bofh.it>
In reply to#1617516
Qualcomm chipsets have QMP phy controller that provides
support to a number of controller, viz. PCIe, UFS, and USB.
Adding dt binding information for the same.

Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
---

Changes since v7:
 - None, just added Stephen's Reviewed-by tag.

Changes since v6:
 - none.

Changes since v5:
 - Added Rob's 'Ack' for the new child nodes based bindings.
 - Dropped leading 0 from the address in 'reg' property.
 - Fixed '@xyz' part of the node name with correct address.

Changes since v4:
 - Added bindings for child nodes. Each phy lane is represented by child
   node with its own register space (for tx, rx and pcs blocks), and clocks
   and resets for power control facility.
 - Removed register space and lane offsets for tx, rx and pcs blocks from
   qmp phy node.
 - #phy-cells is now part of each child node and thus must be 0.
 - Added information on list of mandatory clocks and resets for each phy.

Changes since v3:
 - Added #clock-cells = <1>, indicating that phy is a clock provider.

Changes since v2:
 - Removed binding for "ref_clk_src" since we don't request this
   clock in the driver.
 - Addressed s/ref_clk/ref. Don't need to add '_clk' suffix to clock names.
 - Using 'phy' for the node name.

Changes since v1:
 - New patch, forked out of the original driver patch:
   "phy: qcom-qmp: new qmp phy driver for qcom-chipsets"
 - Added 'Acked-by' from Rob.
 - Updated bindings to include mem resource as a list of
   offset - length pair for serdes block and for each lane.
 - Added a new binding for 'lane-offsets' that contains offsets
   to tx, rx and pcs blocks from each lane base address.

 .../devicetree/bindings/phy/qcom-qmp-phy.txt       | 106 +++++++++++++++++++++
 1 file changed, 106 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt

diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
new file mode 100644
index 000000000000..e11c563a65ec
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
@@ -0,0 +1,106 @@
+Qualcomm QMP PHY controller
+===========================
+
+QMP phy controller supports physical layer functionality for a number of
+controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
+
+Required properties:
+ - compatible: compatible list, contains:
+	       "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
+	       "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996.
+
+ - reg: offset and length of register set for PHY's common serdes block.
+
+ - #clock-cells: must be 1
+    - Phy pll outputs a bunch of clocks for Tx, Rx and Pipe
+      interface (for pipe based PHYs). These clock are then gate-controlled
+      by gcc.
+ - #address-cells: must be 1
+ - #size-cells: must be 1
+ - ranges: must be present
+
+ - clocks: a list of phandles and clock-specifier pairs,
+	   one for each entry in clock-names.
+ - clock-names: "cfg_ahb" for phy config clock,
+		"aux" for phy aux clock,
+		"ref" for 19.2 MHz ref clk,
+		For "qcom,msm8996-qmp-pcie-phy" must contain:
+			"aux", "cfg_ahb", "ref".
+		For "qcom,msm8996-qmp-usb3-phy" must contain:
+			"aux", "cfg_ahb", "ref".
+
+ - resets: a list of phandles and reset controller specifier pairs,
+	   one for each entry in reset-names.
+ - reset-names: "phy" for reset of phy block,
+		"common" for phy common block reset,
+		"cfg" for phy's ahb cfg block reset (Optional).
+		For "qcom,msm8996-qmp-pcie-phy" must contain:
+		 "phy", "common", "cfg".
+		For "qcom,msm8996-qmp-usb3-phy" must contain
+		 "phy", "common".
+
+ - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
+ - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
+
+Optional properties:
+ - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk
+			pll block.
+
+Required nodes:
+ - Each device node of QMP phy is required to have as many child nodes as
+   the number of lanes the PHY has.
+
+Required properties for child node:
+ - reg: list of offset and length pairs of register sets for PHY blocks -
+	tx, rx and pcs.
+
+ - #phy-cells: must be 0
+
+ - clocks: a list of phandles and clock-specifier pairs,
+	   one for each entry in clock-names.
+ - clock-names: Must contain following for pcie and usb qmp phys:
+		 "pipe<lane-number>" for pipe clock specific to each lane.
+
+ - resets: a list of phandles and reset controller specifier pairs,
+	   one for each entry in reset-names.
+ - reset-names: Must contain following for pcie qmp phys:
+		 "lane<lane-number>" for reset specific to each lane.
+
+Example:
+	phy@34000 {
+		compatible = "qcom,msm8996-qmp-pcie-phy";
+		reg = <0x34000 0x488>;
+		#clock-cells = <1>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
+			<&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
+			<&gcc GCC_PCIE_CLKREF_CLK>;
+		clock-names = "aux", "cfg_ahb", "ref";
+
+		vdda-phy-supply = <&pm8994_l28>;
+		vdda-pll-supply = <&pm8994_l12>;
+
+		resets = <&gcc GCC_PCIE_PHY_BCR>,
+			<&gcc GCC_PCIE_PHY_COM_BCR>,
+			<&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
+		reset-names = "phy", "common", "cfg";
+
+		pciephy_0: lane@35000 {
+			reg = <0x35000 0x130>,
+				<0x35200 0x200>,
+				<0x35400 0x1dc>;
+			#phy-cells = <0>;
+
+			clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
+			clock-names = "pipe0";
+			resets = <&gcc GCC_PCIE_0_PHY_BCR>;
+			reset-names = "lane0";
+		};
+
+		pciephy_1: lane@36000 {
+		...
+		...
+	};
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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#1617831

FromKishon Vijay Abraham I <kishon@ti.com>
Date2017-04-06 12:20 +0200
Message-ID<ttcGd-7cD-5@gated-at.bofh.it>
In reply to#1617516

On Thursday 06 April 2017 11:21 AM, Vivek Gautam wrote:
> Hi Kishon,
> Here's the series with fixed checkpatch warnings/checks.
> Please pick it for phy/next.
> 
> This patch series adds couple of PHY drivers for Qualcomm chipsets.
> a) qcom-qusb2 phy driver: that provides High Speed USB functionality.
> b) qcom-qmp phy driver: that is a combo phy providing support for
>    USB3, PCIe, UFS and few other controllers.
> 
> The patches are based on next branch of linux-phy tree.
> 
> These patches have been tested on Dragon board db820c hardware with
> required set of dt patches.
> The tested branch[3] is based on torvald's master with greg's usb/usb-next
> merged. Additionally the patches to get rpm up on msm8996 are also pulled
> in.

merged, thanks!

-Kishon
> 
> Changes since v7:
>  - Fixed 'checkpatch --strict' alignment warnings/checks, and
>    added Stephen's Reviewed-by tag.
> 
> Changes since v6:
>  - Rebased on phy/next and *not* including phy grouping series[4].
>  - qusb2-phy: addressed Stephen's comment.
>    - Dropped pm8994_s2 corner regulator from QUSB2 phy bindings.
>  - qmp-phy: none on functionality side.
>  
> Changes since v5:
>  - Addressed review comments from Bjorn:
>    - Removed instances of readl/wirtel_relaxed calls from the drivers.
>      Instead, using simple readl/writel. Inserting a readl after a writel
>      to ensure the write is through to the device.
>    - Replaced regulator handling with regulator_bulk_** apis. This helps
>      in cutting down a lot of regulator handling code.
>    - Fixed minor return statements.
> 
> Changes since v4:
>  - Addressed comment to add child nodes for qmp phy driver. Each phy lane
>    now has a separate child node under the main qmp node.
>  - Modified the clock and reset initialization and enable methods.
>    Different phys - pcie, usb and later ufs, have varying number of clocks
>    and resets that are mandatory. So adding provision for clocks and reset
>    lists helps in requesting all mandatory resources for individual phys
>    and handle their failure cases accordingly.
> 
> Changes since v3:
>  - Addressed review comments given by Rob and Stephen for qusb2 phy
>    and qmp phy bindings respectively.
>  - Addressed review comments given by Stephen and Bjorn for qmp phy driver.
> 
> Changes since v2:
>  - Addressed review comments given by Rob and Stephen for bindings.
>  - Addressed the review comments given by Stephen for the qusb2 and qmp
>    phy drivers.
> 
> Changes since v1:
>  - Moved device tree binding documentation to separate patches, as suggested
>    by Rob.
>  - Addressed review comment regarding qfprom accesses by qusb2 phy driver,
>    given by Rob.
>  - Addressed review comments from Kishon.
>  - Addressed review comments from Srinivas for QMP phy driver.
>  - Addressed kbuild warning.
> 
> Please see individual patches for detailed changelogs.
> 
> [1] https://patchwork.kernel.org/patch/9567767/
> [2] https://patchwork.kernel.org/patch/9567779/
> [3] https://github.com/vivekgautam1/linux/tree/linux-v4.11-rc5-qmp-phy-db820c
> [4] https://lkml.org/lkml/2017/3/20/407
> 
> Vivek Gautam (4):
>   dt-bindings: phy: Add support for QUSB2 phy
>   phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips
>   dt-bindings: phy: Add support for QMP phy
>   phy: qcom-qmp: new qmp phy driver for qcom-chipsets
> 
>  .../devicetree/bindings/phy/qcom-qmp-phy.txt       |  106 ++
>  .../devicetree/bindings/phy/qcom-qusb2-phy.txt     |   43 +
>  drivers/phy/Kconfig                                |   18 +
>  drivers/phy/Makefile                               |    2 +
>  drivers/phy/phy-qcom-qmp.c                         | 1153 ++++++++++++++++++++
>  drivers/phy/phy-qcom-qusb2.c                       |  493 +++++++++
>  6 files changed, 1815 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
>  create mode 100644 Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
>  create mode 100644 drivers/phy/phy-qcom-qmp.c
>  create mode 100644 drivers/phy/phy-qcom-qusb2.c
>

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#1617917

FromVivek Gautam <vivek.gautam@codeaurora.org>
Date2017-04-06 14:20 +0200
Message-ID<tteyl-8ob-7@gated-at.bofh.it>
In reply to#1617831

On 04/06/2017 03:41 PM, Kishon Vijay Abraham I wrote:
>
> On Thursday 06 April 2017 11:21 AM, Vivek Gautam wrote:
>> Hi Kishon,
>> Here's the series with fixed checkpatch warnings/checks.
>> Please pick it for phy/next.
>>
>> This patch series adds couple of PHY drivers for Qualcomm chipsets.
>> a) qcom-qusb2 phy driver: that provides High Speed USB functionality.
>> b) qcom-qmp phy driver: that is a combo phy providing support for
>>     USB3, PCIe, UFS and few other controllers.
>>
>> The patches are based on next branch of linux-phy tree.
>>
>> These patches have been tested on Dragon board db820c hardware with
>> required set of dt patches.
>> The tested branch[3] is based on torvald's master with greg's usb/usb-next
>> merged. Additionally the patches to get rpm up on msm8996 are also pulled
>> in.
> merged, thanks!

Thanks Kishon.

BRs
Vivek

>
> -Kishon
>> Changes since v7:
>>   - Fixed 'checkpatch --strict' alignment warnings/checks, and
>>     added Stephen's Reviewed-by tag.
>>
>> Changes since v6:
>>   - Rebased on phy/next and *not* including phy grouping series[4].
>>   - qusb2-phy: addressed Stephen's comment.
>>     - Dropped pm8994_s2 corner regulator from QUSB2 phy bindings.
>>   - qmp-phy: none on functionality side.
>>   
>> Changes since v5:
>>   - Addressed review comments from Bjorn:
>>     - Removed instances of readl/wirtel_relaxed calls from the drivers.
>>       Instead, using simple readl/writel. Inserting a readl after a writel
>>       to ensure the write is through to the device.
>>     - Replaced regulator handling with regulator_bulk_** apis. This helps
>>       in cutting down a lot of regulator handling code.
>>     - Fixed minor return statements.
>>
>> Changes since v4:
>>   - Addressed comment to add child nodes for qmp phy driver. Each phy lane
>>     now has a separate child node under the main qmp node.
>>   - Modified the clock and reset initialization and enable methods.
>>     Different phys - pcie, usb and later ufs, have varying number of clocks
>>     and resets that are mandatory. So adding provision for clocks and reset
>>     lists helps in requesting all mandatory resources for individual phys
>>     and handle their failure cases accordingly.
>>
>> Changes since v3:
>>   - Addressed review comments given by Rob and Stephen for qusb2 phy
>>     and qmp phy bindings respectively.
>>   - Addressed review comments given by Stephen and Bjorn for qmp phy driver.
>>
>> Changes since v2:
>>   - Addressed review comments given by Rob and Stephen for bindings.
>>   - Addressed the review comments given by Stephen for the qusb2 and qmp
>>     phy drivers.
>>
>> Changes since v1:
>>   - Moved device tree binding documentation to separate patches, as suggested
>>     by Rob.
>>   - Addressed review comment regarding qfprom accesses by qusb2 phy driver,
>>     given by Rob.
>>   - Addressed review comments from Kishon.
>>   - Addressed review comments from Srinivas for QMP phy driver.
>>   - Addressed kbuild warning.
>>
>> Please see individual patches for detailed changelogs.
>>
>> [1] https://patchwork.kernel.org/patch/9567767/
>> [2] https://patchwork.kernel.org/patch/9567779/
>> [3] https://github.com/vivekgautam1/linux/tree/linux-v4.11-rc5-qmp-phy-db820c
>> [4] https://lkml.org/lkml/2017/3/20/407
>>
>> Vivek Gautam (4):
>>    dt-bindings: phy: Add support for QUSB2 phy
>>    phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips
>>    dt-bindings: phy: Add support for QMP phy
>>    phy: qcom-qmp: new qmp phy driver for qcom-chipsets
>>
>>   .../devicetree/bindings/phy/qcom-qmp-phy.txt       |  106 ++
>>   .../devicetree/bindings/phy/qcom-qusb2-phy.txt     |   43 +
>>   drivers/phy/Kconfig                                |   18 +
>>   drivers/phy/Makefile                               |    2 +
>>   drivers/phy/phy-qcom-qmp.c                         | 1153 ++++++++++++++++++++
>>   drivers/phy/phy-qcom-qusb2.c                       |  493 +++++++++
>>   6 files changed, 1815 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
>>   create mode 100644 Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
>>   create mode 100644 drivers/phy/phy-qcom-qmp.c
>>   create mode 100644 drivers/phy/phy-qcom-qusb2.c
>>

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