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[PATCH v2 0/5] perf report: Show branch type

Started byJin Yao <yao.jin@linux.intel.com>
First post2017-04-07 05:00 +0200
Last post2017-04-08 10:50 +0200
Articles 8 — 4 participants

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Contents

  [PATCH v2 0/5] perf report: Show branch type Jin Yao <yao.jin@linux.intel.com> - 2017-04-07 05:00 +0200
    [PATCH v2 1/5] perf/core: Define the common branch type classification Jin Yao <yao.jin@linux.intel.com> - 2017-04-07 05:00 +0200
    [PATCH v2 2/5] perf/x86/intel: Record branch type Jin Yao <yao.jin@linux.intel.com> - 2017-04-07 05:00 +0200
      Re: [PATCH v2 2/5] perf/x86/intel: Record branch type Peter Zijlstra <peterz@infradead.org> - 2017-04-07 17:30 +0200
        Re: [PATCH v2 2/5] perf/x86/intel: Record branch type Andi Kleen <ak@linux.intel.com> - 2017-04-07 19:00 +0200
          Re: [PATCH v2 2/5] perf/x86/intel: Record branch type Peter Zijlstra <peterz@infradead.org> - 2017-04-07 19:30 +0200
            Re: [PATCH v2 2/5] perf/x86/intel: Record branch type Andi Kleen <ak@linux.intel.com> - 2017-04-07 20:00 +0200
              Re: [PATCH v2 2/5] perf/x86/intel: Record branch type "Jin, Yao" <yao.jin@linux.intel.com> - 2017-04-08 10:50 +0200

#1618454 — [PATCH v2 0/5] perf report: Show branch type

FromJin Yao <yao.jin@linux.intel.com>
Date2017-04-07 05:00 +0200
Subject[PATCH v2 0/5] perf report: Show branch type
Message-ID<ttshY-1au-3@gated-at.bofh.it>
v2:
---
1. Use 4 bits in perf_branch_entry to record branch type.

2. Pull out some common branch types from FAR_BRANCH. Now the branch
   types defined in perf_event.h:

PERF_BR_NONE      : unknown
PERF_BR_JCC_FWD   : conditional forward jump
PERF_BR_JCC_BWD   : conditional backward jump
PERF_BR_JMP       : jump
PERF_BR_IND_JMP   : indirect jump
PERF_BR_CALL      : call
PERF_BR_IND_CALL  : indirect call
PERF_BR_RET       : return
PERF_BR_SYSCALL   : syscall
PERF_BR_SYSRET    : syscall return
PERF_BR_IRQ       : hw interrupt/trap/fault
PERF_BR_INT       : sw interrupt
PERF_BR_IRET      : return from interrupt
PERF_BR_FAR_BRANCH: others not generic far branch type

3. Use 2 bits in perf_branch_entry for a "cross" metrics checking
   for branch cross 4K or 2M area. It's an approximate computing
   for checking if the branch cross 4K page or 2MB page.

For example:

perf record -g --branch-filter any,save_type <command>

perf report --stdio

     JCC forward:  27.7%
    JCC backward:   9.8%
             JMP:   0.0%
         IND_JMP:   6.5%
            CALL:  26.6%
        IND_CALL:   0.0%
             RET:  29.3%
            IRET:   0.0%
        CROSS_4K:   0.0%
        CROSS_2M:  14.3%

perf report --branch-history --stdio --no-children

    -23.60%--main div.c:42 (RET cycles:2)
             compute_flag div.c:28 (RET cycles:2)
             compute_flag div.c:27 (RET CROSS_2M cycles:1)
             rand rand.c:28 (RET CROSS_2M cycles:1)
             rand rand.c:28 (RET cycles:1)
             __random random.c:298 (RET cycles:1)
             __random random.c:297 (JCC forward cycles:1)
             __random random.c:295 (JCC forward cycles:1)
             __random random.c:295 (JCC forward cycles:1)
             __random random.c:295 (JCC forward cycles:1)
             __random random.c:295 (RET cycles:9)

Changed:
  perf/core: Define the common branch type classification
  perf/x86/intel: Record branch type
  perf report: Show branch type statistics for stdio mode
  perf report: Show branch type in callchain entry

Not changed:
  perf record: Create a new option save_type in --branch-filter

v1:
---
It is often useful to know the branch types while analyzing branch
data. For example, a call is very different from a conditional branch.

Currently we have to look it up in binary while the binary may later
not be available and even the binary is available but user has to take
some time. It is very useful for user to check it directly in perf
report.

Perf already has support for disassembling the branch instruction
to get the branch type.

The patch series records the branch type and show the branch type with
other LBR information in callchain entry via perf report. The patch
series also adds the branch type summary at the end of
perf report --stdio.

To keep consistent on kernel and userspace and make the classification
more common, the patch adds the common branch type classification
in perf_event.h.

The common branch types are:

 JCC forward: Conditional forward jump
JCC backward: Conditional backward jump
         JMP: Jump imm
     IND_JMP: Jump reg/mem
        CALL: Call imm
    IND_CALL: Call reg/mem
         RET: Ret
  FAR_BRANCH: SYSCALL/SYSRET, IRQ, IRET, TSX Abort

An example:

1. Record branch type (new option "save_type")

perf record -g --branch-filter any,save_type <command>

2. Show the branch type statistics at the end of perf report --stdio

perf report --stdio

     JCC forward:  34.0%
    JCC backward:   3.6%
             JMP:   0.0%
         IND_JMP:   6.5%
            CALL:  26.6%
        IND_CALL:   0.0%
             RET:  29.3%
      FAR_BRANCH:   0.0%

3. Show branch type in callchain entry

perf report --branch-history --stdio --no-children

    --23.91%--main div.c:42 (RET cycles:2)
              compute_flag div.c:28 (RET cycles:2)
              compute_flag div.c:27 (RET cycles:1)
              rand rand.c:28 (RET cycles:1)
              rand rand.c:28 (RET cycles:1)
              __random random.c:298 (RET cycles:1)
              __random random.c:297 (JCC forward cycles:1)
              __random random.c:295 (JCC forward cycles:1)
              __random random.c:295 (JCC forward cycles:1)
              __random random.c:295 (JCC forward cycles:1)
              __random random.c:295 (RET cycles:9)

Jin Yao (5):
  perf/core: Define the common branch type classification
  perf/x86/intel: Record branch type
  perf record: Create a new option save_type in --branch-filter
  perf report: Show branch type statistics for stdio mode
  perf report: Show branch type in callchain entry

 arch/x86/events/intel/lbr.c              | 106 ++++++++++++++-
 include/uapi/linux/perf_event.h          |  37 +++++-
 tools/include/uapi/linux/perf_event.h    |  37 +++++-
 tools/perf/Documentation/perf-record.txt |   1 +
 tools/perf/builtin-report.c              | 212 +++++++++++++++++++++++++++++
 tools/perf/util/callchain.c              | 221 ++++++++++++++++++++++---------
 tools/perf/util/callchain.h              |  20 +++
 tools/perf/util/event.h                  |   4 +-
 tools/perf/util/hist.c                   |   5 +-
 tools/perf/util/parse-branch-options.c   |   1 +
 10 files changed, 577 insertions(+), 67 deletions(-)

-- 
2.7.4

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#1618455 — [PATCH v2 1/5] perf/core: Define the common branch type classification

FromJin Yao <yao.jin@linux.intel.com>
Date2017-04-07 05:00 +0200
Subject[PATCH v2 1/5] perf/core: Define the common branch type classification
Message-ID<ttshY-1au-11@gated-at.bofh.it>
In reply to#1618454
It is often useful to know the branch types while analyzing branch
data. For example, a call is very different from a conditional branch.

Currently we have to look it up in binary while the binary may later
not be available and even the binary is available but user has to take
some time. It is very useful for user to check it directly in perf
report.

Perf already has support for disassembling the branch instruction
to get the x86 branch type.

To keep consistent on kernel and userspace and make the classification
more common, the patch adds the common branch type classification
in perf_event.h.

PERF_BR_NONE      : unknown
PERF_BR_JCC_FWD   : conditional forward jump
PERF_BR_JCC_BWD   : conditional backward jump
PERF_BR_JMP       : jump
PERF_BR_IND_JMP   : indirect jump
PERF_BR_CALL      : call
PERF_BR_IND_CALL  : indirect call
PERF_BR_RET       : return
PERF_BR_SYSCALL   : syscall
PERF_BR_SYSRET    : syscall return
PERF_BR_IRQ       : hw interrupt/trap/fault
PERF_BR_INT       : sw interrupt
PERF_BR_IRET      : return from interrupt
PERF_BR_FAR_BRANCH: others not generic branch type

The patch adds following metrics checking for branches cross
4K or 2MB areas.

PERF_BR_CROSS_NONE: branch not cross an area
PERF_BR_CROSS_4K  : branch cross 4K area
PERF_BR_CROSS_2M  : branch cross 2MB area

Since the disassembling of branch instruction needs some overhead,
a new PERF_SAMPLE_BRANCH_TYPE_SAVE is introduced to indicate if it
needs to disassemble the branch instruction and record the branch
type.

Signed-off-by: Jin Yao <yao.jin@linux.intel.com>
---
 include/uapi/linux/perf_event.h       | 37 ++++++++++++++++++++++++++++++++++-
 tools/include/uapi/linux/perf_event.h | 37 ++++++++++++++++++++++++++++++++++-
 2 files changed, 72 insertions(+), 2 deletions(-)

diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
index d09a9cd..e2fcd53 100644
--- a/include/uapi/linux/perf_event.h
+++ b/include/uapi/linux/perf_event.h
@@ -174,6 +174,8 @@ enum perf_branch_sample_type_shift {
 	PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT	= 14, /* no flags */
 	PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT	= 15, /* no cycles */
 
+	PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT	= 16, /* save branch type */
+
 	PERF_SAMPLE_BRANCH_MAX_SHIFT		/* non-ABI */
 };
 
@@ -198,9 +200,38 @@ enum perf_branch_sample_type {
 	PERF_SAMPLE_BRANCH_NO_FLAGS	= 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT,
 	PERF_SAMPLE_BRANCH_NO_CYCLES	= 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT,
 
+	PERF_SAMPLE_BRANCH_TYPE_SAVE	=
+		1U << PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT,
+
 	PERF_SAMPLE_BRANCH_MAX		= 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT,
 };
 
+/*
+ * Common flow change classification
+ */
+enum {
+	PERF_BR_NONE		= 0,	/* unknown */
+	PERF_BR_JCC_FWD		= 1,	/* conditional forward jump */
+	PERF_BR_JCC_BWD		= 2,	/* conditional backward jump */
+	PERF_BR_JMP		= 3,	/* jump */
+	PERF_BR_IND_JMP		= 4,	/* indirect jump */
+	PERF_BR_CALL		= 5,	/* call */
+	PERF_BR_IND_CALL	= 6,	/* indirect call */
+	PERF_BR_RET		= 7,	/* return */
+	PERF_BR_SYSCALL		= 8,	/* syscall */
+	PERF_BR_SYSRET		= 9,	/* syscall return */
+	PERF_BR_IRQ		= 10,	/* hw interrupt/trap/fault */
+	PERF_BR_INT		= 11,	/* sw interrupt */
+	PERF_BR_IRET		= 12,	/* return from interrupt */
+	PERF_BR_FAR_BRANCH	= 13,	/* others not generic branch type */
+};
+
+enum {
+	PERF_BR_CROSS_NONE	= 0,	/* branch not cross an area */
+	PERF_BR_CROSS_4K	= 1,	/* branch cross 4K */
+	PERF_BR_CROSS_2M	= 2,	/* branch cross 2MB */
+};
+
 #define PERF_SAMPLE_BRANCH_PLM_ALL \
 	(PERF_SAMPLE_BRANCH_USER|\
 	 PERF_SAMPLE_BRANCH_KERNEL|\
@@ -999,6 +1030,8 @@ union perf_mem_data_src {
  *     in_tx: running in a hardware transaction
  *     abort: aborting a hardware transaction
  *    cycles: cycles from last branch (or 0 if not supported)
+ *      type: branch type
+ *     cross: branch cross 4K or 2MB area
  */
 struct perf_branch_entry {
 	__u64	from;
@@ -1008,7 +1041,9 @@ struct perf_branch_entry {
 		in_tx:1,    /* in transaction */
 		abort:1,    /* transaction abort */
 		cycles:16,  /* cycle count to last branch */
-		reserved:44;
+		type:4,     /* branch type */
+		cross:2,    /* branch cross 4K or 2MB area */
+		reserved:38;
 };
 
 #endif /* _UAPI_LINUX_PERF_EVENT_H */
diff --git a/tools/include/uapi/linux/perf_event.h b/tools/include/uapi/linux/perf_event.h
index d09a9cd..e2fcd53 100644
--- a/tools/include/uapi/linux/perf_event.h
+++ b/tools/include/uapi/linux/perf_event.h
@@ -174,6 +174,8 @@ enum perf_branch_sample_type_shift {
 	PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT	= 14, /* no flags */
 	PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT	= 15, /* no cycles */
 
+	PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT	= 16, /* save branch type */
+
 	PERF_SAMPLE_BRANCH_MAX_SHIFT		/* non-ABI */
 };
 
@@ -198,9 +200,38 @@ enum perf_branch_sample_type {
 	PERF_SAMPLE_BRANCH_NO_FLAGS	= 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT,
 	PERF_SAMPLE_BRANCH_NO_CYCLES	= 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT,
 
+	PERF_SAMPLE_BRANCH_TYPE_SAVE	=
+		1U << PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT,
+
 	PERF_SAMPLE_BRANCH_MAX		= 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT,
 };
 
+/*
+ * Common flow change classification
+ */
+enum {
+	PERF_BR_NONE		= 0,	/* unknown */
+	PERF_BR_JCC_FWD		= 1,	/* conditional forward jump */
+	PERF_BR_JCC_BWD		= 2,	/* conditional backward jump */
+	PERF_BR_JMP		= 3,	/* jump */
+	PERF_BR_IND_JMP		= 4,	/* indirect jump */
+	PERF_BR_CALL		= 5,	/* call */
+	PERF_BR_IND_CALL	= 6,	/* indirect call */
+	PERF_BR_RET		= 7,	/* return */
+	PERF_BR_SYSCALL		= 8,	/* syscall */
+	PERF_BR_SYSRET		= 9,	/* syscall return */
+	PERF_BR_IRQ		= 10,	/* hw interrupt/trap/fault */
+	PERF_BR_INT		= 11,	/* sw interrupt */
+	PERF_BR_IRET		= 12,	/* return from interrupt */
+	PERF_BR_FAR_BRANCH	= 13,	/* others not generic branch type */
+};
+
+enum {
+	PERF_BR_CROSS_NONE	= 0,	/* branch not cross an area */
+	PERF_BR_CROSS_4K	= 1,	/* branch cross 4K */
+	PERF_BR_CROSS_2M	= 2,	/* branch cross 2MB */
+};
+
 #define PERF_SAMPLE_BRANCH_PLM_ALL \
 	(PERF_SAMPLE_BRANCH_USER|\
 	 PERF_SAMPLE_BRANCH_KERNEL|\
@@ -999,6 +1030,8 @@ union perf_mem_data_src {
  *     in_tx: running in a hardware transaction
  *     abort: aborting a hardware transaction
  *    cycles: cycles from last branch (or 0 if not supported)
+ *      type: branch type
+ *     cross: branch cross 4K or 2MB area
  */
 struct perf_branch_entry {
 	__u64	from;
@@ -1008,7 +1041,9 @@ struct perf_branch_entry {
 		in_tx:1,    /* in transaction */
 		abort:1,    /* transaction abort */
 		cycles:16,  /* cycle count to last branch */
-		reserved:44;
+		type:4,     /* branch type */
+		cross:2,    /* branch cross 4K or 2MB area */
+		reserved:38;
 };
 
 #endif /* _UAPI_LINUX_PERF_EVENT_H */
-- 
2.7.4

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#1618456 — [PATCH v2 2/5] perf/x86/intel: Record branch type

FromJin Yao <yao.jin@linux.intel.com>
Date2017-04-07 05:00 +0200
Subject[PATCH v2 2/5] perf/x86/intel: Record branch type
Message-ID<ttshY-1au-13@gated-at.bofh.it>
In reply to#1618454
Perf already has support for disassembling the branch instruction
and using the branch type for filtering. The patch just records
the branch type in perf_branch_entry.

Before recording, the patch converts the x86 branch classification
to common branch classification and compute for checking if the
branches cross 4K or 2MB areas. It's an approximate computing for
crossing 4K page or 2MB page.

Signed-off-by: Jin Yao <yao.jin@linux.intel.com>
---
 arch/x86/events/intel/lbr.c | 106 +++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 105 insertions(+), 1 deletion(-)

diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index 81b321a..635a0fb 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -109,6 +109,9 @@ enum {
 	X86_BR_ZERO_CALL	= 1 << 15,/* zero length call */
 	X86_BR_CALL_STACK	= 1 << 16,/* call stack */
 	X86_BR_IND_JMP		= 1 << 17,/* indirect jump */
+
+	X86_BR_TYPE_SAVE	= 1 << 18,/* indicate to save branch type */
+
 };
 
 #define X86_BR_PLM (X86_BR_USER | X86_BR_KERNEL)
@@ -139,6 +142,9 @@ enum {
 	 X86_BR_IRQ		|\
 	 X86_BR_INT)
 
+#define AREA_4K		4096
+#define AREA_2M		(2 * 1024 * 1024)
+
 static void intel_pmu_lbr_filter(struct cpu_hw_events *cpuc);
 
 /*
@@ -670,6 +676,10 @@ static int intel_pmu_setup_sw_lbr_filter(struct perf_event *event)
 
 	if (br_type & PERF_SAMPLE_BRANCH_CALL)
 		mask |= X86_BR_CALL | X86_BR_ZERO_CALL;
+
+	if (br_type & PERF_SAMPLE_BRANCH_TYPE_SAVE)
+		mask |= X86_BR_TYPE_SAVE;
+
 	/*
 	 * stash actual user request into reg, it may
 	 * be used by fixup code for some CPU
@@ -923,6 +933,84 @@ static int branch_type(unsigned long from, unsigned long to, int abort)
 	return ret;
 }
 
+static int
+common_branch_type(int type, u64 from, u64 to)
+{
+	int ret;
+
+	type = type & (~(X86_BR_KERNEL | X86_BR_USER));
+
+	switch (type) {
+	case X86_BR_CALL:
+	case X86_BR_ZERO_CALL:
+		ret = PERF_BR_CALL;
+		break;
+
+	case X86_BR_RET:
+		ret = PERF_BR_RET;
+		break;
+
+	case X86_BR_SYSCALL:
+		ret = PERF_BR_SYSCALL;
+		break;
+
+	case X86_BR_SYSRET:
+		ret = PERF_BR_SYSRET;
+		break;
+
+	case X86_BR_INT:
+		ret = PERF_BR_INT;
+		break;
+
+	case X86_BR_IRET:
+		ret = PERF_BR_IRET;
+		break;
+
+	case X86_BR_IRQ:
+		ret = PERF_BR_IRQ;
+		break;
+
+	case X86_BR_ABORT:
+		ret = PERF_BR_FAR_BRANCH;
+		break;
+
+	case X86_BR_JCC:
+		if (to > from)
+			ret = PERF_BR_JCC_FWD;
+		else
+			ret = PERF_BR_JCC_BWD;
+		break;
+
+	case X86_BR_JMP:
+		ret = PERF_BR_JMP;
+		break;
+
+	case X86_BR_IND_CALL:
+		ret = PERF_BR_IND_CALL;
+		break;
+
+	case X86_BR_IND_JMP:
+		ret = PERF_BR_IND_JMP;
+		break;
+
+	default:
+		ret = PERF_BR_NONE;
+	}
+
+	return ret;
+}
+
+static bool
+cross_area(u64 addr1, u64 addr2, int size)
+{
+	u64 align1, align2;
+
+	align1 = addr1 & ~(size - 1);
+	align2 = addr2 & ~(size - 1);
+
+	return (align1 != align2) ? true : false;
+}
+
 /*
  * implement actual branch filter based on user demand.
  * Hardware may not exactly satisfy that request, thus
@@ -939,7 +1027,8 @@ intel_pmu_lbr_filter(struct cpu_hw_events *cpuc)
 	bool compress = false;
 
 	/* if sampling all branches, then nothing to filter */
-	if ((br_sel & X86_BR_ALL) == X86_BR_ALL)
+	if (((br_sel & X86_BR_ALL) == X86_BR_ALL) &&
+	    ((br_sel & X86_BR_TYPE_SAVE) != X86_BR_TYPE_SAVE))
 		return;
 
 	for (i = 0; i < cpuc->lbr_stack.nr; i++) {
@@ -960,6 +1049,21 @@ intel_pmu_lbr_filter(struct cpu_hw_events *cpuc)
 			cpuc->lbr_entries[i].from = 0;
 			compress = true;
 		}
+
+		if ((br_sel & X86_BR_TYPE_SAVE) == X86_BR_TYPE_SAVE) {
+			cpuc->lbr_entries[i].type = common_branch_type(type,
+								       from,
+								       to);
+			if (cross_area(from, to, AREA_2M))
+				cpuc->lbr_entries[i].cross = PERF_BR_CROSS_2M;
+			else if (cross_area(from, to, AREA_4K))
+				cpuc->lbr_entries[i].cross = PERF_BR_CROSS_4K;
+			else
+				cpuc->lbr_entries[i].cross = PERF_BR_CROSS_NONE;
+		} else {
+			cpuc->lbr_entries[i].type = PERF_BR_NONE;
+			cpuc->lbr_entries[i].cross = PERF_BR_CROSS_NONE;
+		}
 	}
 
 	if (!compress)
-- 
2.7.4

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#1618904 — Re: [PATCH v2 2/5] perf/x86/intel: Record branch type

FromPeter Zijlstra <peterz@infradead.org>
Date2017-04-07 17:30 +0200
SubjectRe: [PATCH v2 2/5] perf/x86/intel: Record branch type
Message-ID<ttDZM-w1-11@gated-at.bofh.it>
In reply to#1618456
On Fri, Apr 07, 2017 at 06:47:43PM +0800, Jin Yao wrote:
> Perf already has support for disassembling the branch instruction
> and using the branch type for filtering. The patch just records
> the branch type in perf_branch_entry.
> 
> Before recording, the patch converts the x86 branch classification
> to common branch classification and compute for checking if the
> branches cross 4K or 2MB areas. It's an approximate computing for
> crossing 4K page or 2MB page.

The changelog is completely empty of rationale. Why do we care?

Not having the binary is a very bad reason; you can't do much of
anything if that's missing.


> @@ -923,6 +933,84 @@ static int branch_type(unsigned long from, unsigned long to, int abort)
>  	return ret;
>  }
>  
> +static int
> +common_branch_type(int type, u64 from, u64 to)
> +{
> +	int ret;
> +
> +	type = type & (~(X86_BR_KERNEL | X86_BR_USER));
> +
> +	switch (type) {
> +	case X86_BR_CALL:
> +	case X86_BR_ZERO_CALL:
> +		ret = PERF_BR_CALL;
> +		break;
> +
> +	case X86_BR_RET:
> +		ret = PERF_BR_RET;
> +		break;
> +
> +	case X86_BR_SYSCALL:
> +		ret = PERF_BR_SYSCALL;
> +		break;
> +
> +	case X86_BR_SYSRET:
> +		ret = PERF_BR_SYSRET;
> +		break;
> +
> +	case X86_BR_INT:
> +		ret = PERF_BR_INT;
> +		break;
> +
> +	case X86_BR_IRET:
> +		ret = PERF_BR_IRET;
> +		break;
> +
> +	case X86_BR_IRQ:
> +		ret = PERF_BR_IRQ;
> +		break;
> +
> +	case X86_BR_ABORT:
> +		ret = PERF_BR_FAR_BRANCH;
> +		break;
> +
> +	case X86_BR_JCC:
> +		if (to > from)
> +			ret = PERF_BR_JCC_FWD;
> +		else
> +			ret = PERF_BR_JCC_BWD;
> +		break;

This seems like superfluous information; we already get to and from, so
this comparison is pointless.

The rest looks like something you can simpler implement using a lookup
table.

> +
> +	case X86_BR_JMP:
> +		ret = PERF_BR_JMP;
> +		break;
> +
> +	case X86_BR_IND_CALL:
> +		ret = PERF_BR_IND_CALL;
> +		break;
> +
> +	case X86_BR_IND_JMP:
> +		ret = PERF_BR_IND_JMP;
> +		break;
> +
> +	default:
> +		ret = PERF_BR_NONE;
> +	}
> +
> +	return ret;
> +}
> +
> +static bool
> +cross_area(u64 addr1, u64 addr2, int size)
> +{
> +	u64 align1, align2;
> +
> +	align1 = addr1 & ~(size - 1);
> +	align2 = addr2 & ~(size - 1);
> +
> +	return (align1 != align2) ? true : false;
> +}
> +
>  /*
>   * implement actual branch filter based on user demand.
>   * Hardware may not exactly satisfy that request, thus
> @@ -939,7 +1027,8 @@ intel_pmu_lbr_filter(struct cpu_hw_events *cpuc)
>  	bool compress = false;
>  
>  	/* if sampling all branches, then nothing to filter */
> -	if ((br_sel & X86_BR_ALL) == X86_BR_ALL)
> +	if (((br_sel & X86_BR_ALL) == X86_BR_ALL) &&
> +	    ((br_sel & X86_BR_TYPE_SAVE) != X86_BR_TYPE_SAVE))
>  		return;
>  
>  	for (i = 0; i < cpuc->lbr_stack.nr; i++) {
> @@ -960,6 +1049,21 @@ intel_pmu_lbr_filter(struct cpu_hw_events *cpuc)
>  			cpuc->lbr_entries[i].from = 0;
>  			compress = true;
>  		}
> +
> +		if ((br_sel & X86_BR_TYPE_SAVE) == X86_BR_TYPE_SAVE) {
> +			cpuc->lbr_entries[i].type = common_branch_type(type,
> +								       from,
> +								       to);
> +			if (cross_area(from, to, AREA_2M))
> +				cpuc->lbr_entries[i].cross = PERF_BR_CROSS_2M;
> +			else if (cross_area(from, to, AREA_4K))
> +				cpuc->lbr_entries[i].cross = PERF_BR_CROSS_4K;
> +			else
> +				cpuc->lbr_entries[i].cross = PERF_BR_CROSS_NONE;

This again is superfluous information; it is already fully contained in
to and from, which we have.

> +		} else {
> +			cpuc->lbr_entries[i].type = PERF_BR_NONE;
> +			cpuc->lbr_entries[i].cross = PERF_BR_CROSS_NONE;
> +		}
>  	}
>  
>  	if (!compress)
> -- 
> 2.7.4
>

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#1618972 — Re: [PATCH v2 2/5] perf/x86/intel: Record branch type

FromAndi Kleen <ak@linux.intel.com>
Date2017-04-07 19:00 +0200
SubjectRe: [PATCH v2 2/5] perf/x86/intel: Record branch type
Message-ID<ttFoT-1r2-35@gated-at.bofh.it>
In reply to#1618904
On Fri, Apr 07, 2017 at 05:20:31PM +0200, Peter Zijlstra wrote:
> On Fri, Apr 07, 2017 at 06:47:43PM +0800, Jin Yao wrote:
> > Perf already has support for disassembling the branch instruction
> > and using the branch type for filtering. The patch just records
> > the branch type in perf_branch_entry.
> > 
> > Before recording, the patch converts the x86 branch classification
> > to common branch classification and compute for checking if the
> > branches cross 4K or 2MB areas. It's an approximate computing for
> > crossing 4K page or 2MB page.
> 
> The changelog is completely empty of rationale. Why do we care?
> 
> Not having the binary is a very bad reason; you can't do much of
> anything if that's missing.

It's a somewhat common situation with partially JITed code, if you
don't have an agent. You can still do a lot of useful things.

We found it useful to have this extra information during workload
analysis. Forward conditionals and page crossing jumps
are indications of frontend problems.

-Andi

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#1618990 — Re: [PATCH v2 2/5] perf/x86/intel: Record branch type

FromPeter Zijlstra <peterz@infradead.org>
Date2017-04-07 19:30 +0200
SubjectRe: [PATCH v2 2/5] perf/x86/intel: Record branch type
Message-ID<ttFRU-1SP-15@gated-at.bofh.it>
In reply to#1618972
On Fri, Apr 07, 2017 at 09:48:34AM -0700, Andi Kleen wrote:
> On Fri, Apr 07, 2017 at 05:20:31PM +0200, Peter Zijlstra wrote:
> > On Fri, Apr 07, 2017 at 06:47:43PM +0800, Jin Yao wrote:
> > > Perf already has support for disassembling the branch instruction
> > > and using the branch type for filtering. The patch just records
> > > the branch type in perf_branch_entry.
> > > 
> > > Before recording, the patch converts the x86 branch classification
> > > to common branch classification and compute for checking if the
> > > branches cross 4K or 2MB areas. It's an approximate computing for
> > > crossing 4K page or 2MB page.
> > 
> > The changelog is completely empty of rationale. Why do we care?
> > 
> > Not having the binary is a very bad reason; you can't do much of
> > anything if that's missing.
> 
> It's a somewhat common situation with partially JITed code, if you
> don't have an agent. You can still do a lot of useful things.

Like what? How can you say anything about code you don't have?

> We found it useful to have this extra information during workload
> analysis. Forward conditionals and page crossing jumps
> are indications of frontend problems.

But you already have the exact same information in {to,from}, why would
you need to repackage information already contained?

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#1619007 — Re: [PATCH v2 2/5] perf/x86/intel: Record branch type

FromAndi Kleen <ak@linux.intel.com>
Date2017-04-07 20:00 +0200
SubjectRe: [PATCH v2 2/5] perf/x86/intel: Record branch type
Message-ID<ttGkV-28n-1@gated-at.bofh.it>
In reply to#1618990
> > It's a somewhat common situation with partially JITed code, if you
> > don't have an agent. You can still do a lot of useful things.
> 
> Like what? How can you say anything about code you don't have?

For example if you combine the PMU topdown measurement, and see if it's
frontend bound, and then you see it has lots of forward conditionals,
then dynamic basic block reordering will help. If you have lots
of cross page jumps then function reordering will help. etc.

> > We found it useful to have this extra information during workload
> > analysis. Forward conditionals and page crossing jumps
> > are indications of frontend problems.
> 
> But you already have the exact same information in {to,from}, why would
> you need to repackage information already contained?

Without this patch, we don't know if it's conditional or something else.
And the kernel already knows this for its filtering, so it can as well
report it.

Right the CROSS_* and forward backward information could be computed
later.

-Andi

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#1619250 — Re: [PATCH v2 2/5] perf/x86/intel: Record branch type

From"Jin, Yao" <yao.jin@linux.intel.com>
Date2017-04-08 10:50 +0200
SubjectRe: [PATCH v2 2/5] perf/x86/intel: Record branch type
Message-ID<ttUee-2ZI-5@gated-at.bofh.it>
In reply to#1619007
> Without this patch, we don't know if it's conditional or something else.
> And the kernel already knows this for its filtering, so it can as well
> report it.
>
> Right the CROSS_* and forward backward information could be computed
> later.
>
> -Andi
>
>
OK, I will move CROSS_* and JCC forward/backward computing to user-space though it makes user-space code to be complicated.

Thanks
Jin Yao

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