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| Started by | Icenowy Zheng <icenowy@aosc.io> |
|---|---|
| First post | 2017-04-05 16:40 +0200 |
| Last post | 2017-04-06 09:20 +0200 |
| Articles | 2 — 2 participants |
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[PATCH 2/2] arm64: allwinner: a64: add pmu0 regs for USB PHY Icenowy Zheng <icenowy@aosc.io> - 2017-04-05 16:40 +0200
Re: [PATCH 2/2] arm64: allwinner: a64: add pmu0 regs for USB PHY Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-04-06 09:20 +0200
| From | Icenowy Zheng <icenowy@aosc.io> |
|---|---|
| Date | 2017-04-05 16:40 +0200 |
| Subject | [PATCH 2/2] arm64: allwinner: a64: add pmu0 regs for USB PHY |
| Message-ID | <tsUgi-3Nd-5@gated-at.bofh.it> |
The USB PHY in A64 has a "pmu0" region, which controls the EHCI/OHCI
controller pair that can be connected to the PHY0.
Add the MMIO region for PHY node.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 1c64ea2d23f9..0565779e66fa 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -179,8 +179,10 @@
usbphy: phy@01c19400 {
compatible = "allwinner,sun50i-a64-usb-phy";
reg = <0x01c19400 0x14>,
+ <0x01c1a800 0x4>,
<0x01c1b800 0x4>;
reg-names = "phy_ctrl",
+ "pmu0",
"pmu1";
clocks = <&ccu CLK_USB_PHY0>,
<&ccu CLK_USB_PHY1>;
--
2.12.2
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| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2017-04-06 09:20 +0200 |
| Message-ID | <tt9S1-5py-3@gated-at.bofh.it> |
| In reply to | #1616999 |
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On Wed, Apr 05, 2017 at 10:30:34PM +0800, Icenowy Zheng wrote: > The USB PHY in A64 has a "pmu0" region, which controls the EHCI/OHCI > controller pair that can be connected to the PHY0. > > Add the MMIO region for PHY node. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Applied, thanks Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com
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