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[PATCH 01/11] arm64: allwinner: a64: enable RSB on A64

Started byIcenowy Zheng <icenowy@aosc.io>
First post2017-04-04 20:10 +0200
Last post2017-04-05 05:50 +0200
Articles 2 — 2 participants

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  [PATCH 01/11] arm64: allwinner: a64: enable RSB on A64 Icenowy Zheng <icenowy@aosc.io> - 2017-04-04 20:10 +0200
    Re: [linux-sunxi] [PATCH 01/11] arm64: allwinner: a64: enable RSB on A64 Chen-Yu Tsai <wens@csie.org> - 2017-04-05 05:50 +0200

#1616278 — [PATCH 01/11] arm64: allwinner: a64: enable RSB on A64

FromIcenowy Zheng <icenowy@aosc.io>
Date2017-04-04 20:10 +0200
Subject[PATCH 01/11] arm64: allwinner: a64: enable RSB on A64
Message-ID<tsB3Y-8pK-5@gated-at.bofh.it>
Allwinner A64 have a RSB controller like the one on A23/A33 SoCs.

Add it and its pinmux.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 6bc606b4d74d..9a75b1c7c91a 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -420,6 +420,27 @@
 			#gpio-cells = <3>;
 			interrupt-controller;
 			#interrupt-cells = <3>;
+
+			r_rsb_pins: rsb@0 {
+				pins = "PL0", "PL1";
+				function = "s_rsb";
+				drive-strength = <20>;
+				bias-pull-up;
+			};
+		};
+
+		r_rsb: rsb@1f03400 {
+			compatible = "allwinner,sun8i-a23-rsb";
+			reg = <0x01f03400 0x400>;
+			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&r_ccu 6>;
+			clock-frequency = <3000000>;
+			resets = <&r_ccu 2>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&r_rsb_pins>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
 		};
 	};
 };
-- 
2.12.2

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#1616549 — Re: [linux-sunxi] [PATCH 01/11] arm64: allwinner: a64: enable RSB on A64

FromChen-Yu Tsai <wens@csie.org>
Date2017-04-05 05:50 +0200
SubjectRe: [linux-sunxi] [PATCH 01/11] arm64: allwinner: a64: enable RSB on A64
Message-ID<tsK7f-5H7-7@gated-at.bofh.it>
In reply to#1616278
On Wed, Apr 5, 2017 at 2:01 AM, Icenowy Zheng <icenowy@aosc.io> wrote:
> Allwinner A64 have a RSB controller like the one on A23/A33 SoCs.
>
> Add it and its pinmux.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
>  arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> index 6bc606b4d74d..9a75b1c7c91a 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> @@ -420,6 +420,27 @@
>                         #gpio-cells = <3>;
>                         interrupt-controller;
>                         #interrupt-cells = <3>;
> +
> +                       r_rsb_pins: rsb@0 {
> +                               pins = "PL0", "PL1";
> +                               function = "s_rsb";
> +                               drive-strength = <20>;

We don't need this. The hardware default should be enough.

> +                               bias-pull-up;

Boards should have external pull-ups for these pins, as the PMICs
start up in I2C mode. If any board actually doesn't have them and
needs the internal pull-ups, they should be set at the board level.

Otherwise,

Acked-by: Chen-Yu Tsai <wens@csie.org>

> +                       };
> +               };
> +
> +               r_rsb: rsb@1f03400 {
> +                       compatible = "allwinner,sun8i-a23-rsb";
> +                       reg = <0x01f03400 0x400>;
> +                       interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&r_ccu 6>;
> +                       clock-frequency = <3000000>;
> +                       resets = <&r_ccu 2>;
> +                       pinctrl-names = "default";
> +                       pinctrl-0 = <&r_rsb_pins>;
> +                       status = "disabled";
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
>                 };
>         };
>  };
> --
> 2.12.2
>
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