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Re: [PATCH v4 4/6] arm64: dts: rockchip: add core dtsi file for RK3328 SoCs

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  Re: [PATCH v4 4/6] arm64: dts: rockchip: add core dtsi file for RK3328 SoCs Heiko Stuebner <heiko@sntech.de> - 2017-04-04 18:10 +0200
    Re: [PATCH v4 4/6] arm64: dts: rockchip: add core dtsi file for RK3328  SoCs Elaine Zhang <zhangqing@rock-chips.com> - 2017-04-05 04:20 +0200
      Re: [PATCH v4 4/6] arm64: dts: rockchip: add core dtsi file for RK3328 SoCs Heiko Stübner <heiko@sntech.de> - 2017-04-05 12:20 +0200

#1616172 — Re: [PATCH v4 4/6] arm64: dts: rockchip: add core dtsi file for RK3328 SoCs

Am Montag, 27. März 2017, 17:40:48 CEST schrieb cl@rock-chips.com:
> From: Liang Chen <cl@rock-chips.com>
> 
> This patch adds core dtsi file for Rockchip RK3328 SoCs.
> 
> Signed-off-by: Liang Chen <cl@rock-chips.com>

applied for 4.12, with the following list of changes:

- reorder some properties to bring them in alphabetical order
- dropped the status-disabled from the power-controller
  power-domain control is a quite essential part of the system, so if
  boards really want to disable them, they should do it in their board file
  Having power-domains on all the time, is also our default in all other
  devicetrees.
- removed #dma-cells from spi0 -> this is not a dma controller
- reword the cru assigned-clocks comment a bit
- fixed sdmmc1_bus4 pins, as indicated by Shawn and after looking up the
  correct pins in the manual


And a final question, are you sure about SCLK_PDM becoming a child of the
APLL in your cru assigned-clocks, as the APLL will vary later on with cpufreq
active?


Heiko

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#1616527 — Re: [PATCH v4 4/6] arm64: dts: rockchip: add core dtsi file for RK3328 SoCs

On 04/05/2017 12:04 AM, Heiko Stuebner wrote:
> Am Montag, 27. März 2017, 17:40:48 CEST schrieb cl@rock-chips.com:
>> From: Liang Chen <cl@rock-chips.com>
>>
>> This patch adds core dtsi file for Rockchip RK3328 SoCs.
>>
>> Signed-off-by: Liang Chen <cl@rock-chips.com>
>
> applied for 4.12, with the following list of changes:
>
> - reorder some properties to bring them in alphabetical order
> - dropped the status-disabled from the power-controller
>    power-domain control is a quite essential part of the system, so if
>    boards really want to disable them, they should do it in their board file
>    Having power-domains on all the time, is also our default in all other
>    devicetrees.
> - removed #dma-cells from spi0 -> this is not a dma controller
> - reword the cru assigned-clocks comment a bit
> - fixed sdmmc1_bus4 pins, as indicated by Shawn and after looking up the
>    correct pins in the manual
>
>
> And a final question, are you sure about SCLK_PDM becoming a child of the
> APLL in your cru assigned-clocks, as the APLL will vary later on with cpufreq
> active?
>
the NPLL will vary later on with cpufreq active.

The NPLL is better than APLL, so NPLL is for clk_core,and apll is for pdm.

please see the TRM in CRU:
1.4 Function Description
/........./
To maximize the flexibility, some of clocks can select divider source 
from 5 PLLs. (Note: It’s
recommended to use NEW PLL instead of ARM PLL as arm clock source, 
because NEW PLL is
near to ARM. And it’s jitter is better than ARM PLL).

>
> Heiko
>
>
>

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#1616787

Hi Elaine,

Am Mittwoch, 5. April 2017, 10:07:41 CEST schrieb Elaine Zhang:
> On 04/05/2017 12:04 AM, Heiko Stuebner wrote:
> > Am Montag, 27. März 2017, 17:40:48 CEST schrieb cl@rock-chips.com:
> >> From: Liang Chen <cl@rock-chips.com>
> >> 
> >> This patch adds core dtsi file for Rockchip RK3328 SoCs.
> >> 
> >> Signed-off-by: Liang Chen <cl@rock-chips.com>
> > 
> > applied for 4.12, with the following list of changes:
> > 
> > - reorder some properties to bring them in alphabetical order
> > - dropped the status-disabled from the power-controller
> > 
> >    power-domain control is a quite essential part of the system, so if
> >    boards really want to disable them, they should do it in their board
> >    file
> >    Having power-domains on all the time, is also our default in all other
> >    devicetrees.
> > 
> > - removed #dma-cells from spi0 -> this is not a dma controller
> > - reword the cru assigned-clocks comment a bit
> > - fixed sdmmc1_bus4 pins, as indicated by Shawn and after looking up the
> > 
> >    correct pins in the manual
> > 
> > And a final question, are you sure about SCLK_PDM becoming a child of the
> > APLL in your cru assigned-clocks, as the APLL will vary later on with
> > cpufreq active?
> 
> the NPLL will vary later on with cpufreq active.
> 
> The NPLL is better than APLL, so NPLL is for clk_core,and apll is for pdm.
> 
> please see the TRM in CRU:
> 1.4 Function Description
> /........./
> To maximize the flexibility, some of clocks can select divider source
> from 5 PLLs. (Note: It’s
> recommended to use NEW PLL instead of ARM PLL as arm clock source,
> because NEW PLL is
> near to ARM. And it’s jitter is better than ARM PLL).

Thanks for the clarification - this way it definitly makes sense.


Thanks
Heiko

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