Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]
Groups > linux.kernel > #1615021 > unrolled thread
| Started by | Corentin Labbe <clabbe.montjoie@gmail.com> |
|---|---|
| First post | 2017-04-03 11:30 +0200 |
| Last post | 2017-04-03 13:20 +0200 |
| Articles | 2 — 2 participants |
Back to article view | Back to linux.kernel
This discussion starts older than the indexed window; earlier articles aren't shown. The article labeled Started by
below is the oldest one visible, not the original post.
[PATCH v3 03/20] dt-bindings: net: Add DT bindings documentation for Allwinner dwmac-sun8i Corentin Labbe <clabbe.montjoie@gmail.com> - 2017-04-03 11:30 +0200
Re: [PATCH v3 03/20] dt-bindings: net: Add DT bindings documentation for Allwinner dwmac-sun8i Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-04-03 13:20 +0200
| From | Corentin Labbe <clabbe.montjoie@gmail.com> |
|---|---|
| Date | 2017-04-03 11:30 +0200 |
| Subject | [PATCH v3 03/20] dt-bindings: net: Add DT bindings documentation for Allwinner dwmac-sun8i |
| Message-ID | <ts6tc-4ZD-21@gated-at.bofh.it> |
This patch adds documentation for Device-Tree bindings for the
Allwinner dwmac-sun8i driver.
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/net/dwmac-sun8i.txt | 77 ++++++++++++++++++++++
1 file changed, 77 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/dwmac-sun8i.txt
diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
new file mode 100644
index 0000000..f01ef17
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
@@ -0,0 +1,77 @@
+* Allwinner sun8i GMAC ethernet controller
+
+This device is a platform glue layer for stmmac.
+Please see stmmac.txt for the other unchanged properties.
+
+Required properties:
+- compatible: should be one of the following string:
+ "allwinner,sun8i-a83t-emac"
+ "allwinner,sun8i-h3-emac"
+ "allwinner,sun50i-a64-emac"
+- reg: address and length of the register for the device.
+- interrupts: interrupt for the device
+- interrupt-names: should be "macirq"
+- clocks: A phandle to the reference clock for this device
+- clock-names: should be "stmmaceth"
+- resets: A phandle to the reset control for this device
+- reset-names: should be "stmmaceth"
+- phy-mode: See ethernet.txt
+- phy-handle: See ethernet.txt
+- #address-cells: shall be 1
+- #size-cells: shall be 0
+- syscon: A phandle to the syscon of the SoC with one of the following
+ compatible string:
+ - allwinner,sun8i-h3-system-controller
+ - allwinner,sun8i-a64-system-controller
+ - allwinner,sun8i-a83t-system-controller
+
+Optional properties:
+- allwinner,tx-delay: TX clock delay chain value. Range value is 0-0x07. Default is 0)
+- allwinner,rx-delay: RX clock delay chain value. Range value is 0-0x1F. Default is 0)
+Both delay properties are in 0.1ns step.
+
+Optional properties for "allwinner,sun8i-h3-emac":
+- allwinner,leds-active-low: EPHY LEDs are active low
+
+Required child node of emac:
+- mdio bus node: should be named mdio
+
+Required properties of the mdio node:
+- #address-cells: shall be 1
+- #size-cells: shall be 0
+
+The device node referenced by "phy" or "phy-handle" should be a child node
+of the mdio node. See phy.txt for the generic PHY bindings.
+
+Required properties of the phy node with "allwinner,sun8i-h3-emac":
+- clocks: a phandle to the reference clock for the EPHY
+- resets: a phandle to the reset control for the EPHY
+
+Example:
+
+emac: ethernet@1c0b000 {
+ compatible = "allwinner,sun8i-h3-emac";
+ syscon = <&syscon>;
+ reg = <0x01c0b000 0x104>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+ resets = <&ccu RST_BUS_EMAC>;
+ reset-names = "stmmaceth";
+ clocks = <&ccu CLK_BUS_EMAC>;
+ clock-names = "stmmaceth";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ int_mii_phy: ethernet-phy@1 {
+ reg = <1>;
+ clocks = <&ccu CLK_BUS_EPHY>;
+ resets = <&ccu RST_BUS_EPHY>;
+ };
+ };
+};
--
2.10.2
[toc] | [next] | [standalone]
| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2017-04-03 13:20 +0200 |
| Subject | Re: [PATCH v3 03/20] dt-bindings: net: Add DT bindings documentation for Allwinner dwmac-sun8i |
| Message-ID | <ts8bE-66S-19@gated-at.bofh.it> |
| In reply to | #1615021 |
[Multipart message — attachments visible in raw view] — view raw
On Mon, Apr 03, 2017 at 11:14:27AM +0200, Corentin Labbe wrote: > This patch adds documentation for Device-Tree bindings for the > Allwinner dwmac-sun8i driver. > > Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> > Acked-by: Rob Herring <robh@kernel.org> > --- > .../devicetree/bindings/net/dwmac-sun8i.txt | 77 ++++++++++++++++++++++ > 1 file changed, 77 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/dwmac-sun8i.txt > > diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt > new file mode 100644 > index 0000000..f01ef17 > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt > @@ -0,0 +1,77 @@ > +* Allwinner sun8i GMAC ethernet controller > + > +This device is a platform glue layer for stmmac. > +Please see stmmac.txt for the other unchanged properties. > + > +Required properties: > +- compatible: should be one of the following string: > + "allwinner,sun8i-a83t-emac" > + "allwinner,sun8i-h3-emac" > + "allwinner,sun50i-a64-emac" > +- reg: address and length of the register for the device. > +- interrupts: interrupt for the device > +- interrupt-names: should be "macirq" > +- clocks: A phandle to the reference clock for this device > +- clock-names: should be "stmmaceth" > +- resets: A phandle to the reset control for this device > +- reset-names: should be "stmmaceth" > +- phy-mode: See ethernet.txt > +- phy-handle: See ethernet.txt > +- #address-cells: shall be 1 > +- #size-cells: shall be 0 > +- syscon: A phandle to the syscon of the SoC with one of the following > + compatible string: > + - allwinner,sun8i-h3-system-controller > + - allwinner,sun8i-a64-system-controller > + - allwinner,sun8i-a83t-system-controller I'm not sure you need to document those compatibles here. > +Optional properties: > +- allwinner,tx-delay: TX clock delay chain value. Range value is 0-0x07. Default is 0) > +- allwinner,rx-delay: RX clock delay chain value. Range value is 0-0x1F. Default is 0) > +Both delay properties are in 0.1ns step. allwinner,tx-delay-ps and allwinner,rx-delay-ps, with the value in picoseconds? Looks good otherwise, thanks! Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com
[toc] | [prev] | [standalone]
Back to top | Article view | linux.kernel
csiph-web