Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]

Groups > linux.kernel > #1614525 > unrolled thread

[PATCH 3.16 00/19] 3.16.43-rc1 review

Started byBen Hutchings <ben@decadent.org.uk>
First post2017-04-01 15:30 +0200
Last post2017-04-02 05:20 +0200
Articles 11 — 2 participants

Back to article view | Back to linux.kernel

Contents

  [PATCH 3.16 00/19] 3.16.43-rc1 review Ben Hutchings <ben@decadent.org.uk> - 2017-04-01 15:30 +0200
    [PATCH 3.16 07/19] MIPS: Fix build with binutils 2.24.51+ Ben Hutchings <ben@decadent.org.uk> - 2017-04-01 15:30 +0200
    [PATCH 3.16 09/19] crypto: improve gcc optimization flags for  serpent and wp512 Ben Hutchings <ben@decadent.org.uk> - 2017-04-01 15:30 +0200
    Re: [PATCH 3.16 00/19] 3.16.43-rc1 review Guenter Roeck <linux@roeck-us.net> - 2017-04-01 19:50 +0200
      Re: [PATCH 3.16 00/19] 3.16.43-rc1 review Ben Hutchings <ben@decadent.org.uk> - 2017-04-02 00:50 +0200
        Re: [PATCH 3.16 00/19] 3.16.43-rc1 review Guenter Roeck <linux@roeck-us.net> - 2017-04-02 04:30 +0200
        Re: [PATCH 3.16 00/19] 3.16.43-rc1 review Ben Hutchings <ben@decadent.org.uk> - 2017-04-02 04:50 +0200
    [PATCH 3.16 00/26] 3.16.43-rc2 review Ben Hutchings <ben@decadent.org.uk> - 2017-04-02 05:20 +0200
      [PATCH 3.16 23/26] MIPS: Push .set mips64r* into the functions  needing it Ben Hutchings <ben@decadent.org.uk> - 2017-04-02 05:20 +0200
      [PATCH 3.16 24/26] MIPS: assume at as source/dest of MSA  copy/insert instructions Ben Hutchings <ben@decadent.org.uk> - 2017-04-02 05:20 +0200
      [PATCH 3.16 26/26] MIPS: wrap cfcmsa & ctcmsa accesses for  toolchains with MSA support Ben Hutchings <ben@decadent.org.uk> - 2017-04-02 05:20 +0200

#1614525 — [PATCH 3.16 00/19] 3.16.43-rc1 review

FromBen Hutchings <ben@decadent.org.uk>
Date2017-04-01 15:30 +0200
Subject[PATCH 3.16 00/19] 3.16.43-rc1 review
Message-ID<trrgm-3fN-3@gated-at.bofh.it>
This is the start of the stable review cycle for the 3.16.43 release.
There are 19 patches in this series, which will be posted as responses
to this one.  If anyone has any issues with these being applied, please
let me know.

Responses should be made by Tue Apr 04 00:00:00 UTC 2017.
Anything received after that time might be too late.

A combined patch relative to 3.16.42 will be posted as an additional
response to this.  A shortlog and diffstat can be found below.

Ben.

-------------

Andre Przywara (1):
      fs/nfs: fix new compiler warning about boolean in switch
         [c7757074839f2cd440521482d76ea180d0d4bdac]

Arnd Bergmann (2):
      crypto: improve gcc optimization flags for serpent and wp512
         [7d6e9105026788c497f0ab32fa16c82f4ab5ff61]
      mmc: sunxi: avoid invalid pointer calculation
         [d34712d2e3db9b241d0484a6e3839c6b7ef9df78]

Ben Hutchings (1):
      keys: Guard against null match function in keyring_search_aux()
         [c06cfb08b88dfbe13be44a69ae2fdc3a7c902d81]

Eric W. Biederman (1):
      vfs: Commit to never having exectuables on proc and sysfs.
         [22f6b4d34fcf039c63a94e7670e0da24f8575a5a]

Fabio Estevam (1):
      serial: samsung: Use %pa to print 'resource_size_t' type
         [1ff5b64dccbf23acfe7993b9132b6992922a4756]

Florian Westphal (1):
      netlink: remove mmapped netlink support
         [d1b4c689d4130bcfd3532680b64db562300716b6]

James C Boyd (1):
      HID: hid-input: Add parentheses to quell gcc warning
         [09a5c34e8d6b05663ec4c3d22b1fbd9fec89aaf9]

Jann Horn (1):
      aio: mark AIO pseudo-fs noexec
         [22f6b4d34fcf039c63a94e7670e0da24f8575a5a]

John Crispin (1):
      MIPS: ralink: Cosmetic change to prom_init().
         [9c48568b3692f1a56cbf1935e4eea835e6b185b1]

Linus Torvalds (1):
      blk: rq_data_dir() should not return a boolean
         [10fbd36e362a0f367e34a7cd876a81295d8fc5ca]

Manuel Lauss (1):
      MIPS: Fix build with binutils 2.24.51+
         [842dfc11ea9a21f9825167c8a4f2834b205b0a79]

Paul Burton (4):
      MIPS: init upper 64b of vector registers when MSA is first used
         [c9017757c532d48bf43d6e7d3b7282443ad4207b]
      MIPS: preserve scalar FP CSR when switching vector context
         [b83406735a4ae0aff4b614664d6a64a0fd6b9917]
      MIPS: save/disable MSA in lose_fpu
         [33c771ba5c5d067f85a5a6c4b11047219b5b8f4e]
      MIPS: save/restore MSACSR register on context switch
         [f7a46fa7bb0047d3e226702a0c4b786862fe6843]

Ralf Baechle (1):
      MIPS: Zero variable read by get_user / __get_user in case of an error.
         [640465bda58c7078725201be7430c31a349121e9]

Tillmann Heidsieck (1):
      atm: iphase: fix misleading indention
         [cbb41b91e68a302087762823136c9067138cff7c]

Tim Gardner (1):
      fs: namespace: suppress 'may be used uninitialized' warnings
         [b8850d1fa8e2f6653e57daf6d08e58c5f5eb2c85]

 Documentation/networking/netlink_mmap.txt | 339 --------------
 Makefile                                  |   4 +-
 arch/mips/Makefile                        |   9 +
 arch/mips/include/asm/asmmacro-32.h       |   6 +
 arch/mips/include/asm/asmmacro.h          |  49 ++
 arch/mips/include/asm/fpregdef.h          |  14 +
 arch/mips/include/asm/fpu.h               |  15 +-
 arch/mips/include/asm/mipsregs.h          |  11 +-
 arch/mips/include/asm/msa.h               |   1 +
 arch/mips/include/asm/uaccess.h           |   5 +-
 arch/mips/kernel/asm-offsets.c            |   1 +
 arch/mips/kernel/branch.c                 |   8 +-
 arch/mips/kernel/genex.S                  |   1 +
 arch/mips/kernel/r2300_fpu.S              |   6 +
 arch/mips/kernel/r2300_switch.S           |   5 +
 arch/mips/kernel/r4k_fpu.S                |  27 +-
 arch/mips/kernel/r4k_switch.S             |  24 +-
 arch/mips/kernel/r6000_fpu.S              |   5 +
 arch/mips/kernel/traps.c                  |  38 +-
 arch/mips/math-emu/cp1emu.c               |   6 +-
 arch/mips/ralink/prom.c                   |   9 +-
 crypto/Makefile                           |   2 +
 drivers/atm/iphase.c                      |   2 +-
 drivers/hid/hid-input.c                   |   2 +-
 drivers/mmc/host/sunxi-mmc.c              |   5 +-
 drivers/tty/serial/samsung.c              |   4 +-
 fs/aio.c                                  |   1 +
 fs/compat.c                               |  10 +-
 fs/exec.c                                 |  10 +-
 fs/internal.h                             |   2 +-
 fs/namespace.c                            |  26 +-
 fs/nfs/nfs4proc.c                         |  11 +-
 fs/open.c                                 |   2 +-
 fs/proc/root.c                            |   2 +-
 fs/sysfs/mount.c                          |   3 +-
 include/linux/blkdev.h                    |   2 +-
 include/linux/fs.h                        |   3 +
 include/uapi/linux/netlink.h              |   4 +
 include/uapi/linux/netlink_diag.h         |   2 +
 kernel/sys.c                              |   3 +-
 mm/mmap.c                                 |   4 +-
 mm/nommu.c                                |   2 +-
 net/netlink/Kconfig                       |   9 -
 net/netlink/af_netlink.c                  | 738 +-----------------------------
 net/netlink/af_netlink.h                  |  15 -
 net/netlink/diag.c                        |  39 --
 security/keys/keyring.c                   |   6 +-
 security/security.c                       |   2 +-
 48 files changed, 279 insertions(+), 1215 deletions(-)

-- 
Ben Hutchings
It is easier to change the specification to fit the program than vice versa.

[toc] | [next] | [standalone]

#1614526 — [PATCH 3.16 07/19] MIPS: Fix build with binutils 2.24.51+

FromBen Hutchings <ben@decadent.org.uk>
Date2017-04-01 15:30 +0200
Subject[PATCH 3.16 07/19] MIPS: Fix build with binutils 2.24.51+
Message-ID<trrgn-3fN-41@gated-at.bofh.it>
In reply to#1614525
3.16.43-rc1 review patch.  If anyone has any objections, please let me know.

------------------

From: Manuel Lauss <manuel.lauss@gmail.com>

commit 842dfc11ea9a21f9825167c8a4f2834b205b0a79 upstream.

Starting with version 2.24.51.20140728 MIPS binutils complain loudly
about mixing soft-float and hard-float object files, leading to this
build failure since GCC is invoked with "-msoft-float" on MIPS:

{standard input}: Warning: .gnu_attribute 4,3 requires `softfloat'
  LD      arch/mips/alchemy/common/built-in.o
mipsel-softfloat-linux-gnu-ld: Warning: arch/mips/alchemy/common/built-in.o
 uses -msoft-float (set by arch/mips/alchemy/common/prom.o),
 arch/mips/alchemy/common/sleeper.o uses -mhard-float

To fix this, we detect if GAS is new enough to support "-msoft-float" command
option, and if it does, we can let GCC pass it to GAS;  but then we also need
to sprinkle the files which make use of floating point registers with the
necessary ".set hardfloat" directives.

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Cc: Matthew Fortune <Matthew.Fortune@imgtec.com>
Cc: Markos Chandras <Markos.Chandras@imgtec.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/8355/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
Cc: Arnd Bergmann <arnd@arndb.de>
---
 arch/mips/Makefile                  |  9 +++++++++
 arch/mips/include/asm/asmmacro-32.h |  6 ++++++
 arch/mips/include/asm/asmmacro.h    | 18 ++++++++++++++++++
 arch/mips/include/asm/fpregdef.h    | 14 ++++++++++++++
 arch/mips/include/asm/fpu.h         |  4 ++--
 arch/mips/include/asm/mipsregs.h    | 11 ++++++++++-
 arch/mips/kernel/branch.c           |  8 ++------
 arch/mips/kernel/genex.S            |  1 +
 arch/mips/kernel/r2300_fpu.S        |  6 ++++++
 arch/mips/kernel/r2300_switch.S     |  5 +++++
 arch/mips/kernel/r4k_fpu.S          | 27 +++++++++++++++++++++++++--
 arch/mips/kernel/r4k_switch.S       | 15 ++++++++++++++-
 arch/mips/kernel/r6000_fpu.S        |  5 +++++
 arch/mips/math-emu/cp1emu.c         |  6 +-----
 14 files changed, 118 insertions(+), 17 deletions(-)

--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -93,6 +93,15 @@ LDFLAGS_vmlinux			+= -G 0 -static -n -no
 KBUILD_AFLAGS_MODULE		+= -mlong-calls
 KBUILD_CFLAGS_MODULE		+= -mlong-calls
 
+#
+# pass -msoft-float to GAS if it supports it.  However on newer binutils
+# (specifically newer than 2.24.51.20140728) we then also need to explicitly
+# set ".set hardfloat" in all files which manipulate floating point registers.
+#
+ifneq ($(call as-option,-Wa$(comma)-msoft-float,),)
+	cflags-y		+= -DGAS_HAS_SET_HARDFLOAT -Wa,-msoft-float
+endif
+
 cflags-y += -ffreestanding
 
 #
--- a/arch/mips/include/asm/asmmacro-32.h
+++ b/arch/mips/include/asm/asmmacro-32.h
@@ -13,6 +13,8 @@
 #include <asm/mipsregs.h>
 
 	.macro	fpu_save_single thread tmp=t0
+	.set push
+	SET_HARDFLOAT
 	cfc1	\tmp,  fcr31
 	swc1	$f0,  THREAD_FPR0_LS64(\thread)
 	swc1	$f1,  THREAD_FPR1_LS64(\thread)
@@ -47,9 +49,12 @@
 	swc1	$f30, THREAD_FPR30_LS64(\thread)
 	swc1	$f31, THREAD_FPR31_LS64(\thread)
 	sw	\tmp, THREAD_FCR31(\thread)
+	.set pop
 	.endm
 
 	.macro	fpu_restore_single thread tmp=t0
+	.set push
+	SET_HARDFLOAT
 	lw	\tmp, THREAD_FCR31(\thread)
 	lwc1	$f0,  THREAD_FPR0_LS64(\thread)
 	lwc1	$f1,  THREAD_FPR1_LS64(\thread)
@@ -84,6 +89,7 @@
 	lwc1	$f30, THREAD_FPR30_LS64(\thread)
 	lwc1	$f31, THREAD_FPR31_LS64(\thread)
 	ctc1	\tmp, fcr31
+	.set pop
 	.endm
 
 	.macro	cpu_save_nonscratch thread
--- a/arch/mips/include/asm/asmmacro.h
+++ b/arch/mips/include/asm/asmmacro.h
@@ -57,6 +57,8 @@
 #endif /* CONFIG_CPU_MIPSR2 */
 
 	.macro	fpu_save_16even thread tmp=t0
+	.set	push
+	SET_HARDFLOAT
 	cfc1	\tmp, fcr31
 	sdc1	$f0,  THREAD_FPR0_LS64(\thread)
 	sdc1	$f2,  THREAD_FPR2_LS64(\thread)
@@ -75,11 +77,13 @@
 	sdc1	$f28, THREAD_FPR28_LS64(\thread)
 	sdc1	$f30, THREAD_FPR30_LS64(\thread)
 	sw	\tmp, THREAD_FCR31(\thread)
+	.set	pop
 	.endm
 
 	.macro	fpu_save_16odd thread
 	.set	push
 	.set	mips64r2
+	SET_HARDFLOAT
 	sdc1	$f1,  THREAD_FPR1_LS64(\thread)
 	sdc1	$f3,  THREAD_FPR3_LS64(\thread)
 	sdc1	$f5,  THREAD_FPR5_LS64(\thread)
@@ -110,6 +114,8 @@
 	.endm
 
 	.macro	fpu_restore_16even thread tmp=t0
+	.set	push
+	SET_HARDFLOAT
 	lw	\tmp, THREAD_FCR31(\thread)
 	ldc1	$f0,  THREAD_FPR0_LS64(\thread)
 	ldc1	$f2,  THREAD_FPR2_LS64(\thread)
@@ -133,6 +139,7 @@
 	.macro	fpu_restore_16odd thread
 	.set	push
 	.set	mips64r2
+	SET_HARDFLOAT
 	ldc1	$f1,  THREAD_FPR1_LS64(\thread)
 	ldc1	$f3,  THREAD_FPR3_LS64(\thread)
 	ldc1	$f5,  THREAD_FPR5_LS64(\thread)
@@ -277,6 +284,7 @@
 	.macro	cfcmsa	rd, cs
 	.set	push
 	.set	noat
+	SET_HARDFLOAT
 	.insn
 	.word	CFC_MSA_INSN | (\cs << 11)
 	move	\rd, $1
@@ -286,6 +294,7 @@
 	.macro	ctcmsa	cd, rs
 	.set	push
 	.set	noat
+	SET_HARDFLOAT
 	move	$1, \rs
 	.word	CTC_MSA_INSN | (\cd << 6)
 	.set	pop
@@ -294,6 +303,7 @@
 	.macro	ld_d	wd, off, base
 	.set	push
 	.set	noat
+	SET_HARDFLOAT
 	addu	$1, \base, \off
 	.word	LDD_MSA_INSN | (\wd << 6)
 	.set	pop
@@ -302,6 +312,7 @@
 	.macro	st_d	wd, off, base
 	.set	push
 	.set	noat
+	SET_HARDFLOAT
 	addu	$1, \base, \off
 	.word	STD_MSA_INSN | (\wd << 6)
 	.set	pop
@@ -310,6 +321,7 @@
 	.macro	copy_u_w	rd, ws, n
 	.set	push
 	.set	noat
+	SET_HARDFLOAT
 	.insn
 	.word	COPY_UW_MSA_INSN | (\n << 16) | (\ws << 11)
 	/* move triggers an assembler bug... */
@@ -320,6 +332,7 @@
 	.macro	copy_u_d	rd, ws, n
 	.set	push
 	.set	noat
+	SET_HARDFLOAT
 	.insn
 	.word	COPY_UD_MSA_INSN | (\n << 16) | (\ws << 11)
 	/* move triggers an assembler bug... */
@@ -330,6 +343,7 @@
 	.macro	insert_w	wd, n, rs
 	.set	push
 	.set	noat
+	SET_HARDFLOAT
 	/* move triggers an assembler bug... */
 	or	$1, \rs, zero
 	.word	INSERT_W_MSA_INSN | (\n << 16) | (\wd << 6)
@@ -339,6 +353,7 @@
 	.macro	insert_d	wd, n, rs
 	.set	push
 	.set	noat
+	SET_HARDFLOAT
 	/* move triggers an assembler bug... */
 	or	$1, \rs, zero
 	.word	INSERT_D_MSA_INSN | (\n << 16) | (\wd << 6)
@@ -381,6 +396,7 @@
 	st_d	31, THREAD_FPR31, \thread
 	.set	push
 	.set	noat
+	SET_HARDFLOAT
 	cfcmsa	$1, MSA_CSR
 	sw	$1, THREAD_MSA_CSR(\thread)
 	.set	pop
@@ -389,6 +405,7 @@
 	.macro	msa_restore_all	thread
 	.set	push
 	.set	noat
+	SET_HARDFLOAT
 	lw	$1, THREAD_MSA_CSR(\thread)
 	ctcmsa	MSA_CSR, $1
 	.set	pop
@@ -441,6 +458,7 @@
 	.macro	msa_init_all_upper
 	.set	push
 	.set	noat
+	SET_HARDFLOAT
 	not	$1, zero
 	msa_init_upper	0
 	.set	pop
--- a/arch/mips/include/asm/fpregdef.h
+++ b/arch/mips/include/asm/fpregdef.h
@@ -14,6 +14,20 @@
 
 #include <asm/sgidefs.h>
 
+/*
+ * starting with binutils 2.24.51.20140729, MIPS binutils warn about mixing
+ * hardfloat and softfloat object files.  The kernel build uses soft-float by
+ * default, so we also need to pass -msoft-float along to GAS if it supports it.
+ * But this in turn causes assembler errors in files which access hardfloat
+ * registers.  We detect if GAS supports "-msoft-float" in the Makefile and
+ * explicitly put ".set hardfloat" where floating point registers are touched.
+ */
+#ifdef GAS_HAS_SET_HARDFLOAT
+#define SET_HARDFLOAT .set hardfloat
+#else
+#define SET_HARDFLOAT
+#endif
+
 #if _MIPS_SIM == _MIPS_SIM_ABI32
 
 /*
--- a/arch/mips/include/asm/fpu.h
+++ b/arch/mips/include/asm/fpu.h
@@ -145,8 +145,8 @@ static inline void lose_fpu(int save)
 	if (is_msa_enabled()) {
 		if (save) {
 			save_msa(current);
-			asm volatile("cfc1 %0, $31"
-				: "=r"(current->thread.fpu.fcr31));
+			current->thread.fpu.fcr31 =
+					read_32bit_cp1_register(CP1_STATUS);
 		}
 		disable_msa();
 		clear_thread_flag(TIF_USEDMSA);
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1270,7 +1270,7 @@ do {									\
 /*
  * Macros to access the floating point coprocessor control registers
  */
-#define read_32bit_cp1_register(source)					\
+#define _read_32bit_cp1_register(source, gas_hardfloat)			\
 ({									\
 	int __res;							\
 									\
@@ -1280,12 +1280,21 @@ do {									\
 	"	# gas fails to assemble cfc1 for some archs,	\n"	\
 	"	# like Octeon.					\n"	\
 	"	.set	mips1					\n"	\
+	"	"STR(gas_hardfloat)"				\n"	\
 	"	cfc1	%0,"STR(source)"			\n"	\
 	"	.set	pop					\n"	\
 	: "=r" (__res));						\
 	__res;								\
 })
 
+#ifdef GAS_HAS_SET_HARDFLOAT
+#define read_32bit_cp1_register(source)					\
+	_read_32bit_cp1_register(source, .set hardfloat)
+#else
+#define read_32bit_cp1_register(source)					\
+	_read_32bit_cp1_register(source, )
+#endif
+
 #ifdef HAVE_AS_DSP
 #define rddsp(mask)							\
 ({									\
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -144,7 +144,7 @@ int __mm_isBranchInstr(struct pt_regs *r
 		case mm_bc1t_op:
 			preempt_disable();
 			if (is_fpu_owner())
-				asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
+			        fcr31 = read_32bit_cp1_register(CP1_STATUS);
 			else
 				fcr31 = current->thread.fpu.fcr31;
 			preempt_enable();
@@ -562,11 +562,7 @@ int __compute_return_epc_for_insn(struct
 	case cop1_op:
 		preempt_disable();
 		if (is_fpu_owner())
-			asm volatile(
-				".set push\n"
-				"\t.set mips1\n"
-				"\tcfc1\t%0,$31\n"
-				"\t.set pop" : "=r" (fcr31));
+		        fcr31 = read_32bit_cp1_register(CP1_STATUS);
 		else
 			fcr31 = current->thread.fpu.fcr31;
 		preempt_enable();
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -358,6 +358,7 @@ NESTED(nmi_handler, PT_SIZE, sp)
 	.set	push
 	/* gas fails to assemble cfc1 for some archs (octeon).*/ \
 	.set	mips1
+	SET_HARDFLOAT
 	cfc1	a1, fcr31
 	li	a2, ~(0x3f << 12)
 	and	a2, a1
--- a/arch/mips/kernel/r2300_fpu.S
+++ b/arch/mips/kernel/r2300_fpu.S
@@ -28,6 +28,8 @@
 	.set	mips1
 	/* Save floating point context */
 LEAF(_save_fp_context)
+	.set	push
+	SET_HARDFLOAT
 	li	v0, 0					# assume success
 	cfc1	t1,fcr31
 	EX(swc1 $f0,(SC_FPREGS+0)(a0))
@@ -65,6 +67,7 @@ LEAF(_save_fp_context)
 	EX(sw	t1,(SC_FPC_CSR)(a0))
 	cfc1	t0,$0				# implementation/version
 	jr	ra
+	.set	pop
 	.set	nomacro
 	 EX(sw	t0,(SC_FPC_EIR)(a0))
 	.set	macro
@@ -80,6 +83,8 @@ LEAF(_save_fp_context)
  * stack frame which might have been changed by the user.
  */
 LEAF(_restore_fp_context)
+	.set	push
+	SET_HARDFLOAT
 	li	v0, 0					# assume success
 	EX(lw t0,(SC_FPC_CSR)(a0))
 	EX(lwc1 $f0,(SC_FPREGS+0)(a0))
@@ -116,6 +121,7 @@ LEAF(_restore_fp_context)
 	EX(lwc1 $f31,(SC_FPREGS+248)(a0))
 	jr	ra
 	 ctc1	t0,fcr31
+	.set	pop
 	END(_restore_fp_context)
 	.set	reorder
 
--- a/arch/mips/kernel/r2300_switch.S
+++ b/arch/mips/kernel/r2300_switch.S
@@ -120,6 +120,9 @@ LEAF(_restore_fp)
 
 #define FPU_DEFAULT  0x00000000
 
+	.set push
+	SET_HARDFLOAT
+
 LEAF(_init_fpu)
 	mfc0	t0, CP0_STATUS
 	li	t1, ST0_CU1
@@ -165,3 +168,5 @@ LEAF(_init_fpu)
 	mtc1	t0, $f31
 	jr	ra
 	END(_init_fpu)
+
+	.set pop
--- a/arch/mips/kernel/r4k_fpu.S
+++ b/arch/mips/kernel/r4k_fpu.S
@@ -19,8 +19,12 @@
 #include <asm/asm-offsets.h>
 #include <asm/regdef.h>
 
+/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
+#undef fp
+
 	.macro	EX insn, reg, src
 	.set	push
+	SET_HARDFLOAT
 	.set	nomacro
 .ex\@:	\insn	\reg, \src
 	.set	pop
@@ -33,12 +37,17 @@
 	.set	arch=r4000
 
 LEAF(_save_fp_context)
+	.set	push
+	SET_HARDFLOAT
 	cfc1	t1, fcr31
+	.set	pop
 
 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
 	.set	push
+	SET_HARDFLOAT
 #ifdef CONFIG_CPU_MIPS32_R2
-	.set	mips64r2
+	.set	mips32r2
+	.set	fp=64
 	mfc0	t0, CP0_STATUS
 	sll	t0, t0, 5
 	bgez	t0, 1f			# skip storing odd if FR=0
@@ -64,6 +73,8 @@ LEAF(_save_fp_context)
 1:	.set	pop
 #endif
 
+	.set push
+	SET_HARDFLOAT
 	/* Store the 16 even double precision registers */
 	EX	sdc1 $f0, SC_FPREGS+0(a0)
 	EX	sdc1 $f2, SC_FPREGS+16(a0)
@@ -84,11 +95,14 @@ LEAF(_save_fp_context)
 	EX	sw t1, SC_FPC_CSR(a0)
 	jr	ra
 	 li	v0, 0					# success
+	.set pop
 	END(_save_fp_context)
 
 #ifdef CONFIG_MIPS32_COMPAT
 	/* Save 32-bit process floating point context */
 LEAF(_save_fp_context32)
+	.set push
+	SET_HARDFLOAT
 	cfc1	t1, fcr31
 
 	mfc0	t0, CP0_STATUS
@@ -134,6 +148,7 @@ LEAF(_save_fp_context32)
 	EX	sw t1, SC32_FPC_CSR(a0)
 	cfc1	t0, $0				# implementation/version
 	EX	sw t0, SC32_FPC_EIR(a0)
+	.set pop
 
 	jr	ra
 	 li	v0, 0					# success
@@ -150,8 +165,10 @@ LEAF(_restore_fp_context)
 
 #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
 	.set	push
+	SET_HARDFLOAT
 #ifdef CONFIG_CPU_MIPS32_R2
-	.set	mips64r2
+	.set	mips32r2
+	.set	fp=64
 	mfc0	t0, CP0_STATUS
 	sll	t0, t0, 5
 	bgez	t0, 1f			# skip loading odd if FR=0
@@ -175,6 +192,8 @@ LEAF(_restore_fp_context)
 	EX	ldc1 $f31, SC_FPREGS+248(a0)
 1:	.set pop
 #endif
+	.set push
+	SET_HARDFLOAT
 	EX	ldc1 $f0, SC_FPREGS+0(a0)
 	EX	ldc1 $f2, SC_FPREGS+16(a0)
 	EX	ldc1 $f4, SC_FPREGS+32(a0)
@@ -192,6 +211,7 @@ LEAF(_restore_fp_context)
 	EX	ldc1 $f28, SC_FPREGS+224(a0)
 	EX	ldc1 $f30, SC_FPREGS+240(a0)
 	ctc1	t1, fcr31
+	.set pop
 	jr	ra
 	 li	v0, 0					# success
 	END(_restore_fp_context)
@@ -199,6 +219,8 @@ LEAF(_restore_fp_context)
 #ifdef CONFIG_MIPS32_COMPAT
 LEAF(_restore_fp_context32)
 	/* Restore an o32 sigcontext.  */
+	.set push
+	SET_HARDFLOAT
 	EX	lw t1, SC32_FPC_CSR(a0)
 
 	mfc0	t0, CP0_STATUS
@@ -242,6 +264,7 @@ LEAF(_restore_fp_context32)
 	ctc1	t1, fcr31
 	jr	ra
 	 li	v0, 0					# success
+	.set pop
 	END(_restore_fp_context32)
 #endif
 
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -22,6 +22,9 @@
 
 #include <asm/asmmacro.h>
 
+/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
+#undef fp
+
 /*
  * Offset to the current process status flags, the first 32 bytes of the
  * stack are not used.
@@ -65,8 +68,12 @@
 	bgtz	a3, 1f
 
 	/* Save 128b MSA vector context + scalar FP control & status. */
+	.set push
+	SET_HARDFLOAT
 	cfc1	t1, fcr31
 	msa_save_all	a0
+	.set pop	/* SET_HARDFLOAT */
+
 	sw	t1, THREAD_FCR31(a0)
 	b	2f
 
@@ -161,6 +168,9 @@ LEAF(_init_msa_upper)
 
 #define FPU_DEFAULT  0x00000000
 
+	.set push
+	SET_HARDFLOAT
+
 LEAF(_init_fpu)
 	mfc0	t0, CP0_STATUS
 	li	t1, ST0_CU1
@@ -232,7 +242,8 @@ LEAF(_init_fpu)
 
 #ifdef CONFIG_CPU_MIPS32_R2
 	.set    push
-	.set    mips64r2
+	.set    mips32r2
+	.set	fp=64
 	sll     t0, t0, 5			# is Status.FR set?
 	bgez    t0, 1f				# no: skip setting upper 32b
 
@@ -291,3 +302,5 @@ LEAF(_init_fpu)
 #endif
 	jr	ra
 	END(_init_fpu)
+
+	.set pop	/* SET_HARDFLOAT */
--- a/arch/mips/kernel/r6000_fpu.S
+++ b/arch/mips/kernel/r6000_fpu.S
@@ -18,6 +18,9 @@
 
 	.set	noreorder
 	.set	mips2
+	.set	push
+	SET_HARDFLOAT
+
 	/* Save floating point context */
 	LEAF(_save_fp_context)
 	mfc0	t0,CP0_STATUS
@@ -85,3 +88,5 @@
 1:	jr	ra
 	 nop
 	END(_restore_fp_context)
+
+	.set pop	/* SET_HARDFLOAT */
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -586,11 +586,7 @@ static int isBranchInstr(struct pt_regs
 		if (insn.i_format.rs == bc_op) {
 			preempt_disable();
 			if (is_fpu_owner())
-				asm volatile(
-					".set push\n"
-					"\t.set mips1\n"
-					"\tcfc1\t%0,$31\n"
-					"\t.set pop" : "=r" (fcr31));
+			        fcr31 = read_32bit_cp1_register(CP1_STATUS);
 			else
 				fcr31 = current->thread.fpu.fcr31;
 			preempt_enable();

[toc] | [prev] | [next] | [standalone]

#1614528 — [PATCH 3.16 09/19] crypto: improve gcc optimization flags for serpent and wp512

FromBen Hutchings <ben@decadent.org.uk>
Date2017-04-01 15:30 +0200
Subject[PATCH 3.16 09/19] crypto: improve gcc optimization flags for serpent and wp512
Message-ID<trrgo-3fN-57@gated-at.bofh.it>
In reply to#1614525
3.16.43-rc1 review patch.  If anyone has any objections, please let me know.

------------------

From: Arnd Bergmann <arnd@arndb.de>

commit 7d6e9105026788c497f0ab32fa16c82f4ab5ff61 upstream.

An ancient gcc bug (first reported in 2003) has apparently resurfaced
on MIPS, where kernelci.org reports an overly large stack frame in the
whirlpool hash algorithm:

crypto/wp512.c:987:1: warning: the frame size of 1112 bytes is larger than 1024 bytes [-Wframe-larger-than=]

With some testing in different configurations, I'm seeing large
variations in stack frames size up to 1500 bytes for what should have
around 300 bytes at most. I also checked the reference implementation,
which is essentially the same code but also comes with some test and
benchmarking infrastructure.

It seems that recent compiler versions on at least arm, arm64 and powerpc
have a partial fix for this problem, but enabling "-fsched-pressure", but
even with that fix they suffer from the issue to a certain degree. Some
testing on arm64 shows that the time needed to hash a given amount of
data is roughly proportional to the stack frame size here, which makes
sense given that the wp512 implementation is doing lots of loads for
table lookups, and the problem with the overly large stack is a result
of doing a lot more loads and stores for spilled registers (as seen from
inspecting the object code).

Disabling -fschedule-insns consistently fixes the problem for wp512,
in my collection of cross-compilers, the results are consistently better
or identical when comparing the stack sizes in this function, though
some architectures (notable x86) have schedule-insns disabled by
default.

The four columns are:
default: -O2
press:	 -O2 -fsched-pressure
nopress: -O2 -fschedule-insns -fno-sched-pressure
nosched: -O2 -no-schedule-insns (disables sched-pressure)

				default	press	nopress	nosched
alpha-linux-gcc-4.9.3		1136	848	1136	176
am33_2.0-linux-gcc-4.9.3	2100	2076	2100	2104
arm-linux-gnueabi-gcc-4.9.3	848	848	1048	352
cris-linux-gcc-4.9.3		272	272	272	272
frv-linux-gcc-4.9.3		1128	1000	1128	280
hppa64-linux-gcc-4.9.3		1128	336	1128	184
hppa-linux-gcc-4.9.3		644	308	644	276
i386-linux-gcc-4.9.3		352	352	352	352
m32r-linux-gcc-4.9.3		720	656	720	268
microblaze-linux-gcc-4.9.3	1108	604	1108	256
mips64-linux-gcc-4.9.3		1328	592	1328	208
mips-linux-gcc-4.9.3		1096	624	1096	240
powerpc64-linux-gcc-4.9.3	1088	432	1088	160
powerpc-linux-gcc-4.9.3		1080	584	1080	224
s390-linux-gcc-4.9.3		456	456	624	360
sh3-linux-gcc-4.9.3		292	292	292	292
sparc64-linux-gcc-4.9.3		992	240	992	208
sparc-linux-gcc-4.9.3		680	592	680	312
x86_64-linux-gcc-4.9.3		224	240	272	224
xtensa-linux-gcc-4.9.3		1152	704	1152	304

aarch64-linux-gcc-7.0.0		224	224	1104	208
arm-linux-gnueabi-gcc-7.0.1	824	824	1048	352
mips-linux-gcc-7.0.0		1120	648	1120	272
x86_64-linux-gcc-7.0.1		240	240	304	240

arm-linux-gnueabi-gcc-4.4.7	840			392
arm-linux-gnueabi-gcc-4.5.4	784	728	784	320
arm-linux-gnueabi-gcc-4.6.4	736	728	736	304
arm-linux-gnueabi-gcc-4.7.4	944	784	944	352
arm-linux-gnueabi-gcc-4.8.5	464	464	760	352
arm-linux-gnueabi-gcc-4.9.3	848	848	1048	352
arm-linux-gnueabi-gcc-5.3.1	824	824	1064	336
arm-linux-gnueabi-gcc-6.1.1	808	808	1056	344
arm-linux-gnueabi-gcc-7.0.1	824	824	1048	352

Trying the same test for serpent-generic, the picture is a bit different,
and while -fno-schedule-insns is generally better here than the default,
-fsched-pressure wins overall, so I picked that instead.

				default	press	nopress	nosched
alpha-linux-gcc-4.9.3		1392	864	1392	960
am33_2.0-linux-gcc-4.9.3	536	524	536	528
arm-linux-gnueabi-gcc-4.9.3	552	552	776	536
cris-linux-gcc-4.9.3		528	528	528	528
frv-linux-gcc-4.9.3		536	400	536	504
hppa64-linux-gcc-4.9.3		524	208	524	480
hppa-linux-gcc-4.9.3		768	472	768	508
i386-linux-gcc-4.9.3		564	564	564	564
m32r-linux-gcc-4.9.3		712	576	712	532
microblaze-linux-gcc-4.9.3	724	392	724	512
mips64-linux-gcc-4.9.3		720	384	720	496
mips-linux-gcc-4.9.3		728	384	728	496
powerpc64-linux-gcc-4.9.3	704	304	704	480
powerpc-linux-gcc-4.9.3		704	296	704	480
s390-linux-gcc-4.9.3		560	560	592	536
sh3-linux-gcc-4.9.3		540	540	540	540
sparc64-linux-gcc-4.9.3		544	352	544	496
sparc-linux-gcc-4.9.3		544	344	544	496
x86_64-linux-gcc-4.9.3		528	536	576	528
xtensa-linux-gcc-4.9.3		752	544	752	544

aarch64-linux-gcc-7.0.0		432	432	656	480
arm-linux-gnueabi-gcc-7.0.1	616	616	808	536
mips-linux-gcc-7.0.0		720	464	720	488
x86_64-linux-gcc-7.0.1		536	528	600	536

arm-linux-gnueabi-gcc-4.4.7	592			440
arm-linux-gnueabi-gcc-4.5.4	776	448	776	544
arm-linux-gnueabi-gcc-4.6.4	776	448	776	544
arm-linux-gnueabi-gcc-4.7.4	768	448	768	544
arm-linux-gnueabi-gcc-4.8.5	488	488	776	544
arm-linux-gnueabi-gcc-4.9.3	552	552	776	536
arm-linux-gnueabi-gcc-5.3.1	552	552	776	536
arm-linux-gnueabi-gcc-6.1.1	560	560	776	536
arm-linux-gnueabi-gcc-7.0.1	616	616	808	536

I did not do any runtime tests with serpent, so it is possible that stack
frame size does not directly correlate with runtime performance here and
it actually makes things worse, but it's more likely to help here, and
the reduced stack frame size is probably enough reason to apply the patch,
especially given that the crypto code is often used in deep call chains.

Link: https://kernelci.org/build/id/58797d7559b5149efdf6c3a9/logs/
Link: http://www.larc.usp.br/~pbarreto/WhirlpoolPage.html
Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=11488
Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79149
Cc: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
---
 crypto/Makefile | 2 ++
 1 file changed, 2 insertions(+)

--- a/crypto/Makefile
+++ b/crypto/Makefile
@@ -47,6 +47,7 @@ obj-$(CONFIG_CRYPTO_SHA1) += sha1_generi
 obj-$(CONFIG_CRYPTO_SHA256) += sha256_generic.o
 obj-$(CONFIG_CRYPTO_SHA512) += sha512_generic.o
 obj-$(CONFIG_CRYPTO_WP512) += wp512.o
+CFLAGS_wp512.o := $(call cc-option,-fno-schedule-insns)  # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79149
 obj-$(CONFIG_CRYPTO_TGR192) += tgr192.o
 obj-$(CONFIG_CRYPTO_GF128MUL) += gf128mul.o
 obj-$(CONFIG_CRYPTO_ECB) += ecb.o
@@ -67,6 +68,7 @@ obj-$(CONFIG_CRYPTO_BLOWFISH_COMMON) +=
 obj-$(CONFIG_CRYPTO_TWOFISH) += twofish_generic.o
 obj-$(CONFIG_CRYPTO_TWOFISH_COMMON) += twofish_common.o
 obj-$(CONFIG_CRYPTO_SERPENT) += serpent_generic.o
+CFLAGS_serpent_generic.o := $(call cc-option,-fsched-pressure)  # https://gcc.gnu.org/bugzilla/show_bug.cgi?id=79149
 obj-$(CONFIG_CRYPTO_AES) += aes_generic.o
 obj-$(CONFIG_CRYPTO_CAMELLIA) += camellia_generic.o
 obj-$(CONFIG_CRYPTO_CAST_COMMON) += cast_common.o

[toc] | [prev] | [next] | [standalone]

#1614571

FromGuenter Roeck <linux@roeck-us.net>
Date2017-04-01 19:50 +0200
Message-ID<trvjX-5RV-9@gated-at.bofh.it>
In reply to#1614525
On 04/01/2017 06:17 AM, Ben Hutchings wrote:
> This is the start of the stable review cycle for the 3.16.43 release.
> There are 19 patches in this series, which will be posted as responses
> to this one.  If anyone has any issues with these being applied, please
> let me know.
>
> Responses should be made by Tue Apr 04 00:00:00 UTC 2017.
> Anything received after that time might be too late.
>

Build results:
	total: 140 pass: 126 fail: 14
Failed builds:
     binutils 2.22:
	mips:defconfig
	mips:allnoconfig
     binutils 2.24:
	mips:defconfig
	mips:allmodconfig
	mips:allnoconfig
	mips:bcm47xx_defconfig
	mips:bcm63xx_defconfig
	mips:nlm_xlp_defconfig
	mips:ath79_defconfig
	mips:ar7_defconfig
	mips:e55_defconfig
	mips:cavium_octeon_defconfig
	mips:malta_defconfig
	mips:rt305x_defconfig

Qemu test results:
	total: 107 pass: 98 fail: 9
Failed tests:
	mips:malta_defconfig:nosmp
	mips:malta_defconfig:smp
	mips64:malta_defconfig:nosmp
	mips64:malta_defconfig:smp
	mipsel:24Kf:malta_defconfig:nosmp
	mipsel:24Kf:malta_defconfig:smp
	mipsel64:malta_defconfig:nosmp
	mipsel64:malta_defconfig:smp
	mipsel64:fuloong2e_defconfig:fulong2e

I tried to build mips:allnoconfig with the following binutils versions.
They all fail with the same errors.
	2.22 (from Poky version 1.3)
	2.22 (kernel toolchain, gcc 4.6.3)
	2.24 (kernel toolchain, gcc 4.9.0)
	2.26.1 (buildroot toolchain, gcc 5.4.0)

Bisect points to commit c4cf8e3a3e8f as the culprit.

Details are available at http://kerneltests.org/builders.
Unfortunately, just reverting this one patch doesn't work.
Reverting

f1ece3b9dd5e MIPS: Fix build with binutils 2.24.51+
f8547d2f97c8 MIPS: init upper 64b of vector registers when MSA is first used
c4cf8e3a3e8f MIPS: save/restore MSACSR register on context switch

fixes the problem, at least for an allnoconfig build with binutils 2.24.

Guenter

[toc] | [prev] | [next] | [standalone]

#1614612

FromBen Hutchings <ben@decadent.org.uk>
Date2017-04-02 00:50 +0200
Message-ID<trA0i-oR-11@gated-at.bofh.it>
In reply to#1614571

[Multipart message — attachments visible in raw view] — view raw

On Sat, 2017-04-01 at 10:43 -0700, Guenter Roeck wrote:
[snip list of MIPS failures]
> I tried to build mips:allnoconfig with the following binutils versions.
> They all fail with the same errors.
> 	2.22 (from Poky version 1.3)
> 	2.22 (kernel toolchain, gcc 4.6.3)
> 	2.24 (kernel toolchain, gcc 4.9.0)
> 	2.26.1 (buildroot toolchain, gcc 5.4.0)
> 
> Bisect points to commit c4cf8e3a3e8f as the culprit.
> 
> > Details are available at http://kerneltests.org/builders.
> Unfortunately, just reverting this one patch doesn't work.
> Reverting
> 
> f1ece3b9dd5e MIPS: Fix build with binutils 2.24.51+
> f8547d2f97c8 MIPS: init upper 64b of vector registers when MSA is first used
> c4cf8e3a3e8f MIPS: save/restore MSACSR register on context switch
> 
> fixes the problem, at least for an allnoconfig build with binutils 2.24.

I've now tested with binutils 2.25 and 2.28 and added these:

558155a0a731 MIPS: allow msa.h to be included in assembly files
631afc65e8f4 MIPS: Push .set mips64r* into the functions needing it
f23ce3883a30 MIPS: assume at as source/dest of MSA copy/insert instructions
a3a49810c55e MIPS: remove MSA macro recursion
e1bebbab1eae MIPS: wrap cfcmsa & ctcmsa accesses for toolchains with MSA support

which resolve the build regressions for these versions at least.

I can't build a MIPS allnoconfig with binutils 2.25, but selecting the
Malta platform instead of IP22 works.  This is not a regression and is
apparently due to a binutils bug; see commit ae2f5e5ed04a.  I could
pick that workaround for the next cycle.

Ben.

-- 
Ben Hutchings
It is easier to change the specification to fit the program than vice
versa.

[toc] | [prev] | [next] | [standalone]

#1614624

FromGuenter Roeck <linux@roeck-us.net>
Date2017-04-02 04:30 +0200
Message-ID<trDrc-2K1-5@gated-at.bofh.it>
In reply to#1614612
On 04/01/2017 03:40 PM, Ben Hutchings wrote:
> On Sat, 2017-04-01 at 10:43 -0700, Guenter Roeck wrote:
> [snip list of MIPS failures]
>> I tried to build mips:allnoconfig with the following binutils versions.
>> They all fail with the same errors.
>> 	2.22 (from Poky version 1.3)
>> 	2.22 (kernel toolchain, gcc 4.6.3)
>> 	2.24 (kernel toolchain, gcc 4.9.0)
>> 	2.26.1 (buildroot toolchain, gcc 5.4.0)
>>
>> Bisect points to commit c4cf8e3a3e8f as the culprit.
>>
>>> Details are available at http://kerneltests.org/builders.
>> Unfortunately, just reverting this one patch doesn't work.
>> Reverting
>>
>> f1ece3b9dd5e MIPS: Fix build with binutils 2.24.51+
>> f8547d2f97c8 MIPS: init upper 64b of vector registers when MSA is first used
>> c4cf8e3a3e8f MIPS: save/restore MSACSR register on context switch
>>
>> fixes the problem, at least for an allnoconfig build with binutils 2.24.
>
> I've now tested with binutils 2.25 and 2.28 and added these:
>
> 558155a0a731 MIPS: allow msa.h to be included in assembly files
> 631afc65e8f4 MIPS: Push .set mips64r* into the functions needing it
> f23ce3883a30 MIPS: assume at as source/dest of MSA copy/insert instructions
> a3a49810c55e MIPS: remove MSA macro recursion
> e1bebbab1eae MIPS: wrap cfcmsa & ctcmsa accesses for toolchains with MSA support
>
> which resolve the build regressions for these versions at least.
>
> I can't build a MIPS allnoconfig with binutils 2.25, but selecting the
> Malta platform instead of IP22 works.  This is not a regression and is
> apparently due to a binutils bug; see commit ae2f5e5ed04a.  I could
> pick that workaround for the next cycle.
>
> Ben.
>

Hi Ben,

I switched to use binutils 2.26.1 for the qemu tests. With that, we are down to:

Build results:
	total: 140 pass: 137 fail: 3
Failed builds:
     binutils 2.24:
	mips:ath79_defconfig
	mips:malta_defconfig
	mips:rt305x_defconfig

with the following failures:

{standard input}: Assembler messages:
{standard input}:1376: Error: opcode not supported on this processor: mips32r2 (mips32r2) `ctc1 $2,$31'

Guenter

[toc] | [prev] | [next] | [standalone]

#1614626

FromBen Hutchings <ben@decadent.org.uk>
Date2017-04-02 04:50 +0200
Message-ID<trDKx-2Sh-1@gated-at.bofh.it>
In reply to#1614612

[Multipart message — attachments visible in raw view] — view raw

On Sat, 2017-04-01 at 23:40 +0100, Ben Hutchings wrote:
> On Sat, 2017-04-01 at 10:43 -0700, Guenter Roeck wrote:
> [snip list of MIPS failures]
> > I tried to build mips:allnoconfig with the following binutils versions.
> > They all fail with the same errors.
> > 	2.22 (from Poky version 1.3)
> > 	2.22 (kernel toolchain, gcc 4.6.3)
> > 	2.24 (kernel toolchain, gcc 4.9.0)
> > 	2.26.1 (buildroot toolchain, gcc 5.4.0)
> > 
> > Bisect points to commit c4cf8e3a3e8f as the culprit.
> > 
> > Details are available at http://kerneltests.org/builders.
> > 
> > Unfortunately, just reverting this one patch doesn't work.
> > Reverting
> > 
> > f1ece3b9dd5e MIPS: Fix build with binutils 2.24.51+
> > f8547d2f97c8 MIPS: init upper 64b of vector registers when MSA is first used
> > c4cf8e3a3e8f MIPS: save/restore MSACSR register on context switch
> > 
> > fixes the problem, at least for an allnoconfig build with binutils 2.24.
> 
> I've now tested with binutils 2.25 and 2.28 and added these:
> 
> 558155a0a731 MIPS: allow msa.h to be included in assembly files
> 631afc65e8f4 MIPS: Push .set mips64r* into the functions needing it
> f23ce3883a30 MIPS: assume at as source/dest of MSA copy/insert instructions
> a3a49810c55e MIPS: remove MSA macro recursion
> e1bebbab1eae MIPS: wrap cfcmsa & ctcmsa accesses for toolchains with MSA support
> 
> which resolve the build regressions for these versions at least.
[...]

Also added:

5e32033e14ca MIPS: mipsregs.h: Add write_32bit_cp1_register()
d76e9b9fc5de MIPS: traps: Fix inline asm ctc1 missing .set hardfloat

to address 3 remaining build failures on your build farm.

Ben.

-- 
Ben Hutchings
It is impossible to make anything foolproof because fools are so
ingenious.

[toc] | [prev] | [next] | [standalone]

#1614634 — [PATCH 3.16 00/26] 3.16.43-rc2 review

FromBen Hutchings <ben@decadent.org.uk>
Date2017-04-02 05:20 +0200
Subject[PATCH 3.16 00/26] 3.16.43-rc2 review
Message-ID<trEdz-3ia-3@gated-at.bofh.it>
In reply to#1614525
I've added several more patches for MIPS to the queue for this release,
which will be sent as replies to this message.

Responses should be made by Tue Apr 04 00:00:00 UTC 2017.
Anything received after that time might be too late.

A combined patch relative to 3.16.42 will be posted as an additional
response to this.  A shortlog and diffstat can be found below.

Ben.

-------------

Andre Przywara (1):
      fs/nfs: fix new compiler warning about boolean in switch
         [c7757074839f2cd440521482d76ea180d0d4bdac]

Arnd Bergmann (2):
      crypto: improve gcc optimization flags for serpent and wp512
         [7d6e9105026788c497f0ab32fa16c82f4ab5ff61]
      mmc: sunxi: avoid invalid pointer calculation
         [d34712d2e3db9b241d0484a6e3839c6b7ef9df78]

Ben Hutchings (1):
      keys: Guard against null match function in keyring_search_aux()
         [not upstream]

Eric W. Biederman (1):
      vfs: Commit to never having exectuables on proc and sysfs.
         [22f6b4d34fcf039c63a94e7670e0da24f8575a5a]

Fabio Estevam (1):
      serial: samsung: Use %pa to print 'resource_size_t' type
         [1ff5b64dccbf23acfe7993b9132b6992922a4756]

Florian Westphal (1):
      netlink: remove mmapped netlink support
         [d1b4c689d4130bcfd3532680b64db562300716b6]

James C Boyd (1):
      HID: hid-input: Add parentheses to quell gcc warning
         [09a5c34e8d6b05663ec4c3d22b1fbd9fec89aaf9]

James Hogan (2):
      MIPS: mipsregs.h: Add write_32bit_cp1_register()
         [5e32033e14ca9c7f7341cb383f5a05699b0b5382]
      MIPS: traps: Fix inline asm ctc1 missing .set hardfloat
         [d76e9b9fc5de7e8fc4fd0e72a94e8c723929ffea]

Jann Horn (1):
      aio: mark AIO pseudo-fs noexec
         [22f6b4d34fcf039c63a94e7670e0da24f8575a5a]

John Crispin (1):
      MIPS: ralink: Cosmetic change to prom_init().
         [9c48568b3692f1a56cbf1935e4eea835e6b185b1]

Linus Torvalds (1):
      blk: rq_data_dir() should not return a boolean
         [10fbd36e362a0f367e34a7cd876a81295d8fc5ca]

Manuel Lauss (1):
      MIPS: Fix build with binutils 2.24.51+
         [842dfc11ea9a21f9825167c8a4f2834b205b0a79]

Paul Burton (9):
      MIPS: Push .set mips64r* into the functions needing it
         [631afc65e8f4f845945ef9e90236d10cee601498]
      MIPS: allow msa.h to be included in assembly files
         [558155a0a731b4f56846559a57ca7ca921230497]
      MIPS: assume at as source/dest of MSA copy/insert instructions
         [f23ce3883a30743a5b779dc6fb90ca8620688a23]
      MIPS: init upper 64b of vector registers when MSA is first used
         [c9017757c532d48bf43d6e7d3b7282443ad4207b]
      MIPS: preserve scalar FP CSR when switching vector context
         [b83406735a4ae0aff4b614664d6a64a0fd6b9917]
      MIPS: remove MSA macro recursion
         [a3a49810c55e3489dfb5d72a9b2e41ab1db9ffb9]
      MIPS: save/disable MSA in lose_fpu
         [33c771ba5c5d067f85a5a6c4b11047219b5b8f4e]
      MIPS: save/restore MSACSR register on context switch
         [f7a46fa7bb0047d3e226702a0c4b786862fe6843]
      MIPS: wrap cfcmsa & ctcmsa accesses for toolchains with MSA support
         [e1bebbab1eaecac77d77033010b5e0f51b737e64]

Ralf Baechle (1):
      MIPS: Zero variable read by get_user / __get_user in case of an error.
         [640465bda58c7078725201be7430c31a349121e9]

Tillmann Heidsieck (1):
      atm: iphase: fix misleading indention
         [cbb41b91e68a302087762823136c9067138cff7c]

Tim Gardner (1):
      fs: namespace: suppress 'may be used uninitialized' warnings
         [b8850d1fa8e2f6653e57daf6d08e58c5f5eb2c85]

 Documentation/networking/netlink_mmap.txt | 339 --------------
 Makefile                                  |   4 +-
 arch/mips/Makefile                        |   9 +
 arch/mips/include/asm/asmmacro-32.h       |   6 +
 arch/mips/include/asm/asmmacro.h          | 129 +++++-
 arch/mips/include/asm/fpregdef.h          |  14 +
 arch/mips/include/asm/fpu.h               |  15 +-
 arch/mips/include/asm/mipsregs.h          |  11 +-
 arch/mips/include/asm/msa.h               |  23 +-
 arch/mips/include/asm/uaccess.h           |   5 +-
 arch/mips/kernel/asm-offsets.c            |   1 +
 arch/mips/kernel/branch.c                 |   8 +-
 arch/mips/kernel/genex.S                  |   1 +
 arch/mips/kernel/r2300_fpu.S              |   6 +
 arch/mips/kernel/r2300_switch.S           |   5 +
 arch/mips/kernel/r4k_fpu.S                |  29 +-
 arch/mips/kernel/r4k_switch.S             |  24 +-
 arch/mips/kernel/r6000_fpu.S              |   5 +
 arch/mips/kernel/traps.c                  |  39 +-
 arch/mips/math-emu/cp1emu.c               |   6 +-
 arch/mips/ralink/prom.c                   |   9 +-
 crypto/Makefile                           |   2 +
 drivers/atm/iphase.c                      |   2 +-
 drivers/hid/hid-input.c                   |   2 +-
 drivers/mmc/host/sunxi-mmc.c              |   5 +-
 drivers/tty/serial/samsung.c              |   4 +-
 fs/aio.c                                  |   1 +
 fs/compat.c                               |  10 +-
 fs/exec.c                                 |  10 +-
 fs/internal.h                             |   2 +-
 fs/namespace.c                            |  26 +-
 fs/nfs/nfs4proc.c                         |  11 +-
 fs/open.c                                 |   2 +-
 fs/proc/root.c                            |   2 +-
 fs/sysfs/mount.c                          |   3 +-
 include/linux/blkdev.h                    |   2 +-
 include/linux/fs.h                        |   3 +
 include/uapi/linux/netlink.h              |   4 +
 include/uapi/linux/netlink_diag.h         |   2 +
 kernel/sys.c                              |   3 +-
 mm/mmap.c                                 |   4 +-
 mm/nommu.c                                |   2 +-
 net/netlink/Kconfig                       |   9 -
 net/netlink/af_netlink.c                  | 738 +-----------------------------
 net/netlink/af_netlink.h                  |  15 -
 net/netlink/diag.c                        |  39 --
 security/keys/keyring.c                   |   6 +-
 security/security.c                       |   2 +-
 48 files changed, 352 insertions(+), 1247 deletions(-)

-- 
Ben Hutchings
It is impossible to make anything foolproof because fools are so ingenious.

[toc] | [prev] | [next] | [standalone]

#1614635 — [PATCH 3.16 23/26] MIPS: Push .set mips64r* into the functions needing it

FromBen Hutchings <ben@decadent.org.uk>
Date2017-04-02 05:20 +0200
Subject[PATCH 3.16 23/26] MIPS: Push .set mips64r* into the functions needing it
Message-ID<trEdA-3ia-13@gated-at.bofh.it>
In reply to#1614634
3.16.43-rc2 review patch.  If anyone has any objections, please let me know.

------------------

From: Paul Burton <paul.burton@imgtec.com>

commit 631afc65e8f4f845945ef9e90236d10cee601498 upstream.

The {save,restore}_fp_context{,32} functions require that the assembler
allows the use of sdc instructions on any FP register, and this is
acomplished by setting the arch to mips64r2 or mips64r6
(using MIPS_ISA_ARCH_LEVEL_RAW).

However this has the effect of enabling the assembler to use mips64
instructions in the expansion of pseudo-instructions. This was done in
the (now-reverted) commit eec43a224cf1 "MIPS: Save/restore MSA context
around signals" which led to my mistakenly believing that there was an
assembler bug, when in reality the assembler was just emitting mips64
instructions. Avoid the issue for future commits which will add code to
r4k_fpu.S by pushing the .set MIPS_ISA_ARCH_LEVEL_RAW directives into
the functions that require it, and remove the spurious assertion
declaring the assembler bug.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
[james.hogan@imgtec.com: Rebase on v4.0-rc1 and reword commit message to
 reflect use of MIPS_ISA_ARCH_LEVEL_RAW]
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9612/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
[bwh: Backported to 3.16: in r4k_fpu.S, keep using arch=r4000]
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
---
 arch/mips/include/asm/asmmacro.h | 12 ++++--------
 arch/mips/kernel/r4k_fpu.S       |  2 +-
 2 files changed, 5 insertions(+), 9 deletions(-)

--- a/arch/mips/include/asm/asmmacro.h
+++ b/arch/mips/include/asm/asmmacro.h
@@ -324,8 +324,7 @@
 	SET_HARDFLOAT
 	.insn
 	.word	COPY_UW_MSA_INSN | (\n << 16) | (\ws << 11)
-	/* move triggers an assembler bug... */
-	or	\rd, $1, zero
+	move	\rd, $1
 	.set	pop
 	.endm
 
@@ -335,8 +334,7 @@
 	SET_HARDFLOAT
 	.insn
 	.word	COPY_UD_MSA_INSN | (\n << 16) | (\ws << 11)
-	/* move triggers an assembler bug... */
-	or	\rd, $1, zero
+	move	\rd, $1
 	.set	pop
 	.endm
 
@@ -344,8 +342,7 @@
 	.set	push
 	.set	noat
 	SET_HARDFLOAT
-	/* move triggers an assembler bug... */
-	or	$1, \rs, zero
+	move	$1, \rs
 	.word	INSERT_W_MSA_INSN | (\n << 16) | (\wd << 6)
 	.set	pop
 	.endm
@@ -354,8 +351,7 @@
 	.set	push
 	.set	noat
 	SET_HARDFLOAT
-	/* move triggers an assembler bug... */
-	or	$1, \rs, zero
+	move	$1, \rs
 	.word	INSERT_D_MSA_INSN | (\n << 16) | (\wd << 6)
 	.set	pop
 	.endm
--- a/arch/mips/kernel/r4k_fpu.S
+++ b/arch/mips/kernel/r4k_fpu.S
@@ -34,7 +34,6 @@
 	.endm
 
 	.set	noreorder
-	.set	arch=r4000
 
 LEAF(_save_fp_context)
 	.set	push
@@ -102,6 +101,7 @@ LEAF(_save_fp_context)
 	/* Save 32-bit process floating point context */
 LEAF(_save_fp_context32)
 	.set push
+	.set arch=r4000
 	SET_HARDFLOAT
 	cfc1	t1, fcr31

[toc] | [prev] | [next] | [standalone]

#1614636 — [PATCH 3.16 24/26] MIPS: assume at as source/dest of MSA copy/insert instructions

FromBen Hutchings <ben@decadent.org.uk>
Date2017-04-02 05:20 +0200
Subject[PATCH 3.16 24/26] MIPS: assume at as source/dest of MSA copy/insert instructions
Message-ID<trEdA-3ia-19@gated-at.bofh.it>
In reply to#1614634
3.16.43-rc2 review patch.  If anyone has any objections, please let me know.

------------------

From: Paul Burton <paul.burton@imgtec.com>

commit f23ce3883a30743a5b779dc6fb90ca8620688a23 upstream.

Assuming at ($1) as the source or destination register of copy or
insert instructions:

  - Simplifies the macros providing those instructions for toolchains
    without MSA support.

  - Avoids an unnecessary move instruction when at is used as the source
    or destination register anyway.

  - Is sufficient for the uses to be introduced in the kernel by a
    subsequent patch.

Note that due to a patch ordering snafu on my part this also fixes the
currently broken build with MSA support enabled. The build has been
broken since commit c9017757c532 "MIPS: init upper 64b of vector
registers when MSA is first used", which this patch should have
preceeded.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9161/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
---
 arch/mips/include/asm/asmmacro.h | 28 ++++++++++++----------------
 1 file changed, 12 insertions(+), 16 deletions(-)

--- a/arch/mips/include/asm/asmmacro.h
+++ b/arch/mips/include/asm/asmmacro.h
@@ -225,35 +225,35 @@
 	.set	pop
 	.endm
 
-	.macro	copy_u_w	rd, ws, n
+	.macro	copy_u_w	ws, n
 	.set	push
 	.set	mips32r2
 	.set	msa
-	copy_u.w \rd, $w\ws[\n]
+	copy_u.w $1, $w\ws[\n]
 	.set	pop
 	.endm
 
-	.macro	copy_u_d	rd, ws, n
+	.macro	copy_u_d	ws, n
 	.set	push
 	.set	mips64r2
 	.set	msa
-	copy_u.d \rd, $w\ws[\n]
+	copy_u.d $1, $w\ws[\n]
 	.set	pop
 	.endm
 
-	.macro	insert_w	wd, n, rs
+	.macro	insert_w	wd, n
 	.set	push
 	.set	mips32r2
 	.set	msa
-	insert.w $w\wd[\n], \rs
+	insert.w $w\wd[\n], $1
 	.set	pop
 	.endm
 
-	.macro	insert_d	wd, n, rs
+	.macro	insert_d	wd, n
 	.set	push
 	.set	mips64r2
 	.set	msa
-	insert.d $w\wd[\n], \rs
+	insert.d $w\wd[\n], $1
 	.set	pop
 	.endm
 #else
@@ -318,40 +318,36 @@
 	.set	pop
 	.endm
 
-	.macro	copy_u_w	rd, ws, n
+	.macro	copy_u_w	ws, n
 	.set	push
 	.set	noat
 	SET_HARDFLOAT
 	.insn
 	.word	COPY_UW_MSA_INSN | (\n << 16) | (\ws << 11)
-	move	\rd, $1
 	.set	pop
 	.endm
 
-	.macro	copy_u_d	rd, ws, n
+	.macro	copy_u_d	ws, n
 	.set	push
 	.set	noat
 	SET_HARDFLOAT
 	.insn
 	.word	COPY_UD_MSA_INSN | (\n << 16) | (\ws << 11)
-	move	\rd, $1
 	.set	pop
 	.endm
 
-	.macro	insert_w	wd, n, rs
+	.macro	insert_w	wd, n
 	.set	push
 	.set	noat
 	SET_HARDFLOAT
-	move	$1, \rs
 	.word	INSERT_W_MSA_INSN | (\n << 16) | (\wd << 6)
 	.set	pop
 	.endm
 
-	.macro	insert_d	wd, n, rs
+	.macro	insert_d	wd, n
 	.set	push
 	.set	noat
 	SET_HARDFLOAT
-	move	$1, \rs
 	.word	INSERT_D_MSA_INSN | (\n << 16) | (\wd << 6)
 	.set	pop
 	.endm

[toc] | [prev] | [next] | [standalone]

#1614637 — [PATCH 3.16 26/26] MIPS: wrap cfcmsa & ctcmsa accesses for toolchains with MSA support

FromBen Hutchings <ben@decadent.org.uk>
Date2017-04-02 05:20 +0200
Subject[PATCH 3.16 26/26] MIPS: wrap cfcmsa & ctcmsa accesses for toolchains with MSA support
Message-ID<trEdA-3ia-21@gated-at.bofh.it>
In reply to#1614634
3.16.43-rc2 review patch.  If anyone has any objections, please let me know.

------------------

From: Paul Burton <paul.burton@imgtec.com>

commit e1bebbab1eaecac77d77033010b5e0f51b737e64 upstream.

Uses of the cfcmsa & ctcmsa instructions were not being wrapped by a
macro in the case where the toolchain supports MSA, since the arguments
exactly match a typical use of the instructions. However using current
toolchains this leads to errors such as:

  arch/mips/kernel/genex.S:437: Error: opcode not supported on this processor: mips32r2 (mips32r2) `cfcmsa $5,1'

Thus uses of the instructions must be in the context of a ".set msa"
directive, however doing that from the users of the instructions would
be messy due to the possibility that the toolchain does not support
MSA. Fix this by renaming the macros (prepending an underscore) in order
to avoid recursion when attempting to emit the instructions, and provide
implementations for the TOOLCHAIN_SUPPORTS_MSA case which ".set msa" as
appropriate.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9163/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
---
 arch/mips/include/asm/asmmacro.h | 24 ++++++++++++++++++++----
 1 file changed, 20 insertions(+), 4 deletions(-)

--- a/arch/mips/include/asm/asmmacro.h
+++ b/arch/mips/include/asm/asmmacro.h
@@ -209,6 +209,22 @@
 	.endm
 
 #ifdef TOOLCHAIN_SUPPORTS_MSA
+	.macro	_cfcmsa	rd, cs
+	.set	push
+	.set	mips32r2
+	.set	msa
+	cfcmsa	\rd, $\cs
+	.set	pop
+	.endm
+
+	.macro	_ctcmsa	cd, rs
+	.set	push
+	.set	mips32r2
+	.set	msa
+	ctcmsa	$\cd, \rs
+	.set	pop
+	.endm
+
 	.macro	ld_d	wd, off, base
 	.set	push
 	.set	mips32r2
@@ -281,7 +297,7 @@
 	/*
 	 * Temporary until all toolchains in use include MSA support.
 	 */
-	.macro	cfcmsa	rd, cs
+	.macro	_cfcmsa	rd, cs
 	.set	push
 	.set	noat
 	SET_HARDFLOAT
@@ -291,7 +307,7 @@
 	.set	pop
 	.endm
 
-	.macro	ctcmsa	cd, rs
+	.macro	_ctcmsa	cd, rs
 	.set	push
 	.set	noat
 	SET_HARDFLOAT
@@ -389,7 +405,7 @@
 	.set	push
 	.set	noat
 	SET_HARDFLOAT
-	cfcmsa	$1, MSA_CSR
+	_cfcmsa	$1, MSA_CSR
 	sw	$1, THREAD_MSA_CSR(\thread)
 	.set	pop
 	.endm
@@ -399,7 +415,7 @@
 	.set	noat
 	SET_HARDFLOAT
 	lw	$1, THREAD_MSA_CSR(\thread)
-	ctcmsa	MSA_CSR, $1
+	_ctcmsa	MSA_CSR, $1
 	.set	pop
 	ld_d	0, THREAD_FPR0, \thread
 	ld_d	1, THREAD_FPR1, \thread

[toc] | [prev] | [standalone]

Back to top | Article view | linux.kernel

csiph-web