Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]
Groups > linux.kernel > #1605472 > unrolled thread
| Started by | <sean.wang@mediatek.com> |
|---|---|
| First post | 2017-03-21 10:40 +0100 |
| Last post | 2017-03-28 09:00 +0200 |
| Articles | 3 on this page of 23 — 7 participants |
Back to article view | Back to linux.kernel
[PATCH net-next v2 0/5] net-next: dsa: add Mediatek MT7530 support <sean.wang@mediatek.com> - 2017-03-21 10:40 +0100
[PATCH net-next v2 1/5] dt-bindings: net: dsa: add Mediatek MT7530 binding <sean.wang@mediatek.com> - 2017-03-21 10:40 +0100
Re: [PATCH net-next v2 1/5] dt-bindings: net: dsa: add Mediatek MT7530 binding Rob Herring <robh@kernel.org> - 2017-03-24 17:20 +0100
[PATCH net-next v2 3/5] net-next: ethernet: mediatek: add CDM able to recognize the tag for DSA <sean.wang@mediatek.com> - 2017-03-21 10:50 +0100
Re: [PATCH net-next v2 3/5] net-next: ethernet: mediatek: add CDM able to recognize the tag for DSA Andrew Lunn <andrew@lunn.ch> - 2017-03-22 18:50 +0100
Re: [PATCH net-next v2 3/5] net-next: ethernet: mediatek: add CDM able to recognize the tag for DSA Florian Fainelli <f.fainelli@gmail.com> - 2017-03-22 19:30 +0100
[PATCH net-next v2 4/5] net-next: ethernet: mediatek: add device_node of GMAC pointing into the netdev instance <sean.wang@mediatek.com> - 2017-03-21 10:50 +0100
Re: [PATCH net-next v2 4/5] net-next: ethernet: mediatek: add device_node of GMAC pointing into the netdev instance Andrew Lunn <andrew@lunn.ch> - 2017-03-22 19:20 +0100
Re: [PATCH net-next v2 4/5] net-next: ethernet: mediatek: add device_node of GMAC pointing into the netdev instance Florian Fainelli <f.fainelli@gmail.com> - 2017-03-22 19:30 +0100
[PATCH net-next v2 2/5] net-next: dsa: add Mediatek tag RX/TX handler <sean.wang@mediatek.com> - 2017-03-21 10:50 +0100
Re: [PATCH net-next v2 5/5] net-next: dsa: add dsa support for Mediatek MT7530 switch Florian Fainelli <f.fainelli@gmail.com> - 2017-03-22 19:40 +0100
Re: [PATCH net-next v2 5/5] net-next: dsa: add dsa support for Mediatek MT7530 switch Sean Wang <sean.wang@mediatek.com> - 2017-03-28 08:00 +0200
Re: [PATCH net-next v2 5/5] net-next: dsa: add dsa support for Mediatek MT7530 switch Andrew Lunn <andrew@lunn.ch> - 2017-03-22 19:40 +0100
Re: [PATCH net-next v2 5/5] net-next: dsa: add dsa support for Mediatek MT7530 switch Andrew Lunn <andrew@lunn.ch> - 2017-03-23 08:50 +0100
Re: [PATCH net-next v2 5/5] net-next: dsa: add dsa support for Mediatek MT7530 switch Sean Wang <sean.wang@mediatek.com> - 2017-03-23 09:10 +0100
Re: [PATCH net-next v2 5/5] net-next: dsa: add dsa support for Mediatek MT7530 switch Felix Fietkau <nbd@nbd.name> - 2017-03-23 15:10 +0100
Re: [PATCH net-next v2 5/5] net-next: dsa: add dsa support for Mediatek MT7530 switch John Crispin <john@phrozen.org> - 2017-03-23 15:30 +0100
Re: [PATCH net-next v2 5/5] net-next: dsa: add dsa support for Mediatek MT7530 switch Felix Fietkau <nbd@nbd.name> - 2017-03-23 15:40 +0100
Re: [PATCH net-next v2 5/5] net-next: dsa: add dsa support for Mediatek MT7530 switch Andrew Lunn <andrew@lunn.ch> - 2017-03-24 09:00 +0100
Re: [PATCH net-next v2 5/5] net-next: dsa: add dsa support for Mediatek MT7530 switch Andrew Lunn <andrew@lunn.ch> - 2017-03-24 15:10 +0100
Re: [PATCH net-next v2 5/5] net-next: dsa: add dsa support for Mediatek MT7530 switch Sean Wang <sean.wang@mediatek.com> - 2017-03-28 08:10 +0200
Re: [PATCH net-next v2 5/5] net-next: dsa: add dsa support for Mediatek MT7530 switch Andrew Lunn <andrew@lunn.ch> - 2017-03-24 15:30 +0100
Re: [PATCH net-next v2 5/5] net-next: dsa: add dsa support for Mediatek MT7530 switch Sean Wang <sean.wang@mediatek.com> - 2017-03-28 09:00 +0200
Page 2 of 2 — ← Prev page 1 [2]
| From | Sean Wang <sean.wang@mediatek.com> |
|---|---|
| Date | 2017-03-28 08:10 +0200 |
| Subject | Re: [PATCH net-next v2 5/5] net-next: dsa: add dsa support for Mediatek MT7530 switch |
| Message-ID | <tpSum-3pJ-17@gated-at.bofh.it> |
| In reply to | #1608426 |
Hi Andrew,
Add comment as below inline
On Fri, 2017-03-24 at 15:02 +0100, Andrew Lunn wrote:
> Hi Sean
>
> > + regmap = devm_regmap_init(ds->dev, NULL, priv,
> > + &mt7530_regmap_config);
> > + if (IS_ERR(regmap))
> > + dev_warn(priv->dev, "phy regmap initialization failed");
> > +
>
> Shouldn't this be a fatal error? If you keep going when there is an
> error, what happens when you actually try to use the regmap?
>
Initial thought is that it is just for debugging purpose so if it fails,
it should break any functionality of switch and only have implication as
a warning message.
Anyway, i will remove it in the next one since it seems better being
kept in private place as you suggested in the previous mail.
> > + phy_mode = of_get_phy_mode(ds->ports[ds->dst->cpu_port].dn);
> > + if (phy_mode < 0) {
> > + dev_err(priv->dev, "Can't find phy-mode for master device\n");
> > + return phy_mode;
> > + }
> > + dev_info(priv->dev, "phy-mode for master device = %x\n", phy_mode);
>
> dev_dbg?
>
Sorry. i forgot turned it into dev_dbg
> > +
> > + id = mt7530_read(priv, MT7530_CREV);
> > + id >>= CHIP_NAME_SHIFT;
> > + if (id != MT7530_ID)
> > + return -ENODEV;
>
> It might be helpful to say what ID has been found, if it is not the
> supported ID.
I will fix it up to make users know what was going on
thanks for taking your time on those reviewing again!
> Andrew
[toc] | [prev] | [next] | [standalone]
| From | Andrew Lunn <andrew@lunn.ch> |
|---|---|
| Date | 2017-03-24 15:30 +0100 |
| Subject | Re: [PATCH net-next v2 5/5] net-next: dsa: add dsa support for Mediatek MT7530 switch |
| Message-ID | <toyo3-2Pm-47@gated-at.bofh.it> |
| In reply to | #1605472 |
On Tue, Mar 21, 2017 at 05:35:10PM +0800, sean.wang@mediatek.com wrote:
Hi Sean
> + /* Lower Tx Driving */
> + for (i = 0 ; i < 6 ; i++)
Could MT7530_CPU_PORT be used here?
> + mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
> + TD_DM_DRVP(8) | TD_DM_DRVN(8));
> +
> + /* Setup MT7530 core clock */
> + if (!trgint) {
> + /* Disable MT7530 core clock */
> + core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
> +
> + /* Disable MT7530 PLL, since phy_device has not yet been
> + * created when this function is called. So we provide
> + * core_write_mmd_indirect to complete this function
> + */
> + core_write_mmd_indirect(priv,
> + CORE_GSWPLL_GRP1,
> + MDIO_MMD_VEND2,
> + 0);
> +
> + /* Setup MT7530 core clock into 500Mhz */
> + core_write(priv, CORE_GSWPLL_GRP2,
> + RG_GSWPLL_POSDIV_500M(1) |
> + RG_GSWPLL_FBKDIV_500M(25));
> +
> + /* Enable MT7530 PLL */
> + core_write(priv, CORE_GSWPLL_GRP1,
> + RG_GSWPLL_EN_PRE |
> + RG_GSWPLL_POSDIV_200M(2) |
> + RG_GSWPLL_FBKDIV_200M(32));
> +
> + /* Enable MT7530 core clock */
> + core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
> + }
> +
> + /* Setup the MT7530 TRGMII Tx Clock */
> + core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
> + core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
> + core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
> + core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
> + core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
> + core_write(priv, CORE_PLL_GROUP4,
> + RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
> + RG_SYSPLL_BIAS_LPF_EN);
> + core_write(priv, CORE_PLL_GROUP2,
> + RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
> + RG_SYSPLL_POSDIV(1));
> + core_write(priv, CORE_PLL_GROUP7,
> + RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
> + RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
> + core_set(priv, CORE_TRGMII_GSW_CLK_CG,
> + REG_GSWCK_EN | REG_TRGMIICK_EN);
> +
> + if (!trgint)
> + for (i = 0 ; i < 5 ; i++)
Why only 5 here? All other similar loops are to 6. Replacing 5 with a
#define might help make this more readable.
> + mt7530_rmw(priv, MT7530_TRGMII_RD(i),
> + RD_TAP_MASK, RD_TAP(16));
> + else
> + mt7623_trgmii_set(priv, GSW_INTF_MODE, INTF_MODE_TRGMII);
> +
> + return 0;
> +}
> +
> +static int
> +mt7623_pad_clk_setup(struct dsa_switch *ds)
> +{
> + struct mt7530_priv *priv = ds->priv;
> + int i;
> +
> + for (i = 0 ; i < 6; i++)
MT7530_CPU_PORT?
> +
> +/* Registers to mac forward conrol for unknown frames */
/conrol/control
> +
> +/* Registor for port control */
Register
> +/* Regiser for TOP signal control */
Register
> +/* struct mt7530_priv - This is the main datasructure for holding the state
data structure
> + * of the driver
> + * @dev: The device pointer
> + * @ds: The pointer to the dsa core structure
> + * @bus: The bus used for the device and built-in PHY
> + * @ethsys: The regmap used for enabling the necessary PLL
> + * @ethernet: The regmap used for access TRGMII-based registers
> + * @core_pwr: The power supplied into the core
> + * @io_pwr: The power supplied into the I/O
> + * @mcm: Flag for distinguishing if standalone IC or module
> + * coupling
> + * @reset: The descriptor for GPIO line tied to its reset pin
> + * @phy_mode: The xMII for cpu port used
> + * @ports: Holding the state amongs ports
among
Andrew
[toc] | [prev] | [next] | [standalone]
| From | Sean Wang <sean.wang@mediatek.com> |
|---|---|
| Date | 2017-03-28 09:00 +0200 |
| Subject | Re: [PATCH net-next v2 5/5] net-next: dsa: add dsa support for Mediatek MT7530 switch |
| Message-ID | <tpTgK-3Jy-3@gated-at.bofh.it> |
| In reply to | #1608487 |
Hi Andrew
On Fri, 2017-03-24 at 15:19 +0100, Andrew Lunn wrote:
> On Tue, Mar 21, 2017 at 05:35:10PM +0800, sean.wang@mediatek.com wrote:
>
> Hi Sean
>
> > + /* Lower Tx Driving */
> > + for (i = 0 ; i < 6 ; i++)
>
> Could MT7530_CPU_PORT be used here?
>
I should create meaningful definition instead of avoiding hard coding
where 6 should be corrected into 5 which is meant for the number for
control register to configure TRGMII path
> > + mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
> > + TD_DM_DRVP(8) | TD_DM_DRVN(8));
> > +
> > + /* Setup MT7530 core clock */
> > + if (!trgint) {
> > + /* Disable MT7530 core clock */
> > + core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
> > +
> > + /* Disable MT7530 PLL, since phy_device has not yet been
> > + * created when this function is called. So we provide
> > + * core_write_mmd_indirect to complete this function
> > + */
> > + core_write_mmd_indirect(priv,
> > + CORE_GSWPLL_GRP1,
> > + MDIO_MMD_VEND2,
> > + 0);
> > +
> > + /* Setup MT7530 core clock into 500Mhz */
> > + core_write(priv, CORE_GSWPLL_GRP2,
> > + RG_GSWPLL_POSDIV_500M(1) |
> > + RG_GSWPLL_FBKDIV_500M(25));
> > +
> > + /* Enable MT7530 PLL */
> > + core_write(priv, CORE_GSWPLL_GRP1,
> > + RG_GSWPLL_EN_PRE |
> > + RG_GSWPLL_POSDIV_200M(2) |
> > + RG_GSWPLL_FBKDIV_200M(32));
> > +
> > + /* Enable MT7530 core clock */
> > + core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
> > + }
> > +
> > + /* Setup the MT7530 TRGMII Tx Clock */
> > + core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
> > + core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
> > + core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
> > + core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
> > + core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
> > + core_write(priv, CORE_PLL_GROUP4,
> > + RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
> > + RG_SYSPLL_BIAS_LPF_EN);
> > + core_write(priv, CORE_PLL_GROUP2,
> > + RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
> > + RG_SYSPLL_POSDIV(1));
> > + core_write(priv, CORE_PLL_GROUP7,
> > + RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
> > + RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
> > + core_set(priv, CORE_TRGMII_GSW_CLK_CG,
> > + REG_GSWCK_EN | REG_TRGMIICK_EN);
> > +
> > + if (!trgint)
> > + for (i = 0 ; i < 5 ; i++)
>
> Why only 5 here? All other similar loops are to 6. Replacing 5 with a
> #define might help make this more readable.
the same as above, it should be corrected
> > + mt7530_rmw(priv, MT7530_TRGMII_RD(i),
> > + RD_TAP_MASK, RD_TAP(16));
> > + else
> > + mt7623_trgmii_set(priv, GSW_INTF_MODE, INTF_MODE_TRGMII);
> > +
> > + return 0;
> > +}
> > +
> > +static int
> > +mt7623_pad_clk_setup(struct dsa_switch *ds)
> > +{
> > + struct mt7530_priv *priv = ds->priv;
> > + int i;
> > +
> > + for (i = 0 ; i < 6; i++)
>
> MT7530_CPU_PORT?
the same as above , it should be corrected
> > +
> > +/* Registers to mac forward conrol for unknown frames */
>
> /conrol/control
>
will fix it up
> > +
> > +/* Registor for port control */
>
> Register
>
will fix it up
> > +/* Regiser for TOP signal control */
>
> Register
>
will fix it up
> > +/* struct mt7530_priv - This is the main datasructure for holding the state
>
> data structure
>
> > + * of the driver
> > + * @dev: The device pointer
> > + * @ds: The pointer to the dsa core structure
> > + * @bus: The bus used for the device and built-in PHY
> > + * @ethsys: The regmap used for enabling the necessary PLL
> > + * @ethernet: The regmap used for access TRGMII-based registers
> > + * @core_pwr: The power supplied into the core
> > + * @io_pwr: The power supplied into the I/O
> > + * @mcm: Flag for distinguishing if standalone IC or module
> > + * coupling
> > + * @reset: The descriptor for GPIO line tied to its reset pin
> > + * @phy_mode: The xMII for cpu port used
> > + * @ports: Holding the state amongs ports
>
> among
will fix it up
thank for your careful reviewing again!!
> Andrew
[toc] | [prev] | [standalone]
Page 2 of 2 — ← Prev page 1 [2]
Back to top | Article view | linux.kernel
csiph-web