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[PATCH v2 2/5] clk: meson-gxbb: Add GP0 PLL init parameters

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  [PATCH v2 2/5] clk: meson-gxbb: Add GP0 PLL init parameters Neil Armstrong <narmstrong@baylibre.com> - 2017-03-22 11:40 +0100

#1606338 — [PATCH v2 2/5] clk: meson-gxbb: Add GP0 PLL init parameters

Tha Amlogic GXBB SoC GP0 PLL needs some vendor provided parameters to be
initializated in the the GP0 control registers before configuring the rate
with the rate table provided parameters.

GXBB GP0 PLL tweaks are also selected to respect the vendor init procedure.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 drivers/clk/meson/gxbb.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index d07dc22..db95038 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -352,6 +352,13 @@
 	},
 };
 
+struct pll_params_table gxbb_gp0_params_table[] = {
+	PLL_PARAM(HHI_GP0_PLL_CNTL, 0x6a000228),
+	PLL_PARAM(HHI_GP0_PLL_CNTL2, 0x69c80000),
+	PLL_PARAM(HHI_GP0_PLL_CNTL3, 0x0a5590c4),
+	PLL_PARAM(HHI_GP0_PLL_CNTL4, 0x0000500d),
+};
+
 static struct meson_clk_pll gxbb_gp0_pll = {
 	.m = {
 		.reg_off = HHI_GP0_PLL_CNTL,
@@ -368,6 +375,12 @@
 		.shift   = 16,
 		.width   = 2,
 	},
+	.params = {
+		.params_table = gxbb_gp0_params_table,
+		.params_count =	ARRAY_SIZE(gxbb_gp0_params_table),
+		.no_init_reset = true,
+		.clear_reset_for_lock = true,
+	},
 	.rate_table = gp0_pll_rate_table,
 	.rate_count = ARRAY_SIZE(gp0_pll_rate_table),
 	.lock = &clk_lock,
-- 
1.9.1

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