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| Started by | Chen-Yu Tsai <wens@csie.org> |
|---|---|
| First post | 2017-03-20 15:40 +0100 |
| Last post | 2017-03-20 15:40 +0100 |
| Articles | 1 — 1 participant |
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Re: [linux-sunxi] [PATCH v4 1/8] dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64 Chen-Yu Tsai <wens@csie.org> - 2017-03-20 15:40 +0100
| From | Chen-Yu Tsai <wens@csie.org> |
|---|---|
| Date | 2017-03-20 15:40 +0100 |
| Subject | Re: [linux-sunxi] [PATCH v4 1/8] dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64 |
| Message-ID | <tn6Dw-63o-21@gated-at.bofh.it> |
On Mon, Mar 20, 2017 at 12:19 AM, Icenowy Zheng <icenowy@aosc.xyz> wrote: > Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two > controllers: one is MUSB and the other is a EHCI/OHCI pair. > > When it's routed to EHCI/OHCI pair, it will needs a "pmu0" regs to > tweak, like other EHCI/OHCI pairs in Allwinner SoCs. > > Add this to the binding of USB PHYs on Allwinner H3/V3s/A64. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Chen-Yu Tsai <wens@csie.org> Please keep acks and review tags from others if you haven't changed the patch.
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