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[PATCH 0/5] clk: meson: Fix GXBB and GXL/GXM GP0 PLL

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  [PATCH 0/5] clk: meson: Fix GXBB and GXL/GXM GP0 PLL Neil Armstrong <narmstrong@baylibre.com> - 2017-03-13 14:30 +0100
    [PATCH 4/5] clk: meson-gxbb: Expose GP0 dt-bindings clock id Neil Armstrong <narmstrong@baylibre.com> - 2017-03-13 14:30 +0100
    [PATCH 1/5] clk: meson: Add support for parameters for specific PLLs Neil Armstrong <narmstrong@baylibre.com> - 2017-03-13 14:30 +0100
    [PATCH 5/5] dt-bindings: clock: gxbb-clkc: Add GXL compatible variant Neil Armstrong <narmstrong@baylibre.com> - 2017-03-13 14:30 +0100

#1599358 — [PATCH 0/5] clk: meson: Fix GXBB and GXL/GXM GP0 PLL

This patchset fixes support for the Amlogic GXBB then GXL/GXM embedded GP0 PLL.

The current support is done via a very generic interface where only the
N/M/OD parameters are changed in the control registers.

But unlike the Fixed PLL, this PLL is not initialized by the bootloader or
firmware, and needs some parameters to initialize and lock correctly.

This patchset also adds the GXL variant compatible string which is already
supported by the GXL and GXM DT nodes.

Neil Armstrong (5):
  clk: meson: Add support for parameters for specific PLLs
  clk: meson-gxbb: Add GP0 PLL init parameters
  clk: meson-gxbb: Add GXL/GXM GP0 Variant
  clk: meson-gxbb: Expose GP0 dt-bindings clock id
  dt-bindings: clock: gxbb-clkc: Add GXL compatible variant

 .../bindings/clock/amlogic,gxbb-clkc.txt           |  3 +-
 drivers/clk/meson/clk-pll.c                        | 52 +++++++++++-
 drivers/clk/meson/clkc.h                           | 23 +++++
 drivers/clk/meson/gxbb.c                           | 97 +++++++++++++++++++++-
 drivers/clk/meson/gxbb.h                           |  4 +-
 include/dt-bindings/clock/gxbb-clkc.h              |  1 +
 6 files changed, 173 insertions(+), 7 deletions(-)

-- 
1.9.1

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#1599359 — [PATCH 4/5] clk: meson-gxbb: Expose GP0 dt-bindings clock id

This patch exposes the GP0 PLL clock id in the dt bindings.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 drivers/clk/meson/gxbb.h              | 2 +-
 include/dt-bindings/clock/gxbb-clkc.h | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index 7f99bf6..89f1a2c 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -179,7 +179,7 @@
 /* CLKID_FCLK_DIV4 */
 #define CLKID_FCLK_DIV5		  7
 #define CLKID_FCLK_DIV7		  8
-#define CLKID_GP0_PLL		  9
+/* CLKID_GP0_PLL */
 #define CLKID_MPEG_SEL		  10
 #define CLKID_MPEG_DIV		  11
 /* CLKID_CLK81 */
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index 692846c..febef8b 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -10,6 +10,7 @@
 #define CLKID_FCLK_DIV2		4
 #define CLKID_FCLK_DIV3		5
 #define CLKID_FCLK_DIV4		6
+#define CLKID_GP0_PLL		9
 #define CLKID_CLK81		12
 #define CLKID_MPLL2		15
 #define CLKID_SPI		34
-- 
1.9.1

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#1599362 — [PATCH 1/5] clk: meson: Add support for parameters for specific PLLs

In recent Amlogic GXBB, GXL and GXM SoCs, the GP0 PLL needs some specific
parameters in order to initialize and lock correctly.

This patch adds an optional PARAM table used to initialize the PLL to a
default value with it's parameters in order to achieve to desired frequency.

The GP0 PLL in GXBB, GXL/GXM also needs some tweaks in the initialization
steps, and these are exposed along the PARAM table.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 drivers/clk/meson/clk-pll.c | 52 +++++++++++++++++++++++++++++++++++++++++++--
 drivers/clk/meson/clkc.h    | 23 ++++++++++++++++++++
 2 files changed, 73 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index 4adc1e8..aff223b 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -116,6 +116,29 @@ static const struct pll_rate_table *meson_clk_get_pll_settings(struct meson_clk_
 	return NULL;
 }
 
+/* Specific wait loop for GXL/GXM GP0 PLL */
+static int meson_clk_pll_wait_lock_reset(struct meson_clk_pll *pll,
+					 struct parm *p_n)
+{
+	int delay = 100;
+	u32 reg;
+
+	while (delay > 0) {
+		reg = readl(pll->base + p_n->reg_off);
+		writel(reg | MESON_PLL_RESET, pll->base + p_n->reg_off);
+		udelay(10);
+		writel(reg & ~MESON_PLL_RESET, pll->base + p_n->reg_off);
+
+		mdelay(1);
+
+		reg = readl(pll->base + p_n->reg_off);
+		if (reg & MESON_PLL_LOCK)
+			return 0;
+		delay--;
+	}
+	return -ETIMEDOUT;
+}
+
 static int meson_clk_pll_wait_lock(struct meson_clk_pll *pll,
 				   struct parm *p_n)
 {
@@ -132,6 +155,15 @@ static int meson_clk_pll_wait_lock(struct meson_clk_pll *pll,
 	return -ETIMEDOUT;
 }
 
+static void meson_clk_pll_init_params(struct meson_clk_pll *pll)
+{
+	int i;
+
+	for (i = 0 ; i < pll->params.params_count ; ++i)
+		writel(pll->params.params_table[i].value,
+		       pll->base + pll->params.params_table[i].reg_off);
+}
+
 static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 				  unsigned long parent_rate)
 {
@@ -151,10 +183,16 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 	if (!rate_set)
 		return -EINVAL;
 
+	/* Initialize the PLL in a clean state if specified */
+	if (pll->params.params_count)
+		meson_clk_pll_init_params(pll);
+
 	/* PLL reset */
 	p = &pll->n;
 	reg = readl(pll->base + p->reg_off);
-	writel(reg | MESON_PLL_RESET, pll->base + p->reg_off);
+	/* If no_init_reset is provided, avoid resetting at this point */
+	if (!pll->params.no_init_reset)
+		writel(reg | MESON_PLL_RESET, pll->base + p->reg_off);
 
 	reg = PARM_SET(p->width, p->shift, reg, rate_set->n);
 	writel(reg, pll->base + p->reg_off);
@@ -184,7 +222,17 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 	}
 
 	p = &pll->n;
-	ret = meson_clk_pll_wait_lock(pll, p);
+	/* If unreset_for_lock is provided, remove the reset bit here */
+	if (pll->params.unreset_for_lock) {
+		reg = readl(pll->base + p->reg_off);
+		writel(reg & ~MESON_PLL_RESET, pll->base + p->reg_off);
+	}
+
+	/* If reset_lock_loop, use a special loop including resetting */
+	if (pll->params.reset_lock_loop)
+		ret = meson_clk_pll_wait_lock_reset(pll, p);
+	else
+		ret = meson_clk_pll_wait_lock(pll, p);
 	if (ret) {
 		pr_warn("%s: pll did not lock, trying to restore old rate %lu\n",
 			__func__, old_rate);
diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h
index 9bb70e7..5f1c12d 100644
--- a/drivers/clk/meson/clkc.h
+++ b/drivers/clk/meson/clkc.h
@@ -62,6 +62,28 @@ struct pll_rate_table {
 		.frac		= (_frac),				\
 	}								\
 
+struct pll_params_table {
+	unsigned int reg_off;
+	unsigned int value;
+};
+
+#define PLL_PARAM(_reg, _val)						\
+	{								\
+		.reg_off	= (_reg),				\
+		.value		= (_val),				\
+	}
+
+struct pll_setup_params {
+	struct pll_params_table *params_table;
+	unsigned int params_count;
+	/* Workaround for GP0, do not reset before configuring */
+	bool no_init_reset;
+	/* Workaround for GP0, unreset right before checking for lock */
+	bool unreset_for_lock;
+	/* Workaround for GXL GP0, reset in the lock checking loop */
+	bool reset_lock_loop;
+};
+
 struct meson_clk_pll {
 	struct clk_hw hw;
 	void __iomem *base;
@@ -70,6 +92,7 @@ struct meson_clk_pll {
 	struct parm frac;
 	struct parm od;
 	struct parm od2;
+	const struct pll_setup_params params;
 	const struct pll_rate_table *rate_table;
 	unsigned int rate_count;
 	spinlock_t *lock;
-- 
1.9.1

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#1599363 — [PATCH 5/5] dt-bindings: clock: gxbb-clkc: Add GXL compatible variant

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
index ce06435..a09d627 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
@@ -5,7 +5,8 @@ controllers within the SoC.
 
 Required Properties:
 
-- compatible: should be "amlogic,gxbb-clkc"
+- compatible: should be "amlogic,gxbb-clkc" for GXBB SoC,
+	      or "amlogic,gxl-clkc" for GXL and GXM SoC.
 - reg: physical base address of the clock controller and length of memory
        mapped region.
 
-- 
1.9.1

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