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[PATCH v5 3/4] fpga dt: bindings for Altera Partial Reconfiguration IP.

Started bymatthew.gerlach@linux.intel.com
First post2017-03-10 20:50 +0100
Last post2017-03-13 21:50 +0100
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  [PATCH v5 3/4] fpga dt: bindings for Altera Partial Reconfiguration IP. matthew.gerlach@linux.intel.com - 2017-03-10 20:50 +0100
    Re: [PATCH v5 3/4] fpga dt: bindings for Altera Partial  Reconfiguration IP. Moritz Fischer <moritz.fischer@ettus.com> - 2017-03-13 21:50 +0100

#1598055 — [PATCH v5 3/4] fpga dt: bindings for Altera Partial Reconfiguration IP.

Frommatthew.gerlach@linux.intel.com
Date2017-03-10 20:50 +0100
Subject[PATCH v5 3/4] fpga dt: bindings for Altera Partial Reconfiguration IP.
Message-ID<tjyI2-6Y-21@gated-at.bofh.it>
From: Matthew Gerlach <matthew.gerlach@linux.intel.com>

Device Tree bindings for Altera Partial Reconfiguration IP.

Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Acked-by: Rob Herring <robh@kernel.org>
---
v5:
    fix comment as suggested by Rob Herring <robh@kernel.org>
    added Acked-by: Rob Herring <robh@kernel.org>
v4: v3 patch set mistakenly sent out labeled as v4
v3: s/altr,pr-ip/altr,a10-pr-ip/
v2: s/Reconfiguraion/Reconfiguration/
---
 Documentation/devicetree/bindings/fpga/altera-pr-ip.txt | 12 ++++++++++++
 1 file changed, 12 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/altera-pr-ip.txt

diff --git a/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt b/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
new file mode 100644
index 0000000..52a294c
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
@@ -0,0 +1,12 @@
+Altera Arria10 Partial Reconfiguration IP
+
+Required properties:
+- compatible : should contain "altr,a10-pr-ip"
+- reg        : base address and size for memory mapped io.
+
+Example:
+
+	fpga_mgr: fpga-mgr@ff20c000 {
+		compatible = "altr,a10-pr-ip";
+		reg = <0xff20c000 0x10>;
+	};
-- 
2.7.4

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#1599798 — Re: [PATCH v5 3/4] fpga dt: bindings for Altera Partial Reconfiguration IP.

FromMoritz Fischer <moritz.fischer@ettus.com>
Date2017-03-13 21:50 +0100
SubjectRe: [PATCH v5 3/4] fpga dt: bindings for Altera Partial Reconfiguration IP.
Message-ID<tkF4L-5ZL-41@gated-at.bofh.it>
In reply to#1598055
On Fri, Mar 10, 2017 at 11:40 AM,  <matthew.gerlach@linux.intel.com> wrote:
> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>
> Device Tree bindings for Altera Partial Reconfiguration IP.
>
> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Moritz Fischer <mdf@kernel.org>
> ---
> v5:
>     fix comment as suggested by Rob Herring <robh@kernel.org>
>     added Acked-by: Rob Herring <robh@kernel.org>
> v4: v3 patch set mistakenly sent out labeled as v4
> v3: s/altr,pr-ip/altr,a10-pr-ip/
> v2: s/Reconfiguraion/Reconfiguration/
> ---
>  Documentation/devicetree/bindings/fpga/altera-pr-ip.txt | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
>
> diff --git a/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt b/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
> new file mode 100644
> index 0000000..52a294c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt
> @@ -0,0 +1,12 @@
> +Altera Arria10 Partial Reconfiguration IP
> +
> +Required properties:
> +- compatible : should contain "altr,a10-pr-ip"
> +- reg        : base address and size for memory mapped io.
> +
> +Example:
> +
> +       fpga_mgr: fpga-mgr@ff20c000 {
> +               compatible = "altr,a10-pr-ip";
> +               reg = <0xff20c000 0x10>;
> +       };
> --
> 2.7.4
>

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