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Groups > linux.kernel > #1592405 > unrolled thread
| Started by | Yong Mao <yong.mao@mediatek.com> |
|---|---|
| First post | 2017-03-04 08:20 +0100 |
| Last post | 2017-03-06 08:20 +0100 |
| Articles | 3 — 2 participants |
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[PATCH v2] mmc: mediatek: Fixed bug where clock frequency could be set wrong Yong Mao <yong.mao@mediatek.com> - 2017-03-04 08:20 +0100
[PATCH] mmc: mediatek: Fixed bug where clock frequency could be set wrong Yong Mao <yong.mao@mediatek.com> - 2017-03-04 08:20 +0100
Re: [PATCH] mmc: mediatek: Fixed bug where clock frequency could be set wrong Daniel Kurtz <djkurtz@chromium.org> - 2017-03-06 08:20 +0100
| From | Yong Mao <yong.mao@mediatek.com> |
|---|---|
| Date | 2017-03-04 08:20 +0100 |
| Subject | [PATCH v2] mmc: mediatek: Fixed bug where clock frequency could be set wrong |
| Message-ID | <thc8W-5wq-1@gated-at.bofh.it> |
yong mao (1): mmc: mediatek: Fixed bug where clock frequency could be set wrong drivers/mmc/host/mtk-sd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 1.8.1.1.dirty
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| From | Yong Mao <yong.mao@mediatek.com> |
|---|---|
| Date | 2017-03-04 08:20 +0100 |
| Subject | [PATCH] mmc: mediatek: Fixed bug where clock frequency could be set wrong |
| Message-ID | <thc8W-5wq-5@gated-at.bofh.it> |
| In reply to | #1592405 |
From: yong mao <yong.mao@mediatek.com> This patch can fix two issues: Issue 1: In previous code, div may be overflow when setting clock frequency as f_min. We can use DIV_ROUND_UP to fix this boundary related issue. Issue 2: In previous code, we can not set the correct clock frequency when div equals 0xff. Signed-off-by: Yong Mao <yong.mao@mediatek.com> Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> --- drivers/mmc/host/mtk-sd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index 07f3236..3ad5228 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -591,7 +591,7 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) } } sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, - (mode << 8) | (div % 0xff)); + (mode << 8) | div); sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) cpu_relax(); @@ -1692,7 +1692,7 @@ static int msdc_drv_probe(struct platform_device *pdev) host->src_clk_freq = clk_get_rate(host->src_clk); /* Set host parameters to mmc */ mmc->ops = &mt_msdc_ops; - mmc->f_min = host->src_clk_freq / (4 * 255); + mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23; /* MMC core transfer sizes tunable parameters */ -- 1.7.9.5
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| From | Daniel Kurtz <djkurtz@chromium.org> |
|---|---|
| Date | 2017-03-06 08:20 +0100 |
| Subject | Re: [PATCH] mmc: mediatek: Fixed bug where clock frequency could be set wrong |
| Message-ID | <thV62-4pW-17@gated-at.bofh.it> |
| In reply to | #1592406 |
Hi Yong, On Sat, Mar 4, 2017 at 3:10 PM, Yong Mao <yong.mao@mediatek.com> wrote: > From: yong mao <yong.mao@mediatek.com> > > This patch can fix two issues: > > Issue 1: > In previous code, div may be overflow when setting clock frequency > as f_min. We can use DIV_ROUND_UP to fix this boundary related > issue. > > Issue 2: > In previous code, we can not set the correct clock frequency when > div equals 0xff. > > Signed-off-by: Yong Mao <yong.mao@mediatek.com> > Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> > --- > drivers/mmc/host/mtk-sd.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c > index 07f3236..3ad5228 100644 > --- a/drivers/mmc/host/mtk-sd.c > +++ b/drivers/mmc/host/mtk-sd.c > @@ -591,7 +591,7 @@ static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) > } > } > sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, > - (mode << 8) | (div % 0xff)); > + (mode << 8) | div); > sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); > while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) > cpu_relax(); > @@ -1692,7 +1692,7 @@ static int msdc_drv_probe(struct platform_device *pdev) > host->src_clk_freq = clk_get_rate(host->src_clk); > /* Set host parameters to mmc */ > mmc->ops = &mt_msdc_ops; > - mmc->f_min = host->src_clk_freq / (4 * 255); > + mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); > > mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23; > /* MMC core transfer sizes tunable parameters */ > -- > 1.7.9.5 >
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