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[PATCH] reset: sunxi: fix for 64-bit compilation

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  [PATCH] reset: sunxi: fix for 64-bit compilation Andre Przywara <andre.przywara@arm.com> - 2017-03-06 02:40 +0100
    Re: [PATCH] reset: sunxi: fix for 64-bit compilation Chen-Yu Tsai <wens@csie.org> - 2017-03-08 05:50 +0100
      Re: [PATCH] reset: sunxi: fix for 64-bit compilation Andre Przywara <andre.przywara@arm.com> - 2017-03-08 10:40 +0100
        Re: [PATCH] reset: sunxi: fix for 64-bit compilation Philipp Zabel <p.zabel@pengutronix.de> - 2017-03-08 12:00 +0100

#1592882 — [PATCH] reset: sunxi: fix for 64-bit compilation

The Allwinner reset controller has 32-bit registers, so translating
the reset cell number into a register and bit offset should not use
any architecture dependent data size. Otherwise this breaks for 64-bit
architectures like arm64.
Fix this by making it clear that it's the hardware register width which
matters here in the calculation.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 drivers/reset/reset-sunxi.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/drivers/reset/reset-sunxi.c b/drivers/reset/reset-sunxi.c
index b44f6b5..cd585cd 100644
--- a/drivers/reset/reset-sunxi.c
+++ b/drivers/reset/reset-sunxi.c
@@ -34,15 +34,16 @@ static int sunxi_reset_assert(struct reset_controller_dev *rcdev,
 	struct sunxi_reset_data *data = container_of(rcdev,
 						     struct sunxi_reset_data,
 						     rcdev);
-	int bank = id / BITS_PER_LONG;
-	int offset = id % BITS_PER_LONG;
+	int reg_width = sizeof(u32);
+	int bank = id / (reg_width * BITS_PER_BYTE);
+	int offset = id % (reg_width * BITS_PER_BYTE);
 	unsigned long flags;
 	u32 reg;
 
 	spin_lock_irqsave(&data->lock, flags);
 
-	reg = readl(data->membase + (bank * 4));
-	writel(reg & ~BIT(offset), data->membase + (bank * 4));
+	reg = readl(data->membase + (bank * reg_width));
+	writel(reg & ~BIT(offset), data->membase + (bank * reg_width));
 
 	spin_unlock_irqrestore(&data->lock, flags);
 
@@ -55,15 +56,16 @@ static int sunxi_reset_deassert(struct reset_controller_dev *rcdev,
 	struct sunxi_reset_data *data = container_of(rcdev,
 						     struct sunxi_reset_data,
 						     rcdev);
-	int bank = id / BITS_PER_LONG;
-	int offset = id % BITS_PER_LONG;
+	int reg_width = sizeof(u32);
+	int bank = id / (reg_width * BITS_PER_BYTE);
+	int offset = id % (reg_width * BITS_PER_BYTE);
 	unsigned long flags;
 	u32 reg;
 
 	spin_lock_irqsave(&data->lock, flags);
 
-	reg = readl(data->membase + (bank * 4));
-	writel(reg | BIT(offset), data->membase + (bank * 4));
+	reg = readl(data->membase + (bank * reg_width));
+	writel(reg | BIT(offset), data->membase + (bank * reg_width));
 
 	spin_unlock_irqrestore(&data->lock, flags);
 
-- 
2.8.2

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#1594848

On Mon, Mar 6, 2017 at 9:35 AM, Andre Przywara <andre.przywara@arm.com> wrote:
> The Allwinner reset controller has 32-bit registers, so translating
> the reset cell number into a register and bit offset should not use
> any architecture dependent data size. Otherwise this breaks for 64-bit
> architectures like arm64.
> Fix this by making it clear that it's the hardware register width which
> matters here in the calculation.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Acked-by: Chen-Yu Tsai <wens@csie.org>

Though I don't expect this driver to be used with arm64 chips.

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#1594985

Hi,

On 08/03/17 04:28, Chen-Yu Tsai wrote:
> On Mon, Mar 6, 2017 at 9:35 AM, Andre Przywara <andre.przywara@arm.com> wrote:
>> The Allwinner reset controller has 32-bit registers, so translating
>> the reset cell number into a register and bit offset should not use
>> any architecture dependent data size. Otherwise this breaks for 64-bit
>> architectures like arm64.
>> Fix this by making it clear that it's the hardware register width which
>> matters here in the calculation.
>>
>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> 
> Acked-by: Chen-Yu Tsai <wens@csie.org>

Thanks a lot!

> Though I don't expect this driver to be used with arm64 chips.

Well, weren't we toying with the idea of using this for the A64 PRCM
support?

Also the driver is actually pretty generic, and I have (renaming)
patches lying around to make this obvious. This is partly driven by a
side project for some (arm64) SoC support, which can happily use that
driver to tackle its device reset support.

So as this is an obvious bug, I'd rather see this fixed now.

Cheers,
Andre.

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#1595042

On Wed, 2017-03-08 at 09:26 +0000, Andre Przywara wrote:
> Hi,
> 
> On 08/03/17 04:28, Chen-Yu Tsai wrote:
> > On Mon, Mar 6, 2017 at 9:35 AM, Andre Przywara <andre.przywara@arm.com> wrote:
> >> The Allwinner reset controller has 32-bit registers, so translating
> >> the reset cell number into a register and bit offset should not use
> >> any architecture dependent data size. Otherwise this breaks for 64-bit
> >> architectures like arm64.
> >> Fix this by making it clear that it's the hardware register width which
> >> matters here in the calculation.
> >>
> >> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> > 
> > Acked-by: Chen-Yu Tsai <wens@csie.org>
> 
> Thanks a lot!

Applied, thanks.

> > Though I don't expect this driver to be used with arm64 chips.
> 
> Well, weren't we toying with the idea of using this for the A64 PRCM
> support?
> 
> Also the driver is actually pretty generic, and I have (renaming)
> patches lying around to make this obvious.

That is interesting, I have an untested patch that unifies sunxi,
socfpga, and stm32 floating around. I suppose this could be extended to
also cover ath79 and zx2967. I'll dust it off and send it out.

regards
Philipp

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