Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]


Groups > linux.kernel > #1589553 > unrolled thread

[PATCH v2 1/3] coresight: bindings for debug module

Started byLeo Yan <leo.yan@linaro.org>
First post2017-02-28 16:20 +0100
Last post2017-03-03 09:20 +0100
Articles 4 — 3 participants

Back to article view | Back to linux.kernel

This discussion starts older than the indexed window; earlier articles aren't shown. The article labeled Started by below is the oldest one visible, not the original post.


Contents

  [PATCH v2 1/3] coresight: bindings for debug module Leo Yan <leo.yan@linaro.org> - 2017-02-28 16:20 +0100
    Re: [PATCH v2 1/3] coresight: bindings for debug module Mathieu Poirier <mathieu.poirier@linaro.org> - 2017-03-01 17:00 +0100
      Re: [PATCH v2 1/3] coresight: bindings for debug module Leo Yan <leo.yan@linaro.org> - 2017-03-02 02:10 +0100
    Re: [PATCH v2 1/3] coresight: bindings for debug module Rob Herring <robh@kernel.org> - 2017-03-03 09:20 +0100

#1589553 — [PATCH v2 1/3] coresight: bindings for debug module

FromLeo Yan <leo.yan@linaro.org>
Date2017-02-28 16:20 +0100
Subject[PATCH v2 1/3] coresight: bindings for debug module
Message-ID<tfRJg-6ds-29@gated-at.bofh.it>
According to ARMv8 architecture reference manual (ARM DDI 0487A.k)
Chapter 'Part H: External debug', the CPU can integrate debug module
and it can support self-hosted debug and external debug. Especially
for supporting self-hosted debug, this means the program can access
the debug module from mmio region; and usually the mmio region is
integrated with coresight.

So add document for binding debug component, includes binding to APB
clock; and also need specify the CPU node which the debug module is
dedicated to specific CPU.

Suggested-by: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
---
 .../devicetree/bindings/arm/coresight-debug.txt    | 40 ++++++++++++++++++++++
 1 file changed, 40 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/coresight-debug.txt

diff --git a/Documentation/devicetree/bindings/arm/coresight-debug.txt b/Documentation/devicetree/bindings/arm/coresight-debug.txt
new file mode 100644
index 0000000..89820d5
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/coresight-debug.txt
@@ -0,0 +1,40 @@
+* CoreSight Debug Component:
+
+CoreSight debug component are compliant with the ARMv8 architecture reference
+manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The external debug
+module is mainly used for two modes: self-hosted debug and external debug, and
+it can be accessed from mmio region from Coresight and eventually the debug
+module connects with CPU for debugging. And the debug module provides
+sample-based profiling extension, which can be used to sample CPU program
+counter, secure state and exception level, etc; usually every CPU has one
+dedicated debug module to be connected.
+
+Required properties:
+
+- compatible : should be
+	     * "arm,coresight-debug", "arm,primecell"; supplemented with
+	       "arm,primecell" as driver is using the AMBA bus interface.
+
+- reg : physical base address and length of the register set.
+
+- clocks : the clock associated to this component.
+
+- clock-names : the name of the clock referenced by the code. Since we are
+                using the AMBA framework, the name of the clock providing
+		the interconnect should be "apb_pclk" and the clock is
+		mandatory. The interface between the debug logic and the
+		processor core is clocked by the internal CPU clock, so it
+		is enabled with CPU clock by default.
+
+- cpu : the cpu phandle the debug module is affined to. When omitted
+	the source is considered to belong to CPU0.
+
+Example:
+
+	debug@f6590000 {
+		compatible = "arm,coresight-debug","arm,primecell";
+		reg = <0 0xf6590000 0 0x1000>;
+		clocks = <&sys_ctrl HI6220_DAPB_CLK>;
+		clock-names = "apb_pclk";
+		cpu = <&cpu0>;
+	};
-- 
2.7.4

[toc] | [next] | [standalone]


#1590458

FromMathieu Poirier <mathieu.poirier@linaro.org>
Date2017-03-01 17:00 +0100
Message-ID<tgePy-5b2-69@gated-at.bofh.it>
In reply to#1589553
On Tue, Feb 28, 2017 at 11:06:58PM +0800, Leo Yan wrote:
> According to ARMv8 architecture reference manual (ARM DDI 0487A.k)
> Chapter 'Part H: External debug', the CPU can integrate debug module
> and it can support self-hosted debug and external debug. Especially
> for supporting self-hosted debug, this means the program can access
> the debug module from mmio region; and usually the mmio region is
> integrated with coresight.
> 
> So add document for binding debug component, includes binding to APB
> clock; and also need specify the CPU node which the debug module is
> dedicated to specific CPU.
> 
> Suggested-by: Mike Leach <mike.leach@linaro.org>
> Signed-off-by: Leo Yan <leo.yan@linaro.org>
> ---
>  .../devicetree/bindings/arm/coresight-debug.txt    | 40 ++++++++++++++++++++++
>  1 file changed, 40 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/coresight-debug.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/coresight-debug.txt b/Documentation/devicetree/bindings/arm/coresight-debug.txt
> new file mode 100644
> index 0000000..89820d5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/coresight-debug.txt
> @@ -0,0 +1,40 @@
> +* CoreSight Debug Component:
> +
> +CoreSight debug component are compliant with the ARMv8 architecture reference
> +manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The external debug
> +module is mainly used for two modes: self-hosted debug and external debug, and
> +it can be accessed from mmio region from Coresight and eventually the debug
> +module connects with CPU for debugging. And the debug module provides
> +sample-based profiling extension, which can be used to sample CPU program
> +counter, secure state and exception level, etc; usually every CPU has one
> +dedicated debug module to be connected.
> +
> +Required properties:
> +
> +- compatible : should be
> +	     * "arm,coresight-debug", "arm,primecell"; supplemented with
> +	       "arm,primecell" as driver is using the AMBA bus interface.

             * "arm,coresight-debug"; supplemented with "arm,primecell" since
               this driver is using the AMBA bus interface.

> +
> +- reg : physical base address and length of the register set.
> +
> +- clocks : the clock associated to this component.
> +
> +- clock-names : the name of the clock referenced by the code. Since we are
> +                using the AMBA framework, the name of the clock providing
> +		the interconnect should be "apb_pclk" and the clock is
> +		mandatory. The interface between the debug logic and the
> +		processor core is clocked by the internal CPU clock, so it
> +		is enabled with CPU clock by default.
> +
> +- cpu : the cpu phandle the debug module is affined to. When omitted
> +	the source is considered to belong to CPU0.

s/source/module

With those change:

Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>

> +
> +Example:
> +
> +	debug@f6590000 {
> +		compatible = "arm,coresight-debug","arm,primecell";
> +		reg = <0 0xf6590000 0 0x1000>;
> +		clocks = <&sys_ctrl HI6220_DAPB_CLK>;
> +		clock-names = "apb_pclk";
> +		cpu = <&cpu0>;
> +	};
> -- 
> 2.7.4
> 

[toc] | [prev] | [next] | [standalone]


#1590753

FromLeo Yan <leo.yan@linaro.org>
Date2017-03-02 02:10 +0100
Message-ID<tgnpL-30D-1@gated-at.bofh.it>
In reply to#1590458
On Wed, Mar 01, 2017 at 08:45:50AM -0700, Mathieu Poirier wrote:
> On Tue, Feb 28, 2017 at 11:06:58PM +0800, Leo Yan wrote:
> > According to ARMv8 architecture reference manual (ARM DDI 0487A.k)
> > Chapter 'Part H: External debug', the CPU can integrate debug module
> > and it can support self-hosted debug and external debug. Especially
> > for supporting self-hosted debug, this means the program can access
> > the debug module from mmio region; and usually the mmio region is
> > integrated with coresight.
> > 
> > So add document for binding debug component, includes binding to APB
> > clock; and also need specify the CPU node which the debug module is
> > dedicated to specific CPU.
> > 
> > Suggested-by: Mike Leach <mike.leach@linaro.org>
> > Signed-off-by: Leo Yan <leo.yan@linaro.org>
> > ---
> >  .../devicetree/bindings/arm/coresight-debug.txt    | 40 ++++++++++++++++++++++
> >  1 file changed, 40 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/arm/coresight-debug.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/arm/coresight-debug.txt b/Documentation/devicetree/bindings/arm/coresight-debug.txt
> > new file mode 100644
> > index 0000000..89820d5
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/coresight-debug.txt
> > @@ -0,0 +1,40 @@
> > +* CoreSight Debug Component:
> > +
> > +CoreSight debug component are compliant with the ARMv8 architecture reference
> > +manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The external debug
> > +module is mainly used for two modes: self-hosted debug and external debug, and
> > +it can be accessed from mmio region from Coresight and eventually the debug
> > +module connects with CPU for debugging. And the debug module provides
> > +sample-based profiling extension, which can be used to sample CPU program
> > +counter, secure state and exception level, etc; usually every CPU has one
> > +dedicated debug module to be connected.
> > +
> > +Required properties:
> > +
> > +- compatible : should be
> > +	     * "arm,coresight-debug", "arm,primecell"; supplemented with
> > +	       "arm,primecell" as driver is using the AMBA bus interface.
> 
>              * "arm,coresight-debug"; supplemented with "arm,primecell" since
>                this driver is using the AMBA bus interface.
> 
> > +
> > +- reg : physical base address and length of the register set.
> > +
> > +- clocks : the clock associated to this component.
> > +
> > +- clock-names : the name of the clock referenced by the code. Since we are
> > +                using the AMBA framework, the name of the clock providing
> > +		the interconnect should be "apb_pclk" and the clock is
> > +		mandatory. The interface between the debug logic and the
> > +		processor core is clocked by the internal CPU clock, so it
> > +		is enabled with CPU clock by default.
> > +
> > +- cpu : the cpu phandle the debug module is affined to. When omitted
> > +	the source is considered to belong to CPU0.
> 
> s/source/module
> 
> With those change:
> 
> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>

Thanks for reviewing :)

> > +
> > +Example:
> > +
> > +	debug@f6590000 {
> > +		compatible = "arm,coresight-debug","arm,primecell";
> > +		reg = <0 0xf6590000 0 0x1000>;
> > +		clocks = <&sys_ctrl HI6220_DAPB_CLK>;
> > +		clock-names = "apb_pclk";
> > +		cpu = <&cpu0>;
> > +	};
> > -- 
> > 2.7.4
> > 

[toc] | [prev] | [next] | [standalone]


#1591736

FromRob Herring <robh@kernel.org>
Date2017-03-03 09:20 +0100
Message-ID<tgQBr-6J0-11@gated-at.bofh.it>
In reply to#1589553
On Tue, Feb 28, 2017 at 11:06:58PM +0800, Leo Yan wrote:
> According to ARMv8 architecture reference manual (ARM DDI 0487A.k)
> Chapter 'Part H: External debug', the CPU can integrate debug module
> and it can support self-hosted debug and external debug. Especially
> for supporting self-hosted debug, this means the program can access
> the debug module from mmio region; and usually the mmio region is
> integrated with coresight.
> 
> So add document for binding debug component, includes binding to APB
> clock; and also need specify the CPU node which the debug module is
> dedicated to specific CPU.
> 
> Suggested-by: Mike Leach <mike.leach@linaro.org>
> Signed-off-by: Leo Yan <leo.yan@linaro.org>
> ---
>  .../devicetree/bindings/arm/coresight-debug.txt    | 40 ++++++++++++++++++++++
>  1 file changed, 40 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/coresight-debug.txt

Acked-by: Rob Herring <robh@kernel.org>

[toc] | [prev] | [standalone]


Back to top | Article view | linux.kernel


csiph-web