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Groups > linux.kernel > #1590005 > unrolled thread
| Started by | Len Brown <lenb@kernel.org> |
|---|---|
| First post | 2017-03-01 06:50 +0100 |
| Last post | 2017-03-02 02:20 +0100 |
| Articles | 20 on this page of 27 — 2 participants |
Back to article view | Back to linux.kernel
[GIT PULL] turbostat 17.02.24 Len Brown <lenb@kernel.org> - 2017-03-01 06:50 +0100
[PATCH 11/44] tools/power turbostat: Baytrail c-state support Len Brown <lenb@kernel.org> - 2017-03-01 06:50 +0100
[PATCH 06/44] tools/power turbostat: update MSR_PKG_CST_CONFIG_CONTROL decoding Len Brown <lenb@kernel.org> - 2017-03-01 06:50 +0100
[PATCH 24/44] x86: intel-family.h: Add GEMINI_LAKE SOC Len Brown <lenb@kernel.org> - 2017-03-01 06:50 +0100
Re: [PATCH 24/44] x86: intel-family.h: Add GEMINI_LAKE SOC Andy Shevchenko <andy.shevchenko@gmail.com> - 2017-03-02 01:00 +0100
[PATCH 18/44] x86 msr_index.h: Define MSR_MISC_FEATURE_CONTROL Len Brown <lenb@kernel.org> - 2017-03-01 06:50 +0100
[PATCH 02/44] tools/power turbostat: Add --show and --hide parameters Len Brown <lenb@kernel.org> - 2017-03-01 06:50 +0100
[PATCH 07/44] x86: msr-index.h: Define MSR_PKG_CST_CONFIG_CONTROL Len Brown <lenb@kernel.org> - 2017-03-01 06:50 +0100
[PATCH 34/44] tools/power turbostat: Add --list option to show available header names Len Brown <lenb@kernel.org> - 2017-03-01 06:50 +0100
[PATCH 30/44] tools/power turbostat: extend --add option to accept /sys path Len Brown <lenb@kernel.org> - 2017-03-01 06:50 +0100
[PATCH 41/44] tools/power turbostat: dump p-state software config Len Brown <lenb@kernel.org> - 2017-03-01 06:50 +0100
[PATCH 05/44] tools/power turbostat: Baytrail: remove debug line in quiet mode Len Brown <lenb@kernel.org> - 2017-03-01 07:00 +0100
[PATCH 03/44] tools/power turbostat: BYT does not have MSR_MISC_PWR_MGMT Len Brown <lenb@kernel.org> - 2017-03-01 07:00 +0100
[PATCH 12/44] tools/power turbostat: add precision to --debug frequency output Len Brown <lenb@kernel.org> - 2017-03-01 07:00 +0100
[PATCH 40/44] tools/power turbostat: show package number, even without --debug Len Brown <lenb@kernel.org> - 2017-03-01 07:00 +0100
[PATCH 08/44] intel_idle: use new name for MSR_PKG_CST_CONFIG_CONTROL Len Brown <lenb@kernel.org> - 2017-03-01 07:00 +0100
[PATCH 14/44] x86 msr-index.h: Define Atom specific core ratio MSR locations Len Brown <lenb@kernel.org> - 2017-03-01 07:00 +0100
[PATCH 10/44] x86: msr-index.h: Remove unused MSR_NHM_SNB_PKG_CST_CFG_CTL Len Brown <lenb@kernel.org> - 2017-03-01 07:40 +0100
[PATCH 01/44] tools/power turbostat: fix bugs in --add option Len Brown <lenb@kernel.org> - 2017-03-01 07:50 +0100
[PATCH 16/44] tools/power turbostat: dump Atom P-states correctly Len Brown <lenb@kernel.org> - 2017-03-01 08:20 +0100
[PATCH 13/44] tools/power turbostat: further decode MSR_IA32_MISC_ENABLE Len Brown <lenb@kernel.org> - 2017-03-01 08:20 +0100
[PATCH 33/44] tools/power turbostat: fix zero IRQ count shown in one-shot command mode Len Brown <lenb@kernel.org> - 2017-03-01 08:20 +0100
[PATCH 04/44] tools/power turbostat: decode Baytrail CC6 and MC6 demotion configuration Len Brown <lenb@kernel.org> - 2017-03-01 08:30 +0100
[PATCH 09/44] tools/power turbostat: use new name for MSR_PKG_CST_CONFIG_CONTROL Len Brown <lenb@kernel.org> - 2017-03-01 09:20 +0100
[PATCH 35/44] tools/power turbostat: use wide columns to display large numbers Len Brown <lenb@kernel.org> - 2017-03-01 10:40 +0100
[PATCH 28/44] tools/power turbostat: fix decoding for GLM, DNV, SKX turbo-ratio limits Len Brown <lenb@kernel.org> - 2017-03-01 16:40 +0100
[PATCH 19/44] tools/power turbostat: decode MSR_MISC_FEATURE_CONTROL Len Brown <lenb@kernel.org> - 2017-03-02 02:20 +0100
Page 1 of 2 [1] 2 Next page →
| From | Len Brown <lenb@kernel.org> |
|---|---|
| Date | 2017-03-01 06:50 +0100 |
| Subject | [GIT PULL] turbostat 17.02.24 |
| Message-ID | <tg59v-6Jh-3@gated-at.bofh.it> |
Hi Rafael,
Please pull these turbostat-related patches.
This patch series updates turbostat in the Linux kernel tree to
to the latest out-of-tree version -- 17.02.24.
There are several significant changes since the version that
shipped in the Linux-4.10 tree.
Default output is now verbose, --debug is no longer required
to get all counters. As a result, some options have
been added to specify exactly what output is wanted.
Added --quiet to skip system configuration output
Added --list, --show and --hide parameters
Added --cpu parameter
Enhanced Baytrail SOC support
Added Gemini Lake SOC support
Added sysfs C-state columns
These changes are detailed on the updated turbostat.8 man page.
thanks!
Len Brown, Intel Open Source Technology Center
The following changes since commit c470abd4fde40ea6a0846a2beab642a578c0b8cd:
Linux 4.10 (2017-02-19 14:34:00 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux.git turbostat
for you to fetch changes up to e3942ed8c66bcff496abee5182422cd542962d9e:
tools/power turbostat: version 17.02.24 (2017-03-01 00:14:26 -0500)
----------------------------------------------------------------
Len Brown (44):
tools/power turbostat: fix bugs in --add option
tools/power turbostat: Add --show and --hide parameters
tools/power turbostat: BYT does not have MSR_MISC_PWR_MGMT
tools/power turbostat: decode Baytrail CC6 and MC6 demotion configuration
tools/power turbostat: Baytrail: remove debug line in quiet mode
tools/power turbostat: update MSR_PKG_CST_CONFIG_CONTROL decoding
x86: msr-index.h: Define MSR_PKG_CST_CONFIG_CONTROL
intel_idle: use new name for MSR_PKG_CST_CONFIG_CONTROL
tools/power turbostat: use new name for MSR_PKG_CST_CONFIG_CONTROL
x86: msr-index.h: Remove unused MSR_NHM_SNB_PKG_CST_CFG_CTL
tools/power turbostat: Baytrail c-state support
tools/power turbostat: add precision to --debug frequency output
tools/power turbostat: further decode MSR_IA32_MISC_ENABLE
x86 msr-index.h: Define Atom specific core ratio MSR locations
intel_pstate: use MSR_ATOM_RATIOS definitions from msr-index.h
tools/power turbostat: dump Atom P-states correctly
tools/power turbostat: decode CPUID(6).TURBO
x86 msr_index.h: Define MSR_MISC_FEATURE_CONTROL
tools/power turbostat: decode MSR_MISC_FEATURE_CONTROL
tools/power turbostat: show all columns, independent of --debug
tools/power turbostat: print system config, unless --quiet
tools/power turbostat: use tsc_tweak everwhere it is needed
tools/power turbostat: bug fixes to --add, --show/--hide features
x86: intel-family.h: Add GEMINI_LAKE SOC
tools/power turbostat: initial Gemini Lake SOC support
tools/power turbostat: Denverton: use HW CC1 counter, skip C3, C7
tools/power turbostat: skip unused counters on SKX
tools/power turbostat: fix decoding for GLM, DNV, SKX turbo-ratio limits
tools/power turbostat: skip unused counters on BDX
tools/power turbostat: extend --add option to accept /sys path
tools/power turbostat: print sysfs C-state stats
tools/power turbostat: add --cpu parameter
tools/power turbostat: fix zero IRQ count shown in one-shot command mode
tools/power turbostat: Add --list option to show available header names
tools/power turbostat: use wide columns to display large numbers
tools/power turbostat: update --list feature
tools/power turbostat: turbostat.8 update
tools/power turbostat: move --Package and --processor into the --cpu option
tools/power turbostat: support "--hide C1" etc.
tools/power turbostat: show package number, even without --debug
tools/power turbostat: dump p-state software config
tools/power turbostat: show error on exec
tools/power turbostat: bugfix: --add u32 was printed as u64
tools/power turbostat: version 17.02.24
arch/x86/include/asm/intel-family.h | 1 +
arch/x86/include/asm/msr-index.h | 11 +-
drivers/cpufreq/intel_pstate.c | 15 +-
drivers/idle/intel_idle.c | 6 +-
tools/power/x86/turbostat/turbostat.8 | 253 +++--
tools/power/x86/turbostat/turbostat.c | 1880 ++++++++++++++++++++++++---------
6 files changed, 1570 insertions(+), 596 deletions(-)
[toc] | [next] | [standalone]
| From | Len Brown <lenb@kernel.org> |
|---|---|
| Date | 2017-03-01 06:50 +0100 |
| Subject | [PATCH 11/44] tools/power turbostat: Baytrail c-state support |
| Message-ID | <tg5jc-6MD-3@gated-at.bofh.it> |
| In reply to | #1590005 |
From: Len Brown <len.brown@intel.com>
The Baytrail SOC, with its Silvermont core, has some unique properties:
1. a hardware CC1 residency counter
2. a module-c6 residency counter
3. a package-c6 counter at traditional package-c7 counter address.
The SOC does not support c3, pc3, c7 or pc7 counters.
Signed-off-by: Len Brown <len.brown@intel.com>
---
arch/x86/include/asm/msr-index.h | 2 ++
tools/power/x86/turbostat/turbostat.c | 46 ++++++++++++++++++++++++++++-------
2 files changed, 39 insertions(+), 9 deletions(-)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 12ecc6c1e7f8..079db99f6560 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -147,6 +147,7 @@
/* C-state Residency Counters */
#define MSR_PKG_C3_RESIDENCY 0x000003f8
#define MSR_PKG_C6_RESIDENCY 0x000003f9
+#define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa
#define MSR_PKG_C7_RESIDENCY 0x000003fa
#define MSR_CORE_C3_RESIDENCY 0x000003fc
#define MSR_CORE_C6_RESIDENCY 0x000003fd
@@ -203,6 +204,7 @@
#define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
#define MSR_CORE_C1_RES 0x00000660
+#define MSR_MODULE_C6_RES_MS 0x00000664
#define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668
#define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669
diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c
index d56f2b75dc58..19802be6dc02 100644
--- a/tools/power/x86/turbostat/turbostat.c
+++ b/tools/power/x86/turbostat/turbostat.c
@@ -167,6 +167,7 @@ struct core_data {
unsigned long long c3;
unsigned long long c6;
unsigned long long c7;
+ unsigned long long mc6_us; /* duplicate as per-core for now, even though per module */
unsigned int core_temp_c;
unsigned int core_id;
unsigned long long counter[MAX_ADDED_COUNTERS];
@@ -375,6 +376,7 @@ struct msr_counter bic[] = {
{ 0x0, "RAM_J" },
{ 0x0, "Core" },
{ 0x0, "CPU" },
+ { 0x0, "Mod%c6" },
};
#define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter))
@@ -412,6 +414,7 @@ struct msr_counter bic[] = {
#define BIC_RAM_J (1ULL << 31)
#define BIC_Core (1ULL << 32)
#define BIC_CPU (1ULL << 33)
+#define BIC_Mod_c6 (1ULL << 34)
unsigned long long bic_enabled = 0xFFFFFFFFFFFFFFFFULL;
unsigned long long bic_present;
@@ -504,6 +507,8 @@ void print_header(void)
if (DO_BIC(BIC_CPU_c7))
outp += sprintf(outp, "\tCPU%%c7");
+ if (DO_BIC(BIC_Mod_c6))
+ outp += sprintf(outp, "\tMod%%c6");
if (DO_BIC(BIC_CoreTmp))
outp += sprintf(outp, "\tCoreTmp");
@@ -629,6 +634,7 @@ int dump_counters(struct thread_data *t, struct core_data *c,
outp += sprintf(outp, "cADDED [%d] msr0x%x: %08llX\n",
i, mp->msr_num, c->counter[i]);
}
+ outp += sprintf(outp, "mc6_us: %016llX\n", c->mc6_us);
}
if (p) {
@@ -774,6 +780,10 @@ int format_counters(struct thread_data *t, struct core_data *c,
if (DO_BIC(BIC_CPU_c7))
outp += sprintf(outp, "\t%.2f", 100.0 * c->c7/t->tsc);
+ /* Mod%c6 */
+ if (DO_BIC(BIC_Mod_c6))
+ outp += sprintf(outp, "\t%.2f", 100.0 * c->mc6_us / t->tsc);
+
if (DO_BIC(BIC_CoreTmp))
outp += sprintf(outp, "\t%d", c->core_temp_c);
@@ -988,6 +998,7 @@ delta_core(struct core_data *new, struct core_data *old)
old->c6 = new->c6 - old->c6;
old->c7 = new->c7 - old->c7;
old->core_temp_c = new->core_temp_c;
+ old->mc6_us = new->mc6_us - old->mc6_us;
for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
if (mp->format == FORMAT_RAW)
@@ -1109,6 +1120,7 @@ void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data
c->c3 = 0;
c->c6 = 0;
c->c7 = 0;
+ c->mc6_us = 0;
c->core_temp_c = 0;
p->pkg_wtd_core_c0 = 0;
@@ -1173,6 +1185,7 @@ int sum_counters(struct thread_data *t, struct core_data *c,
average.cores.c3 += c->c3;
average.cores.c6 += c->c6;
average.cores.c7 += c->c7;
+ average.cores.mc6_us += c->mc6_us;
average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c);
@@ -1246,6 +1259,7 @@ void compute_average(struct thread_data *t, struct core_data *c,
average.cores.c3 /= topo.num_cores;
average.cores.c6 /= topo.num_cores;
average.cores.c7 /= topo.num_cores;
+ average.cores.mc6_us /= topo.num_cores;
if (do_skl_residency) {
average.packages.pkg_wtd_core_c0 /= topo.num_packages;
@@ -1376,8 +1390,7 @@ int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
return -5;
t->smi_count = msr & 0xFFFFFFFF;
}
-
- if (use_c1_residency_msr) {
+ if (DO_BIC(BIC_CPU_c1) && use_c1_residency_msr) {
if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1))
return -6;
}
@@ -1409,6 +1422,10 @@ int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7))
return -8;
+ if (DO_BIC(BIC_Mod_c6))
+ if (get_msr(cpu, MSR_MODULE_C6_RES_MS, &c->mc6_us))
+ return -8;
+
if (DO_BIC(BIC_CoreTmp)) {
if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
return -9;
@@ -1437,9 +1454,16 @@ int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
if (do_pc3)
if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3))
return -9;
- if (do_pc6)
- if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6))
- return -10;
+ if (do_pc6) {
+ if (do_slm_cstates) {
+ if (get_msr(cpu, MSR_ATOM_PKG_C6_RESIDENCY, &p->pc6))
+ return -10;
+ } else {
+ if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6))
+ return -10;
+ }
+ }
+
if (do_pc2)
if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2))
return -11;
@@ -1533,7 +1557,7 @@ char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2",
int nhm_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
int snb_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
int hsw_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
-int slv_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
+int slv_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7};
int amt_pkg_cstate_limits[16] = {PCLUNL, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
int phi_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
int bxt_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
@@ -3336,8 +3360,6 @@ int has_skl_msrs(unsigned int family, unsigned int model)
return 0;
}
-
-
int is_slm(unsigned int family, unsigned int model)
{
if (!genuine_intel)
@@ -3731,6 +3753,12 @@ void process_cpuid()
do_pc3 = (pkg_cstate_limit >= PCL__3);
do_pc6 = (pkg_cstate_limit >= PCL__6);
do_pc7 = do_snb_cstates && (pkg_cstate_limit >= PCL__7);
+ if (has_slv_msrs(family, model)) {
+ do_pc2 = do_pc3 = do_pc7 = 0;
+ do_pc6 = 1;
+ BIC_PRESENT(BIC_Mod_c6);
+ use_c1_residency_msr = 1;
+ }
do_c8_c9_c10 = has_hsw_msrs(family, model);
do_irtl_hsw = has_hsw_msrs(family, model);
do_skl_residency = has_skl_msrs(family, model);
@@ -4112,7 +4140,7 @@ int get_and_dump_counters(void)
}
void print_version() {
- fprintf(outf, "turbostat version 4.17 1 Jan 2017"
+ fprintf(outf, "turbostat version 4.17 10 Jan 2017"
" - Len Brown <lenb@kernel.org>\n");
}
--
2.11.0.161.g6610af872
[toc] | [prev] | [next] | [standalone]
| From | Len Brown <lenb@kernel.org> |
|---|---|
| Date | 2017-03-01 06:50 +0100 |
| Subject | [PATCH 06/44] tools/power turbostat: update MSR_PKG_CST_CONFIG_CONTROL decoding |
| Message-ID | <tg5jc-6MD-9@gated-at.bofh.it> |
| In reply to | #1590005 |
From: Len Brown <len.brown@intel.com>
AMT value 0 is unlimited, not PC0
Signed-off-by: Len Brown <len.brown@intel.com>
---
tools/power/x86/turbostat/turbostat.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c
index 9b35c9bb0489..aedfaddbad30 100644
--- a/tools/power/x86/turbostat/turbostat.c
+++ b/tools/power/x86/turbostat/turbostat.c
@@ -1534,7 +1534,7 @@ int nhm_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV,
int snb_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
int hsw_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
int slv_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
-int amt_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
+int amt_pkg_cstate_limits[16] = {PCLUNL, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
int phi_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
int bxt_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
int skx_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
--
2.11.0.161.g6610af872
[toc] | [prev] | [next] | [standalone]
| From | Len Brown <lenb@kernel.org> |
|---|---|
| Date | 2017-03-01 06:50 +0100 |
| Subject | [PATCH 24/44] x86: intel-family.h: Add GEMINI_LAKE SOC |
| Message-ID | <tg5jc-6MD-11@gated-at.bofh.it> |
| In reply to | #1590005 |
From: Len Brown <len.brown@intel.com> Cc: x86@kernel.org Signed-off-by: Len Brown <len.brown@intel.com> --- arch/x86/include/asm/intel-family.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h index 8167fdb67ae8..9814db42b790 100644 --- a/arch/x86/include/asm/intel-family.h +++ b/arch/x86/include/asm/intel-family.h @@ -59,6 +59,7 @@ #define INTEL_FAM6_ATOM_MERRIFIELD 0x4A /* Tangier */ #define INTEL_FAM6_ATOM_MOOREFIELD 0x5A /* Anniedale */ #define INTEL_FAM6_ATOM_GOLDMONT 0x5C +#define INTEL_FAM6_ATOM_GEMINI_LAKE 0x7A #define INTEL_FAM6_ATOM_DENVERTON 0x5F /* Goldmont Microserver */ /* Xeon Phi */ -- 2.11.0.161.g6610af872
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| From | Andy Shevchenko <andy.shevchenko@gmail.com> |
|---|---|
| Date | 2017-03-02 01:00 +0100 |
| Subject | Re: [PATCH 24/44] x86: intel-family.h: Add GEMINI_LAKE SOC |
| Message-ID | <tgmk1-22k-5@gated-at.bofh.it> |
| In reply to | #1590009 |
On Wed, Mar 1, 2017 at 7:27 AM, Len Brown <lenb@kernel.org> wrote: > From: Len Brown <len.brown@intel.com> > --- a/arch/x86/include/asm/intel-family.h > +++ b/arch/x86/include/asm/intel-family.h > @@ -59,6 +59,7 @@ > #define INTEL_FAM6_ATOM_MERRIFIELD 0x4A /* Tangier */ > #define INTEL_FAM6_ATOM_MOOREFIELD 0x5A /* Anniedale */ > #define INTEL_FAM6_ATOM_GOLDMONT 0x5C > +#define INTEL_FAM6_ATOM_GEMINI_LAKE 0x7A > #define INTEL_FAM6_ATOM_DENVERTON 0x5F /* Goldmont Microserver */ One nit: can we keep it in order by model ID? -- With Best Regards, Andy Shevchenko
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| From | Len Brown <lenb@kernel.org> |
|---|---|
| Date | 2017-03-01 06:50 +0100 |
| Subject | [PATCH 18/44] x86 msr_index.h: Define MSR_MISC_FEATURE_CONTROL |
| Message-ID | <tg5jd-6MD-15@gated-at.bofh.it> |
| In reply to | #1590005 |
From: Len Brown <len.brown@intel.com> This non-architectural MSR has disable bits for various prefetchers on modern processors. While these bits are generally touched only by the BIOS, say, via BIOS SETUP, it is useful to dump them when examining options that can alter performance. Cc: x86@kernel.org Signed-off-by: Len Brown <len.brown@intel.com> --- arch/x86/include/asm/msr-index.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 83bc672c225c..312fb7e14cdd 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -467,6 +467,7 @@ #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 +#define MSR_MISC_FEATURE_CONTROL 0x000001a4 #define MSR_MISC_PWR_MGMT 0x000001aa #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 -- 2.11.0.161.g6610af872
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| From | Len Brown <lenb@kernel.org> |
|---|---|
| Date | 2017-03-01 06:50 +0100 |
| Subject | [PATCH 02/44] tools/power turbostat: Add --show and --hide parameters |
| Message-ID | <tg5jc-6MD-13@gated-at.bofh.it> |
| In reply to | #1590005 |
From: Len Brown <len.brown@intel.com>
Add the "--show" and "--hide" cmdline parameters.
By default, turbostat shows all columns.
turbostat --hide counter_list
will continue showing all columns, except for those listed.
turbostat --show counter_list
will show _only_ the listed columns
These features work for built-in counters, and have no effect
on columns added with the --add parameter.
Signed-off-by: Len Brown <len.brown@intel.com>
---
tools/power/x86/turbostat/turbostat.8 | 4 +
tools/power/x86/turbostat/turbostat.c | 463 +++++++++++++++++++++++++---------
2 files changed, 347 insertions(+), 120 deletions(-)
diff --git a/tools/power/x86/turbostat/turbostat.8 b/tools/power/x86/turbostat/turbostat.8
index 03cb639b292e..e8fb1e02d121 100644
--- a/tools/power/x86/turbostat/turbostat.8
+++ b/tools/power/x86/turbostat/turbostat.8
@@ -47,6 +47,10 @@ name as necessary to disambiguate it from others is necessary. Note that option
default: delta
.fi
.PP
+\fB--hide column\fP do not show the specified columns. May be invoked multiple times, or with a comma-separated list of column names.
+.PP
+\fB--show column\fP show only the specified columns. May be invoked multiple times, or with a comma-separated list of column names.
+.PP
\fB--Dump\fP displays the raw counter values.
.PP
\fB--debug\fP displays additional system configuration information. Invoking this parameter
diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c
index c7fadf0faa4b..fff280b50af0 100644
--- a/tools/power/x86/turbostat/turbostat.c
+++ b/tools/power/x86/turbostat/turbostat.c
@@ -52,7 +52,6 @@ unsigned int debug;
unsigned int rapl_joules;
unsigned int summary_only;
unsigned int dump_only;
-unsigned int do_nhm_cstates;
unsigned int do_snb_cstates;
unsigned int do_knl_cstates;
unsigned int do_pc2;
@@ -72,24 +71,17 @@ unsigned int genuine_intel;
unsigned int has_invariant_tsc;
unsigned int do_nhm_platform_info;
unsigned int aperf_mperf_multiplier = 1;
-int do_irq = 1;
-int do_smi;
double bclk;
double base_hz;
unsigned int has_base_hz;
double tsc_tweak = 1.0;
-unsigned int show_pkg;
-unsigned int show_core;
-unsigned int show_cpu;
unsigned int show_pkg_only;
unsigned int show_core_only;
char *output_buffer, *outp;
unsigned int do_rapl;
unsigned int do_dts;
unsigned int do_ptm;
-unsigned int do_gfx_rc6_ms;
unsigned long long gfx_cur_rc6_ms;
-unsigned int do_gfx_mhz;
unsigned int gfx_cur_mhz;
unsigned int tcc_activation_temp;
unsigned int tcc_activation_temp_override;
@@ -226,6 +218,9 @@ struct msr_counter {
enum counter_type type;
enum counter_format format;
struct msr_counter *next;
+ unsigned int flags;
+#define FLAGS_HIDE (1 << 0)
+#define FLAGS_SHOW (1 << 1)
};
struct sys_counters {
@@ -341,39 +336,153 @@ int get_msr(int cpu, off_t offset, unsigned long long *msr)
}
/*
- * Example Format w/ field column widths:
- *
- * Package Core CPU Avg_MHz Bzy_MHz TSC_MHz IRQ SMI Busy% CPU_%c1 CPU_%c3 CPU_%c6 CPU_%c7 ThreadC CoreTmp CoreCnt PkgTmp GFXMHz Pkg%pc2 Pkg%pc3 Pkg%pc6 Pkg%pc7 PkgWatt CorWatt GFXWatt PkgCnt
- * 12345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678
+ * Each string in this array is compared in --show and --hide cmdline.
+ * Thus, strings that are proper sub-sets must follow their more specific peers.
*/
+struct msr_counter bic[] = {
+ { 0x0, "Package" },
+ { 0x0, "Avg_MHz" },
+ { 0x0, "Bzy_MHz" },
+ { 0x0, "TSC_MHz" },
+ { 0x0, "IRQ" },
+ { 0x0, "SMI", 32, 0, FORMAT_DELTA, NULL},
+ { 0x0, "Busy%" },
+ { 0x0, "CPU%c1" },
+ { 0x0, "CPU%c3" },
+ { 0x0, "CPU%c6" },
+ { 0x0, "CPU%c7" },
+ { 0x0, "ThreadC" },
+ { 0x0, "CoreTmp" },
+ { 0x0, "CoreCnt" },
+ { 0x0, "PkgTmp" },
+ { 0x0, "GFX%rc6" },
+ { 0x0, "GFXMHz" },
+ { 0x0, "Pkg%pc2" },
+ { 0x0, "Pkg%pc3" },
+ { 0x0, "Pkg%pc6" },
+ { 0x0, "Pkg%pc7" },
+ { 0x0, "PkgWatt" },
+ { 0x0, "CorWatt" },
+ { 0x0, "GFXWatt" },
+ { 0x0, "PkgCnt" },
+ { 0x0, "RAMWatt" },
+ { 0x0, "PKG_%" },
+ { 0x0, "RAM_%" },
+ { 0x0, "Pkg_J" },
+ { 0x0, "Cor_J" },
+ { 0x0, "GFX_J" },
+ { 0x0, "RAM_J" },
+ { 0x0, "Core" },
+ { 0x0, "CPU" },
+};
+
+#define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter))
+#define BIC_Package (1ULL << 0)
+#define BIC_Avg_MHz (1ULL << 1)
+#define BIC_Bzy_MHz (1ULL << 2)
+#define BIC_TSC_MHz (1ULL << 3)
+#define BIC_IRQ (1ULL << 4)
+#define BIC_SMI (1ULL << 5)
+#define BIC_Busy (1ULL << 6)
+#define BIC_CPU_c1 (1ULL << 7)
+#define BIC_CPU_c3 (1ULL << 8)
+#define BIC_CPU_c6 (1ULL << 9)
+#define BIC_CPU_c7 (1ULL << 10)
+#define BIC_ThreadC (1ULL << 11)
+#define BIC_CoreTmp (1ULL << 12)
+#define BIC_CoreCnt (1ULL << 13)
+#define BIC_PkgTmp (1ULL << 14)
+#define BIC_GFX_rc6 (1ULL << 15)
+#define BIC_GFXMHz (1ULL << 16)
+#define BIC_Pkgpc2 (1ULL << 17)
+#define BIC_Pkgpc3 (1ULL << 18)
+#define BIC_Pkgpc6 (1ULL << 19)
+#define BIC_Pkgpc7 (1ULL << 20)
+#define BIC_PkgWatt (1ULL << 21)
+#define BIC_CorWatt (1ULL << 22)
+#define BIC_GFXWatt (1ULL << 23)
+#define BIC_PkgCnt (1ULL << 24)
+#define BIC_RAMWatt (1ULL << 27)
+#define BIC_PKG__ (1ULL << 28)
+#define BIC_RAM__ (1ULL << 29)
+#define BIC_Pkg_J (1ULL << 30)
+#define BIC_Cor_J (1ULL << 31)
+#define BIC_GFX_J (1ULL << 30)
+#define BIC_RAM_J (1ULL << 31)
+#define BIC_Core (1ULL << 32)
+#define BIC_CPU (1ULL << 33)
+
+unsigned long long bic_enabled = 0xFFFFFFFFFFFFFFFFULL;
+unsigned long long bic_present;
+
+#define DO_BIC(COUNTER_NAME) (bic_enabled & bic_present & COUNTER_NAME)
+#define BIC_PRESENT(COUNTER_BIT) (bic_present |= COUNTER_BIT)
+
+/*
+ * bic_lookup
+ * for all the strings in comma separate name_list,
+ * set the approprate bit in return value.
+ */
+unsigned long long bic_lookup(char *name_list)
+{
+ int i;
+ unsigned long long retval = 0;
+
+ while (name_list) {
+ char *comma;
+
+ comma = strchr(name_list, ',');
+
+ if (comma)
+ *comma = '\0';
+
+ for (i = 0; i < MAX_BIC; ++i) {
+ if (!strcmp(name_list, bic[i].name)) {
+ retval |= (1ULL << i);
+ break;
+ }
+ }
+ if (i == MAX_BIC) {
+ fprintf(stderr, "Invalid counter name: %s\n", name_list);
+ exit(-1);
+ }
+
+ name_list = comma;
+ if (name_list)
+ name_list++;
+
+ }
+ return retval;
+}
void print_header(void)
{
struct msr_counter *mp;
- if (show_pkg)
+ if (DO_BIC(BIC_Package))
outp += sprintf(outp, "\tPackage");
- if (show_core)
+ if (DO_BIC(BIC_Core))
outp += sprintf(outp, "\tCore");
- if (show_cpu)
+ if (DO_BIC(BIC_CPU))
outp += sprintf(outp, "\tCPU");
- if (has_aperf)
+ if (DO_BIC(BIC_Avg_MHz))
outp += sprintf(outp, "\tAvg_MHz");
- if (has_aperf)
+ if (DO_BIC(BIC_Busy))
outp += sprintf(outp, "\tBusy%%");
- if (has_aperf)
+ if (DO_BIC(BIC_Bzy_MHz))
outp += sprintf(outp, "\tBzy_MHz");
- outp += sprintf(outp, "\tTSC_MHz");
+ if (DO_BIC(BIC_TSC_MHz))
+ outp += sprintf(outp, "\tTSC_MHz");
if (!debug)
goto done;
- if (do_irq)
+ if (DO_BIC(BIC_IRQ))
outp += sprintf(outp, "\tIRQ");
- if (do_smi)
+ if (DO_BIC(BIC_SMI))
outp += sprintf(outp, "\tSMI");
- if (do_nhm_cstates)
+ if (DO_BIC(BIC_CPU_c1))
outp += sprintf(outp, "\tCPU%%c1");
for (mp = sys.tp; mp; mp = mp->next) {
@@ -387,15 +496,15 @@ void print_header(void)
}
}
- if (do_nhm_cstates && !do_slm_cstates && !do_knl_cstates)
+ if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates)
outp += sprintf(outp, "\tCPU%%c3");
- if (do_nhm_cstates)
+ if (DO_BIC(BIC_CPU_c6))
outp += sprintf(outp, "\tCPU%%c6");
- if (do_snb_cstates)
+ if (DO_BIC(BIC_CPU_c7))
outp += sprintf(outp, "\tCPU%%c7");
- if (do_dts)
+ if (DO_BIC(BIC_CoreTmp))
outp += sprintf(outp, "\tCoreTmp");
for (mp = sys.cp; mp; mp = mp->next) {
@@ -409,13 +518,13 @@ void print_header(void)
}
}
- if (do_ptm)
+ if (DO_BIC(BIC_PkgTmp))
outp += sprintf(outp, "\tPkgTmp");
- if (do_gfx_rc6_ms)
+ if (DO_BIC(BIC_GFX_rc6))
outp += sprintf(outp, "\tGFX%%rc6");
- if (do_gfx_mhz)
+ if (DO_BIC(BIC_GFXMHz))
outp += sprintf(outp, "\tGFXMHz");
if (do_skl_residency) {
@@ -440,30 +549,30 @@ void print_header(void)
}
if (do_rapl && !rapl_joules) {
- if (do_rapl & RAPL_PKG)
+ if (DO_BIC(BIC_PkgWatt))
outp += sprintf(outp, "\tPkgWatt");
- if (do_rapl & RAPL_CORES_ENERGY_STATUS)
+ if (DO_BIC(BIC_CorWatt))
outp += sprintf(outp, "\tCorWatt");
- if (do_rapl & RAPL_GFX)
+ if (DO_BIC(BIC_GFXWatt))
outp += sprintf(outp, "\tGFXWatt");
- if (do_rapl & RAPL_DRAM)
+ if (DO_BIC(BIC_RAMWatt))
outp += sprintf(outp, "\tRAMWatt");
- if (do_rapl & RAPL_PKG_PERF_STATUS)
+ if (DO_BIC(BIC_PKG__))
outp += sprintf(outp, "\tPKG_%%");
- if (do_rapl & RAPL_DRAM_PERF_STATUS)
+ if (DO_BIC(BIC_RAM__))
outp += sprintf(outp, "\tRAM_%%");
} else if (do_rapl && rapl_joules) {
- if (do_rapl & RAPL_PKG)
+ if (DO_BIC(BIC_Pkg_J))
outp += sprintf(outp, "\tPkg_J");
- if (do_rapl & RAPL_CORES_ENERGY_STATUS)
+ if (DO_BIC(BIC_Cor_J))
outp += sprintf(outp, "\tCor_J");
- if (do_rapl & RAPL_GFX)
+ if (DO_BIC(BIC_GFX_J))
outp += sprintf(outp, "\tGFX_J");
- if (do_rapl & RAPL_DRAM)
+ if (DO_BIC(BIC_RAM_J))
outp += sprintf(outp, "\tRAM_J");
- if (do_rapl & RAPL_PKG_PERF_STATUS)
+ if (DO_BIC(BIC_PKG__))
outp += sprintf(outp, "\tPKG_%%");
- if (do_rapl & RAPL_DRAM_PERF_STATUS)
+ if (DO_BIC(BIC_RAM__))
outp += sprintf(outp, "\tRAM_%%");
}
for (mp = sys.pp; mp; mp = mp->next) {
@@ -497,9 +606,9 @@ int dump_counters(struct thread_data *t, struct core_data *c,
outp += sprintf(outp, "mperf: %016llX\n", t->mperf);
outp += sprintf(outp, "c1: %016llX\n", t->c1);
- if (do_irq)
+ if (DO_BIC(BIC_IRQ))
outp += sprintf(outp, "IRQ: %08X\n", t->irq_count);
- if (do_smi)
+ if (DO_BIC(BIC_SMI))
outp += sprintf(outp, "SMI: %08X\n", t->smi_count);
for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
@@ -583,40 +692,37 @@ int format_counters(struct thread_data *t, struct core_data *c,
/* topo columns, print blanks on 1st (average) line */
if (t == &average.threads) {
- if (show_pkg)
+ if (DO_BIC(BIC_Package))
outp += sprintf(outp, "\t-");
- if (show_core)
+ if (DO_BIC(BIC_Core))
outp += sprintf(outp, "\t-");
- if (show_cpu)
+ if (DO_BIC(BIC_CPU))
outp += sprintf(outp, "\t-");
} else {
- if (show_pkg) {
+ if (DO_BIC(BIC_Package)) {
if (p)
outp += sprintf(outp, "\t%d", p->package_id);
else
outp += sprintf(outp, "\t-");
}
- if (show_core) {
+ if (DO_BIC(BIC_Core)) {
if (c)
outp += sprintf(outp, "\t%d", c->core_id);
else
outp += sprintf(outp, "\t-");
}
- if (show_cpu)
+ if (DO_BIC(BIC_CPU))
outp += sprintf(outp, "\t%d", t->cpu_id);
}
- /* Avg_MHz */
- if (has_aperf)
+ if (DO_BIC(BIC_Avg_MHz))
outp += sprintf(outp, "\t%.0f",
1.0 / units * t->aperf / interval_float);
- /* Busy% */
- if (has_aperf)
+ if (DO_BIC(BIC_Busy))
outp += sprintf(outp, "\t%.2f", 100.0 * t->mperf/t->tsc/tsc_tweak);
- /* Bzy_MHz */
- if (has_aperf) {
+ if (DO_BIC(BIC_Bzy_MHz)) {
if (has_base_hz)
outp += sprintf(outp, "\t%.0f", base_hz / units * t->aperf / t->mperf);
else
@@ -624,22 +730,22 @@ int format_counters(struct thread_data *t, struct core_data *c,
1.0 * t->tsc / units * t->aperf / t->mperf / interval_float);
}
- /* TSC_MHz */
- outp += sprintf(outp, "\t%.0f", 1.0 * t->tsc/units/interval_float);
+ if (DO_BIC(BIC_TSC_MHz))
+ outp += sprintf(outp, "\t%.0f", 1.0 * t->tsc/units/interval_float);
if (!debug)
goto done;
/* IRQ */
- if (do_irq)
+ if (DO_BIC(BIC_IRQ))
outp += sprintf(outp, "\t%d", t->irq_count);
/* SMI */
- if (do_smi)
+ if (DO_BIC(BIC_SMI))
outp += sprintf(outp, "\t%d", t->smi_count);
/* C1 */
- if (do_nhm_cstates)
+ if (DO_BIC(BIC_CPU_c1))
outp += sprintf(outp, "\t%.2f", 100.0 * t->c1/t->tsc);
/* Added counters */
@@ -660,15 +766,14 @@ int format_counters(struct thread_data *t, struct core_data *c,
if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
goto done;
- if (do_nhm_cstates && !do_slm_cstates && !do_knl_cstates)
+ if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates)
outp += sprintf(outp, "\t%.2f", 100.0 * c->c3/t->tsc);
- if (do_nhm_cstates)
+ if (DO_BIC(BIC_CPU_c6))
outp += sprintf(outp, "\t%.2f", 100.0 * c->c6/t->tsc);
- if (do_snb_cstates)
+ if (DO_BIC(BIC_CPU_c7))
outp += sprintf(outp, "\t%.2f", 100.0 * c->c7/t->tsc);
-
- if (do_dts)
+ if (DO_BIC(BIC_CoreTmp))
outp += sprintf(outp, "\t%d", c->core_temp_c);
for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
@@ -689,11 +794,11 @@ int format_counters(struct thread_data *t, struct core_data *c,
goto done;
/* PkgTmp */
- if (do_ptm)
+ if (DO_BIC(BIC_PkgTmp))
outp += sprintf(outp, "\t%d", p->pkg_temp_c);
/* GFXrc6 */
- if (do_gfx_rc6_ms) {
+ if (DO_BIC(BIC_GFX_rc6)) {
if (p->gfx_rc6_ms == -1) { /* detect GFX counter reset */
outp += sprintf(outp, "\t**.**");
} else {
@@ -703,7 +808,7 @@ int format_counters(struct thread_data *t, struct core_data *c,
}
/* GFXMHz */
- if (do_gfx_mhz)
+ if (DO_BIC(BIC_GFXMHz))
outp += sprintf(outp, "\t%d", p->gfx_mhz);
/* Totl%C0, Any%C0 GFX%C0 CPUGFX% */
@@ -737,37 +842,27 @@ int format_counters(struct thread_data *t, struct core_data *c,
else
fmt8 = "%6.0f**";
- if (do_rapl && !rapl_joules) {
- if (do_rapl & RAPL_PKG)
- outp += sprintf(outp, fmt8, p->energy_pkg * rapl_energy_units / interval_float);
- if (do_rapl & RAPL_CORES_ENERGY_STATUS)
- outp += sprintf(outp, fmt8, p->energy_cores * rapl_energy_units / interval_float);
- if (do_rapl & RAPL_GFX)
- outp += sprintf(outp, fmt8, p->energy_gfx * rapl_energy_units / interval_float);
- if (do_rapl & RAPL_DRAM)
- outp += sprintf(outp, fmt8, p->energy_dram * rapl_dram_energy_units / interval_float);
- if (do_rapl & RAPL_PKG_PERF_STATUS)
- outp += sprintf(outp, fmt8, 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float);
- if (do_rapl & RAPL_DRAM_PERF_STATUS)
- outp += sprintf(outp, fmt8, 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float);
- } else if (do_rapl && rapl_joules) {
- if (do_rapl & RAPL_PKG)
- outp += sprintf(outp, fmt8,
- p->energy_pkg * rapl_energy_units);
- if (do_rapl & RAPL_CORES)
- outp += sprintf(outp, fmt8,
- p->energy_cores * rapl_energy_units);
- if (do_rapl & RAPL_GFX)
- outp += sprintf(outp, fmt8,
- p->energy_gfx * rapl_energy_units);
- if (do_rapl & RAPL_DRAM)
- outp += sprintf(outp, fmt8,
- p->energy_dram * rapl_dram_energy_units);
- if (do_rapl & RAPL_PKG_PERF_STATUS)
- outp += sprintf(outp, fmt8, 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float);
- if (do_rapl & RAPL_DRAM_PERF_STATUS)
- outp += sprintf(outp, fmt8, 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float);
- }
+ if (DO_BIC(BIC_PkgWatt))
+ outp += sprintf(outp, fmt8, p->energy_pkg * rapl_energy_units / interval_float);
+ if (DO_BIC(BIC_CorWatt))
+ outp += sprintf(outp, fmt8, p->energy_cores * rapl_energy_units / interval_float);
+ if (DO_BIC(BIC_GFXWatt))
+ outp += sprintf(outp, fmt8, p->energy_gfx * rapl_energy_units / interval_float);
+ if (DO_BIC(BIC_RAMWatt))
+ outp += sprintf(outp, fmt8, p->energy_dram * rapl_dram_energy_units / interval_float);
+ if (DO_BIC(BIC_Pkg_J))
+ outp += sprintf(outp, fmt8, p->energy_pkg * rapl_energy_units);
+ if (DO_BIC(BIC_Cor_J))
+ outp += sprintf(outp, fmt8, p->energy_cores * rapl_energy_units);
+ if (DO_BIC(BIC_GFX_J))
+ outp += sprintf(outp, fmt8, p->energy_gfx * rapl_energy_units);
+ if (DO_BIC(BIC_RAM_J))
+ outp += sprintf(outp, fmt8, p->energy_dram * rapl_dram_energy_units);
+ if (DO_BIC(BIC_PKG__))
+ outp += sprintf(outp, fmt8, 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float);
+ if (DO_BIC(BIC_RAM__))
+ outp += sprintf(outp, fmt8, 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float);
+
for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
if (mp->format == FORMAT_RAW) {
if (mp->width == 32)
@@ -921,7 +1016,7 @@ delta_thread(struct thread_data *new, struct thread_data *old,
old->c1 = new->c1 - old->c1;
- if (has_aperf) {
+ if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz)) {
if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) {
old->aperf = new->aperf - old->aperf;
old->mperf = new->mperf - old->mperf;
@@ -957,10 +1052,10 @@ delta_thread(struct thread_data *new, struct thread_data *old,
old->mperf = 1; /* divide by 0 protection */
}
- if (do_irq)
+ if (DO_BIC(BIC_IRQ))
old->irq_count = new->irq_count - old->irq_count;
- if (do_smi)
+ if (DO_BIC(BIC_SMI))
old->smi_count = new->smi_count - old->smi_count;
for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
@@ -1217,7 +1312,7 @@ int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
retry:
t->tsc = rdtsc(); /* we are running on local CPU of interest */
- if (has_aperf) {
+ if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz)) {
unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time;
/*
@@ -1273,9 +1368,9 @@ int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
t->mperf = t->mperf * aperf_mperf_multiplier;
}
- if (do_irq)
+ if (DO_BIC(BIC_IRQ))
t->irq_count = irqs_per_cpu[cpu];
- if (do_smi) {
+ if (DO_BIC(BIC_SMI)) {
if (get_msr(cpu, MSR_SMI_COUNT, &msr))
return -5;
t->smi_count = msr & 0xFFFFFFFF;
@@ -1296,12 +1391,12 @@ int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
return 0;
- if (do_nhm_cstates && !do_slm_cstates && !do_knl_cstates) {
+ if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates) {
if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3))
return -6;
}
- if (do_nhm_cstates && !do_knl_cstates) {
+ if (DO_BIC(BIC_CPU_c6) && !do_knl_cstates) {
if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6))
return -7;
} else if (do_knl_cstates) {
@@ -1309,11 +1404,11 @@ int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
return -7;
}
- if (do_snb_cstates)
+ if (DO_BIC(BIC_CPU_c7))
if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7))
return -8;
- if (do_dts) {
+ if (DO_BIC(BIC_CoreTmp)) {
if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
return -9;
c->core_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F);
@@ -1388,16 +1483,16 @@ int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
return -16;
p->rapl_dram_perf_status = msr & 0xFFFFFFFF;
}
- if (do_ptm) {
+ if (DO_BIC(BIC_PkgTmp)) {
if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
return -17;
p->pkg_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F);
}
- if (do_gfx_rc6_ms)
+ if (DO_BIC(BIC_GFX_rc6))
p->gfx_rc6_ms = gfx_cur_rc6_ms;
- if (do_gfx_mhz)
+ if (DO_BIC(BIC_GFXMHz))
p->gfx_mhz = gfx_cur_mhz;
for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
@@ -2155,10 +2250,10 @@ int snapshot_proc_sysfs_files(void)
if (snapshot_proc_interrupts())
return 1;
- if (do_gfx_rc6_ms)
+ if (DO_BIC(BIC_GFX_rc6))
snapshot_gfx_rc6_ms();
- if (do_gfx_mhz)
+ if (DO_BIC(BIC_GFXMHz))
snapshot_gfx_mhz();
return 0;
@@ -2794,15 +2889,39 @@ void rapl_probe(unsigned int family, unsigned int model)
case INTEL_FAM6_BROADWELL_CORE: /* BDW */
case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO;
+ if (rapl_joules) {
+ BIC_PRESENT(BIC_Pkg_J);
+ BIC_PRESENT(BIC_Cor_J);
+ BIC_PRESENT(BIC_GFX_J);
+ } else {
+ BIC_PRESENT(BIC_PkgWatt);
+ BIC_PRESENT(BIC_CorWatt);
+ BIC_PRESENT(BIC_GFXWatt);
+ }
break;
case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO;
+ if (rapl_joules)
+ BIC_PRESENT(BIC_Pkg_J);
+ else
+ BIC_PRESENT(BIC_PkgWatt);
break;
case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO;
+ BIC_PRESENT(BIC_PKG__);
+ BIC_PRESENT(BIC_RAM__);
+ if (rapl_joules) {
+ BIC_PRESENT(BIC_Pkg_J);
+ BIC_PRESENT(BIC_Cor_J);
+ BIC_PRESENT(BIC_RAM_J);
+ } else {
+ BIC_PRESENT(BIC_PkgWatt);
+ BIC_PRESENT(BIC_CorWatt);
+ BIC_PRESENT(BIC_RAMWatt);
+ }
break;
case INTEL_FAM6_HASWELL_X: /* HSX */
case INTEL_FAM6_BROADWELL_X: /* BDX */
@@ -2811,17 +2930,55 @@ void rapl_probe(unsigned int family, unsigned int model)
case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
case INTEL_FAM6_XEON_PHI_KNM:
do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO;
+ BIC_PRESENT(BIC_PKG__);
+ BIC_PRESENT(BIC_RAM__);
+ if (rapl_joules) {
+ BIC_PRESENT(BIC_Pkg_J);
+ BIC_PRESENT(BIC_RAM_J);
+ } else {
+ BIC_PRESENT(BIC_PkgWatt);
+ BIC_PRESENT(BIC_RAMWatt);
+ }
break;
case INTEL_FAM6_SANDYBRIDGE_X:
case INTEL_FAM6_IVYBRIDGE_X:
do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO;
+ BIC_PRESENT(BIC_PKG__);
+ BIC_PRESENT(BIC_RAM__);
+ if (rapl_joules) {
+ BIC_PRESENT(BIC_Pkg_J);
+ BIC_PRESENT(BIC_Cor_J);
+ BIC_PRESENT(BIC_RAM_J);
+ } else {
+ BIC_PRESENT(BIC_PkgWatt);
+ BIC_PRESENT(BIC_CorWatt);
+ BIC_PRESENT(BIC_RAMWatt);
+ }
break;
case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */
case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */
do_rapl = RAPL_PKG | RAPL_CORES;
+ if (rapl_joules) {
+ BIC_PRESENT(BIC_Pkg_J);
+ BIC_PRESENT(BIC_Cor_J);
+ } else {
+ BIC_PRESENT(BIC_PkgWatt);
+ BIC_PRESENT(BIC_CorWatt);
+ }
break;
case INTEL_FAM6_ATOM_DENVERTON: /* DNV */
do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS;
+ BIC_PRESENT(BIC_PKG__);
+ BIC_PRESENT(BIC_RAM__);
+ if (rapl_joules) {
+ BIC_PRESENT(BIC_Pkg_J);
+ BIC_PRESENT(BIC_Cor_J);
+ BIC_PRESENT(BIC_RAM_J);
+ } else {
+ BIC_PRESENT(BIC_PkgWatt);
+ BIC_PRESENT(BIC_CorWatt);
+ BIC_PRESENT(BIC_RAMWatt);
+ }
break;
default:
return;
@@ -3398,8 +3555,17 @@ void process_cpuid()
__cpuid(0x6, eax, ebx, ecx, edx);
has_aperf = ecx & (1 << 0);
+ if (has_aperf) {
+ BIC_PRESENT(BIC_Avg_MHz);
+ BIC_PRESENT(BIC_Busy);
+ BIC_PRESENT(BIC_Bzy_MHz);
+ }
do_dts = eax & (1 << 0);
+ if (do_dts)
+ BIC_PRESENT(BIC_CoreTmp);
do_ptm = eax & (1 << 6);
+ if (do_ptm)
+ BIC_PRESENT(BIC_PkgTmp);
has_hwp = eax & (1 << 7);
has_hwp_notify = eax & (1 << 8);
has_hwp_activity_window = eax & (1 << 9);
@@ -3497,8 +3663,21 @@ void process_cpuid()
if (has_aperf)
aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model);
- do_nhm_platform_info = do_nhm_cstates = do_smi = probe_nhm_msrs(family, model);
+ BIC_PRESENT(BIC_IRQ);
+ BIC_PRESENT(BIC_TSC_MHz);
+
+ if (probe_nhm_msrs(family, model)) {
+ do_nhm_platform_info = 1;
+ BIC_PRESENT(BIC_CPU_c1);
+ BIC_PRESENT(BIC_CPU_c3);
+ BIC_PRESENT(BIC_CPU_c6);
+ BIC_PRESENT(BIC_SMI);
+ }
do_snb_cstates = has_snb_msrs(family, model);
+
+ if (do_snb_cstates)
+ BIC_PRESENT(BIC_CPU_c7);
+
do_irtl_snb = has_snb_msrs(family, model);
do_pc2 = do_snb_cstates && (pkg_cstate_limit >= PCL__2);
do_pc3 = (pkg_cstate_limit >= PCL__3);
@@ -3522,9 +3701,11 @@ void process_cpuid()
if (has_skl_msrs(family, model))
calculate_tsc_tweak();
- do_gfx_rc6_ms = !access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK);
+ if (!access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK))
+ BIC_PRESENT(BIC_GFX_rc6);
- do_gfx_mhz = !access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK);
+ if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK))
+ BIC_PRESENT(BIC_GFXMHz);
return;
}
@@ -3583,7 +3764,7 @@ void topology_probe()
topo.max_cpu_num = 0;
for_all_proc_cpus(count_cpus);
if (!summary_only && topo.num_cpus > 1)
- show_cpu = 1;
+ BIC_PRESENT(BIC_CPU);
if (debug > 1)
fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num);
@@ -3644,14 +3825,14 @@ void topology_probe()
fprintf(outf, "max_core_id %d, sizing for %d cores per package\n",
max_core_id, topo.num_cores_per_pkg);
if (debug && !summary_only && topo.num_cores_per_pkg > 1)
- show_core = 1;
+ BIC_PRESENT(BIC_Core);
topo.num_packages = max_package_id + 1;
if (debug > 1)
fprintf(outf, "max_package_id %d, sizing for %d packages\n",
max_package_id, topo.num_packages);
if (debug && !summary_only && topo.num_packages > 1)
- show_pkg = 1;
+ BIC_PRESENT(BIC_Package);
topo.num_threads_per_core = max_siblings;
if (debug > 1)
@@ -4045,6 +4226,40 @@ void parse_add_command(char *add_command)
exit(1);
}
}
+/*
+ * HIDE_LIST - hide this list of counters, show the rest [default]
+ * SHOW_LIST - show this list of counters, hide the rest
+ */
+enum show_hide_mode { SHOW_LIST, HIDE_LIST } global_show_hide_mode = HIDE_LIST;
+
+int shown;
+/*
+ * parse_show_hide() - process cmdline to set default counter action
+ */
+void parse_show_hide(char *optarg, enum show_hide_mode new_mode)
+{
+ /*
+ * --show: show only those specified
+ * The 1st invocation will clear and replace the enabled mask
+ * subsequent invocations can add to it.
+ */
+ if (new_mode == SHOW_LIST) {
+ if (shown == 0)
+ bic_enabled = bic_lookup(optarg);
+ else
+ bic_enabled |= bic_lookup(optarg);
+ shown = 1;
+
+ return;
+ }
+
+ /*
+ * --hide: do not show those specified
+ * multiple invocations simply clear more bits in enabled mask
+ */
+ bic_enabled &= ~bic_lookup(optarg);
+}
+
void cmdline(int argc, char **argv)
{
int opt;
@@ -4055,10 +4270,12 @@ void cmdline(int argc, char **argv)
{"debug", no_argument, 0, 'd'},
{"interval", required_argument, 0, 'i'},
{"help", no_argument, 0, 'h'},
+ {"hide", required_argument, 0, 'H'}, // meh, -h taken by --help
{"Joules", no_argument, 0, 'J'},
{"out", required_argument, 0, 'o'},
{"Package", no_argument, 0, 'p'},
{"processor", no_argument, 0, 'p'},
+ {"show", required_argument, 0, 's'},
{"Summary", no_argument, 0, 'S'},
{"TCC", required_argument, 0, 'T'},
{"version", no_argument, 0, 'v' },
@@ -4079,6 +4296,9 @@ void cmdline(int argc, char **argv)
case 'd':
debug++;
break;
+ case 'H':
+ parse_show_hide(optarg, HIDE_LIST);
+ break;
case 'h':
default:
help();
@@ -4109,6 +4329,9 @@ void cmdline(int argc, char **argv)
case 'p':
show_core_only++;
break;
+ case 's':
+ parse_show_hide(optarg, SHOW_LIST);
+ break;
case 'S':
summary_only++;
break;
--
2.11.0.161.g6610af872
[toc] | [prev] | [next] | [standalone]
| From | Len Brown <lenb@kernel.org> |
|---|---|
| Date | 2017-03-01 06:50 +0100 |
| Subject | [PATCH 07/44] x86: msr-index.h: Define MSR_PKG_CST_CONFIG_CONTROL |
| Message-ID | <tg5jd-6MD-17@gated-at.bofh.it> |
| In reply to | #1590005 |
From: Len Brown <len.brown@intel.com> define MSR_PKG_CST_CONFIG_CONTROL (0xE2), which is the string used by Intel Documentation. We use this MSR in intel_idle and turbostat by a previous name, to be updated in the next patch. Cc: x86@kernel.org Signed-off-by: Len Brown <len.brown@intel.com> --- arch/x86/include/asm/msr-index.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 710273c617b8..975f23eefe14 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -47,6 +47,7 @@ #define MSR_PLATFORM_INFO 0x000000ce #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 +#define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 #define NHM_C3_AUTO_DEMOTE (1UL << 25) #define NHM_C1_AUTO_DEMOTE (1UL << 26) #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) -- 2.11.0.161.g6610af872
[toc] | [prev] | [next] | [standalone]
| From | Len Brown <lenb@kernel.org> |
|---|---|
| Date | 2017-03-01 06:50 +0100 |
| Subject | [PATCH 34/44] tools/power turbostat: Add --list option to show available header names |
| Message-ID | <tg5jd-6MD-19@gated-at.bofh.it> |
| In reply to | #1590005 |
From: Len Brown <len.brown@intel.com>
It is handy to know the list of column header names,
so that they can be used with --add and --skip
The new --list option shows them:
sudo ./turbostat --list --hide sysfs
,Core,CPU,Avg_MHz,Busy%,Bzy_MHz,TSC_MHz,IRQ,SMI,CPU%c1,CPU%c3,CPU%c6,CPU%c7,CoreTmp,PkgTmp,GFX%rc6,GFXMHz,PkgWatt,CorWatt,GFXWatt
Signed-off-by: Len Brown <len.brown@intel.com>
---
tools/power/x86/turbostat/turbostat.c | 118 +++++++++++++++++++---------------
1 file changed, 66 insertions(+), 52 deletions(-)
diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c
index 48b540a2fe81..7b02fbb65893 100644
--- a/tools/power/x86/turbostat/turbostat.c
+++ b/tools/power/x86/turbostat/turbostat.c
@@ -52,6 +52,7 @@ unsigned int debug;
unsigned int quiet;
unsigned int rapl_joules;
unsigned int summary_only;
+unsigned int list_header_only;
unsigned int dump_only;
unsigned int do_snb_cstates;
unsigned int do_knl_cstates;
@@ -469,133 +470,133 @@ unsigned long long bic_lookup(char *name_list)
return retval;
}
-void print_header(void)
+void print_header(char *delim)
{
struct msr_counter *mp;
if (DO_BIC(BIC_Package))
- outp += sprintf(outp, "\tPackage");
+ outp += sprintf(outp, "%sPackage", delim);
if (DO_BIC(BIC_Core))
- outp += sprintf(outp, "\tCore");
+ outp += sprintf(outp, "%sCore", delim);
if (DO_BIC(BIC_CPU))
- outp += sprintf(outp, "\tCPU");
+ outp += sprintf(outp, "%sCPU", delim);
if (DO_BIC(BIC_Avg_MHz))
- outp += sprintf(outp, "\tAvg_MHz");
+ outp += sprintf(outp, "%sAvg_MHz", delim);
if (DO_BIC(BIC_Busy))
- outp += sprintf(outp, "\tBusy%%");
+ outp += sprintf(outp, "%sBusy%%", delim);
if (DO_BIC(BIC_Bzy_MHz))
- outp += sprintf(outp, "\tBzy_MHz");
+ outp += sprintf(outp, "%sBzy_MHz", delim);
if (DO_BIC(BIC_TSC_MHz))
- outp += sprintf(outp, "\tTSC_MHz");
+ outp += sprintf(outp, "%sTSC_MHz", delim);
if (DO_BIC(BIC_IRQ))
- outp += sprintf(outp, "\tIRQ");
+ outp += sprintf(outp, "%sIRQ", delim);
if (DO_BIC(BIC_SMI))
- outp += sprintf(outp, "\tSMI");
+ outp += sprintf(outp, "%sSMI", delim);
for (mp = sys.tp; mp; mp = mp->next) {
if (mp->format == FORMAT_RAW) {
if (mp->width == 64)
- outp += sprintf(outp, "\t%18.18s", mp->name);
+ outp += sprintf(outp, "%s%18.18s", delim, mp->name);
else
- outp += sprintf(outp, "\t%10.10s", mp->name);
+ outp += sprintf(outp, "%s%10.10s", delim, mp->name);
} else {
- outp += sprintf(outp, "\t%s", mp->name);
+ outp += sprintf(outp, "%s%s", delim, mp->name);
}
}
if (DO_BIC(BIC_CPU_c1))
- outp += sprintf(outp, "\tCPU%%c1");
+ outp += sprintf(outp, "%sCPU%%c1", delim);
if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates)
- outp += sprintf(outp, "\tCPU%%c3");
+ outp += sprintf(outp, "%sCPU%%c3", delim);
if (DO_BIC(BIC_CPU_c6))
- outp += sprintf(outp, "\tCPU%%c6");
+ outp += sprintf(outp, "%sCPU%%c6", delim);
if (DO_BIC(BIC_CPU_c7))
- outp += sprintf(outp, "\tCPU%%c7");
+ outp += sprintf(outp, "%sCPU%%c7", delim);
if (DO_BIC(BIC_Mod_c6))
- outp += sprintf(outp, "\tMod%%c6");
+ outp += sprintf(outp, "%sMod%%c6", delim);
if (DO_BIC(BIC_CoreTmp))
- outp += sprintf(outp, "\tCoreTmp");
+ outp += sprintf(outp, "%sCoreTmp", delim);
for (mp = sys.cp; mp; mp = mp->next) {
if (mp->format == FORMAT_RAW) {
if (mp->width == 64)
- outp += sprintf(outp, "\t%18.18s", mp->name);
+ outp += sprintf(outp, "%s%18.18s", delim, mp->name);
else
- outp += sprintf(outp, "\t%10.10s", mp->name);
+ outp += sprintf(outp, "%s%10.10s", delim, mp->name);
} else {
- outp += sprintf(outp, "\t%s", mp->name);
+ outp += sprintf(outp, "%s%s", delim, mp->name);
}
}
if (DO_BIC(BIC_PkgTmp))
- outp += sprintf(outp, "\tPkgTmp");
+ outp += sprintf(outp, "%sPkgTmp", delim);
if (DO_BIC(BIC_GFX_rc6))
- outp += sprintf(outp, "\tGFX%%rc6");
+ outp += sprintf(outp, "%sGFX%%rc6", delim);
if (DO_BIC(BIC_GFXMHz))
- outp += sprintf(outp, "\tGFXMHz");
+ outp += sprintf(outp, "%sGFXMHz", delim);
if (do_skl_residency) {
- outp += sprintf(outp, "\tTotl%%C0");
- outp += sprintf(outp, "\tAny%%C0");
- outp += sprintf(outp, "\tGFX%%C0");
- outp += sprintf(outp, "\tCPUGFX%%");
+ outp += sprintf(outp, "%sTotl%%C0", delim);
+ outp += sprintf(outp, "%sAny%%C0", delim);
+ outp += sprintf(outp, "%sGFX%%C0", delim);
+ outp += sprintf(outp, "%sCPUGFX%%", delim);
}
if (DO_BIC(BIC_Pkgpc2))
- outp += sprintf(outp, "\tPkg%%pc2");
+ outp += sprintf(outp, "%sPkg%%pc2", delim);
if (DO_BIC(BIC_Pkgpc3))
- outp += sprintf(outp, "\tPkg%%pc3");
+ outp += sprintf(outp, "%sPkg%%pc3", delim);
if (DO_BIC(BIC_Pkgpc6))
- outp += sprintf(outp, "\tPkg%%pc6");
+ outp += sprintf(outp, "%sPkg%%pc6", delim);
if (DO_BIC(BIC_Pkgpc7))
- outp += sprintf(outp, "\tPkg%%pc7");
+ outp += sprintf(outp, "%sPkg%%pc7", delim);
if (DO_BIC(BIC_Pkgpc8))
- outp += sprintf(outp, "\tPkg%%pc8");
+ outp += sprintf(outp, "%sPkg%%pc8", delim);
if (DO_BIC(BIC_Pkgpc9))
- outp += sprintf(outp, "\tPkg%%pc9");
+ outp += sprintf(outp, "%sPkg%%pc9", delim);
if (DO_BIC(BIC_Pkgpc10))
- outp += sprintf(outp, "\tPk%%pc10");
+ outp += sprintf(outp, "%sPk%%pc10", delim);
if (do_rapl && !rapl_joules) {
if (DO_BIC(BIC_PkgWatt))
- outp += sprintf(outp, "\tPkgWatt");
+ outp += sprintf(outp, "%sPkgWatt", delim);
if (DO_BIC(BIC_CorWatt))
- outp += sprintf(outp, "\tCorWatt");
+ outp += sprintf(outp, "%sCorWatt", delim);
if (DO_BIC(BIC_GFXWatt))
- outp += sprintf(outp, "\tGFXWatt");
+ outp += sprintf(outp, "%sGFXWatt", delim);
if (DO_BIC(BIC_RAMWatt))
- outp += sprintf(outp, "\tRAMWatt");
+ outp += sprintf(outp, "%sRAMWatt", delim);
if (DO_BIC(BIC_PKG__))
- outp += sprintf(outp, "\tPKG_%%");
+ outp += sprintf(outp, "%sPKG_%%", delim);
if (DO_BIC(BIC_RAM__))
- outp += sprintf(outp, "\tRAM_%%");
+ outp += sprintf(outp, "%sRAM_%%", delim);
} else if (do_rapl && rapl_joules) {
if (DO_BIC(BIC_Pkg_J))
- outp += sprintf(outp, "\tPkg_J");
+ outp += sprintf(outp, "%sPkg_J", delim);
if (DO_BIC(BIC_Cor_J))
- outp += sprintf(outp, "\tCor_J");
+ outp += sprintf(outp, "%sCor_J", delim);
if (DO_BIC(BIC_GFX_J))
- outp += sprintf(outp, "\tGFX_J");
+ outp += sprintf(outp, "%sGFX_J", delim);
if (DO_BIC(BIC_RAM_J))
- outp += sprintf(outp, "\tRAM_J");
+ outp += sprintf(outp, "%sRAM_J", delim);
if (DO_BIC(BIC_PKG__))
- outp += sprintf(outp, "\tPKG_%%");
+ outp += sprintf(outp, "%sPKG_%%", delim);
if (DO_BIC(BIC_RAM__))
- outp += sprintf(outp, "\tRAM_%%");
+ outp += sprintf(outp, "%sRAM_%%", delim);
}
for (mp = sys.pp; mp; mp = mp->next) {
if (mp->format == FORMAT_RAW) {
if (mp->width == 64)
- outp += sprintf(outp, "\t%18.18s", mp->name);
+ outp += sprintf(outp, "%s%18.18s", delim, mp->name);
else
- outp += sprintf(outp, "\t%10.10s", mp->name);
+ outp += sprintf(outp, "%s%10.10s", delim, mp->name);
} else {
- outp += sprintf(outp, "\t%s", mp->name);
+ outp += sprintf(outp, "%s%s", delim, mp->name);
}
}
@@ -933,7 +934,7 @@ void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_
static int printed;
if (!printed || !summary_only)
- print_header();
+ print_header("\t");
if (topo.num_cpus > 1)
format_counters(&average.threads, &average.cores,
@@ -4107,6 +4108,7 @@ void help()
"--quiet skip decoding system configuration header\n"
"--interval sec Override default 5-second measurement interval\n"
"--help print this help message\n"
+ "--list list column headers only\n"
"--out file create or truncate \"file\" for all output\n"
"--version print version information\n"
"\n"
@@ -4814,6 +4816,7 @@ void cmdline(int argc, char **argv)
{"help", no_argument, 0, 'h'},
{"hide", required_argument, 0, 'H'}, // meh, -h taken by --help
{"Joules", no_argument, 0, 'J'},
+ {"list", no_argument, 0, 'l'},
{"out", required_argument, 0, 'o'},
{"Package", no_argument, 0, 'p'},
{"processor", no_argument, 0, 'p'},
@@ -4866,6 +4869,10 @@ void cmdline(int argc, char **argv)
case 'J':
rapl_joules++;
break;
+ case 'l':
+ list_header_only++;
+ quiet++;
+ break;
case 'o':
outf = fopen_or_die(optarg, "w");
break;
@@ -4912,6 +4919,13 @@ int main(int argc, char **argv)
if (dump_only)
return get_and_dump_counters();
+ /* list header and exit */
+ if (list_header_only) {
+ print_header(",");
+ flush_output_stdout();
+ return 0;
+ }
+
/*
* if any params left, it must be a command to fork
*/
--
2.11.0.161.g6610af872
[toc] | [prev] | [next] | [standalone]
| From | Len Brown <lenb@kernel.org> |
|---|---|
| Date | 2017-03-01 06:50 +0100 |
| Subject | [PATCH 30/44] tools/power turbostat: extend --add option to accept /sys path |
| Message-ID | <tg5jd-6MD-21@gated-at.bofh.it> |
| In reply to | #1590005 |
From: Len Brown <len.brown@intel.com>
Previously, the --add option could specify only an MSR.
Here is is extended so an arbitrary /sys attribute,
as specified by an absolute file path name.
sudo ./turbostat --add /sys/devices/system/cpu/cpu0/cpuidle/state5/usage
Signed-off-by: Len Brown <len.brown@intel.com>
---
tools/power/x86/turbostat/turbostat.c | 92 ++++++++++++++++++++++++++---------
1 file changed, 69 insertions(+), 23 deletions(-)
diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c
index 334c4c29d4b5..841f837e317f 100644
--- a/tools/power/x86/turbostat/turbostat.c
+++ b/tools/power/x86/turbostat/turbostat.c
@@ -138,6 +138,7 @@ unsigned int has_misc_feature_control;
* Usually truncated to 7 characters, but also handles 18 columns for raw 64-bit counters
*/
#define NAME_BYTES 20
+#define PATH_BYTES 128
int backwards_count;
char *progname;
@@ -213,6 +214,7 @@ enum counter_format {FORMAT_RAW, FORMAT_DELTA, FORMAT_PERCENT};
struct msr_counter {
unsigned int msr_num;
char name[NAME_BYTES];
+ char path[PATH_BYTES];
unsigned int width;
enum counter_type type;
enum counter_format format;
@@ -344,7 +346,7 @@ struct msr_counter bic[] = {
{ 0x0, "Bzy_MHz" },
{ 0x0, "TSC_MHz" },
{ 0x0, "IRQ" },
- { 0x0, "SMI", 32, 0, FORMAT_DELTA, NULL},
+ { 0x0, "SMI", "", 32, 0, FORMAT_DELTA, NULL},
{ 0x0, "Busy%" },
{ 0x0, "CPU%c1" },
{ 0x0, "CPU%c3" },
@@ -1308,6 +1310,51 @@ static unsigned long long rdtsc(void)
}
/*
+ * Open a file, and exit on failure
+ */
+FILE *fopen_or_die(const char *path, const char *mode)
+{
+ FILE *filep = fopen(path, mode);
+
+ if (!filep)
+ err(1, "%s: open failed", path);
+ return filep;
+}
+/*
+ * snapshot_sysfs_counter()
+ *
+ * return snapshot of given counter
+ */
+unsigned long long snapshot_sysfs_counter(char *path)
+{
+ FILE *fp;
+ int retval;
+ unsigned long long counter;
+
+ fp = fopen_or_die(path, "r");
+
+ retval = fscanf(fp, "%lld", &counter);
+ if (retval != 1)
+ err(1, "snapshot_sysfs_counter(%s)", path);
+
+ fclose(fp);
+
+ return counter;
+}
+
+int get_mp(int cpu, struct msr_counter *mp, unsigned long long *counterp)
+{
+ if (mp->msr_num != 0) {
+ if (get_msr(cpu, mp->msr_num, counterp))
+ return -1;
+ } else {
+ *counterp = snapshot_sysfs_counter(mp->path);
+ }
+
+ return 0;
+}
+
+/*
* get_counters(...)
* migrate to cpu
* acquire and record local counters for that cpu
@@ -1397,11 +1444,10 @@ int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
}
for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
- if (get_msr(cpu, mp->msr_num, &t->counter[i]))
+ if (get_mp(cpu, mp, &t->counter[i]))
return -10;
}
-
/* collect core counters only for 1st thread in core */
if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
return 0;
@@ -1434,7 +1480,7 @@ int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
}
for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
- if (get_msr(cpu, mp->msr_num, &c->counter[i]))
+ if (get_mp(cpu, mp, &c->counter[i]))
return -10;
}
@@ -1524,7 +1570,7 @@ int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
p->gfx_mhz = gfx_cur_mhz;
for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
- if (get_msr(cpu, mp->msr_num, &p->counter[i]))
+ if (get_mp(cpu, mp, &p->counter[i]))
return -10;
}
@@ -2013,16 +2059,6 @@ void free_all_buffers(void)
free(irqs_per_cpu);
}
-/*
- * Open a file, and exit on failure
- */
-FILE *fopen_or_die(const char *path, const char *mode)
-{
- FILE *filep = fopen(path, mode);
- if (!filep)
- err(1, "%s: open failed", path);
- return filep;
-}
/*
* Parse a file containing a single int.
@@ -2581,7 +2617,7 @@ int probe_nhm_msrs(unsigned int family, unsigned int model)
return 1;
}
/*
- * SLV client has supporet for unique MSRs:
+ * SLV client has support for unique MSRs:
*
* MSR_CC6_DEMOTION_POLICY_CONFIG
* MSR_MC6_DEMOTION_POLICY_CONFIG
@@ -4342,9 +4378,9 @@ void print_version() {
" - Len Brown <lenb@kernel.org>\n");
}
-int add_counter(unsigned int msr_num, char *name, unsigned int width,
- enum counter_scope scope, enum counter_type type,
- enum counter_format format)
+int add_counter(unsigned int msr_num, char *path, char *name,
+ unsigned int width, enum counter_scope scope,
+ enum counter_type type, enum counter_format format)
{
struct msr_counter *msrp;
@@ -4356,6 +4392,8 @@ int add_counter(unsigned int msr_num, char *name, unsigned int width,
msrp->msr_num = msr_num;
strncpy(msrp->name, name, NAME_BYTES);
+ if (path)
+ strncpy(msrp->path, path, PATH_BYTES);
msrp->width = width;
msrp->type = type;
msrp->format = format;
@@ -4402,6 +4440,7 @@ int add_counter(unsigned int msr_num, char *name, unsigned int width,
void parse_add_command(char *add_command)
{
int msr_num = 0;
+ char *path = NULL;
char name_buffer[NAME_BYTES] = "";
int width = 64;
int fail = 0;
@@ -4417,6 +4456,11 @@ void parse_add_command(char *add_command)
if (sscanf(add_command, "msr%d", &msr_num) == 1)
goto next;
+ if (*add_command == '/') {
+ path = add_command;
+ goto next;
+ }
+
if (sscanf(add_command, "u%d", &width) == 1) {
if ((width == 32) || (width == 64))
goto next;
@@ -4466,12 +4510,14 @@ void parse_add_command(char *add_command)
next:
add_command = strchr(add_command, ',');
- if (add_command)
+ if (add_command) {
+ *add_command = '\0';
add_command++;
+ }
}
- if (msr_num == 0) {
- fprintf(stderr, "--add: (msrDDD | msr0xXXX) required\n");
+ if ((msr_num == 0) && (path == NULL)) {
+ fprintf(stderr, "--add: (msrDDD | msr0xXXX | /path_to_counter ) required\n");
fail++;
}
@@ -4495,7 +4541,7 @@ void parse_add_command(char *add_command)
}
}
- if (add_counter(msr_num, name_buffer, width, scope, type, format))
+ if (add_counter(msr_num, path, name_buffer, width, scope, type, format))
fail++;
if (fail) {
--
2.11.0.161.g6610af872
[toc] | [prev] | [next] | [standalone]
| From | Len Brown <lenb@kernel.org> |
|---|---|
| Date | 2017-03-01 06:50 +0100 |
| Subject | [PATCH 41/44] tools/power turbostat: dump p-state software config |
| Message-ID | <tg5jd-6MD-23@gated-at.bofh.it> |
| In reply to | #1590005 |
From: Len Brown <len.brown@intel.com>
cpu1: cpufreq driver: acpi-cpufreq
cpu1: cpufreq governor: ondemand
cpufreq boost: 1
or
cpu0: cpufreq driver: intel_pstate
cpu0: cpufreq governor: powersave
cpufreq intel_pstate no_turbo: 0
Signed-off-by: Len Brown <len.brown@intel.com>
---
tools/power/x86/turbostat/turbostat.c | 50 +++++++++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c
index 2c674ad5ab80..7af5f42a9792 100644
--- a/tools/power/x86/turbostat/turbostat.c
+++ b/tools/power/x86/turbostat/turbostat.c
@@ -2979,6 +2979,54 @@ dump_sysfs_cstate_config(void)
fclose(input);
}
}
+static void
+dump_sysfs_pstate_config(void)
+{
+ char path[64];
+ char driver_buf[64];
+ char governor_buf[64];
+ FILE *input;
+ int turbo;
+
+ sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_driver",
+ base_cpu);
+ input = fopen(path, "r");
+ if (input == NULL) {
+ fprintf(stderr, "NSFOD %s\n", path);
+ return;
+ }
+ fgets(driver_buf, sizeof(driver_buf), input);
+ fclose(input);
+
+ sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_governor",
+ base_cpu);
+ input = fopen(path, "r");
+ if (input == NULL) {
+ fprintf(stderr, "NSFOD %s\n", path);
+ return;
+ }
+ fgets(governor_buf, sizeof(governor_buf), input);
+ fclose(input);
+
+ fprintf(outf, "cpu%d: cpufreq driver: %s", base_cpu, driver_buf);
+ fprintf(outf, "cpu%d: cpufreq governor: %s", base_cpu, governor_buf);
+
+ sprintf(path, "/sys/devices/system/cpu/cpufreq/boost");
+ input = fopen(path, "r");
+ if (input != NULL) {
+ fscanf(input, "%d", &turbo);
+ fprintf(outf, "cpufreq boost: %d\n", turbo);
+ fclose(input);
+ }
+
+ sprintf(path, "/sys/devices/system/cpu/intel_pstate/no_turbo");
+ input = fopen(path, "r");
+ if (input != NULL) {
+ fscanf(input, "%d", &turbo);
+ fprintf(outf, "cpufreq intel_pstate no_turbo: %d\n", turbo);
+ fclose(input);
+ }
+}
/*
@@ -4168,6 +4216,8 @@ void process_cpuid()
if (!quiet)
dump_sysfs_cstate_config();
+ if (!quiet)
+ dump_sysfs_pstate_config();
if (has_skl_msrs(family, model))
calculate_tsc_tweak();
--
2.11.0.161.g6610af872
[toc] | [prev] | [next] | [standalone]
| From | Len Brown <lenb@kernel.org> |
|---|---|
| Date | 2017-03-01 07:00 +0100 |
| Subject | [PATCH 05/44] tools/power turbostat: Baytrail: remove debug line in quiet mode |
| Message-ID | <tg5sR-6RT-5@gated-at.bofh.it> |
| In reply to | #1590005 |
From: Len Brown <len.brown@intel.com> Without --debug, a debug line was printed on Baytrail: SLM BCLK: 83.3 Mhz Signed-off-by: Len Brown <len.brown@intel.com> --- tools/power/x86/turbostat/turbostat.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c index 1b762f67e3e2..9b35c9bb0489 100644 --- a/tools/power/x86/turbostat/turbostat.c +++ b/tools/power/x86/turbostat/turbostat.c @@ -3388,7 +3388,8 @@ double slm_bclk(void) } freq = slm_freq_table[i]; - fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq); + if (debug) + fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq); return freq; } -- 2.11.0.161.g6610af872
[toc] | [prev] | [next] | [standalone]
| From | Len Brown <lenb@kernel.org> |
|---|---|
| Date | 2017-03-01 07:00 +0100 |
| Subject | [PATCH 03/44] tools/power turbostat: BYT does not have MSR_MISC_PWR_MGMT |
| Message-ID | <tg5sR-6RT-3@gated-at.bofh.it> |
| In reply to | #1590005 |
From: Len Brown <len.brown@intel.com>
and so --debug fails with:
turbostat: msr 1 offset 0x1aa read failed: Input/output error
It seems that baytrail, and airmont do not have this MSR.
It is included in subsequent Goldmont Atom.
Signed-off-by: Len Brown <len.brown@intel.com>
---
tools/power/x86/turbostat/turbostat.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c
index fff280b50af0..fdf0273465fa 100644
--- a/tools/power/x86/turbostat/turbostat.c
+++ b/tools/power/x86/turbostat/turbostat.c
@@ -70,6 +70,7 @@ unsigned int units = 1000000; /* MHz etc */
unsigned int genuine_intel;
unsigned int has_invariant_tsc;
unsigned int do_nhm_platform_info;
+unsigned int no_MSR_MISC_PWR_MGMT;
unsigned int aperf_mperf_multiplier = 1;
double bclk;
double base_hz;
@@ -330,7 +331,7 @@ int get_msr(int cpu, off_t offset, unsigned long long *msr)
retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset);
if (retval != sizeof *msr)
- err(-1, "msr %d offset 0x%llx read failed", cpu, (unsigned long long)offset);
+ err(-1, "cpu%d: msr offset 0x%llx read failed", cpu, (unsigned long long)offset);
return 0;
}
@@ -2384,6 +2385,8 @@ void check_permissions()
* MSR_PLATFORM_INFO 0x000000ce
* MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2
*
+ * MSR_MISC_PWR_MGMT 0x000001aa
+ *
* MSR_PKG_C3_RESIDENCY 0x000003f8
* MSR_PKG_C6_RESIDENCY 0x000003f9
* MSR_CORE_C3_RESIDENCY 0x000003fc
@@ -2440,11 +2443,13 @@ int probe_nhm_msrs(unsigned int family, unsigned int model)
pkg_cstate_limits = skx_pkg_cstate_limits;
break;
case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */
+ no_MSR_MISC_PWR_MGMT = 1;
case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */
pkg_cstate_limits = slv_pkg_cstate_limits;
break;
case INTEL_FAM6_ATOM_AIRMONT: /* AMT */
pkg_cstate_limits = amt_pkg_cstate_limits;
+ no_MSR_MISC_PWR_MGMT = 1;
break;
case INTEL_FAM6_XEON_PHI_KNL: /* PHI */
case INTEL_FAM6_XEON_PHI_KNM:
@@ -3481,6 +3486,9 @@ void decode_misc_pwr_mgmt_msr(void)
if (!do_nhm_platform_info)
return;
+ if (no_MSR_MISC_PWR_MGMT)
+ return;
+
if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr))
fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n",
base_cpu, msr,
@@ -4061,7 +4069,7 @@ int get_and_dump_counters(void)
}
void print_version() {
- fprintf(outf, "turbostat version 4.16 24 Dec 2016"
+ fprintf(outf, "turbostat version 4.17 1 Jan 2017"
" - Len Brown <lenb@kernel.org>\n");
}
--
2.11.0.161.g6610af872
[toc] | [prev] | [next] | [standalone]
| From | Len Brown <lenb@kernel.org> |
|---|---|
| Date | 2017-03-01 07:00 +0100 |
| Subject | [PATCH 12/44] tools/power turbostat: add precision to --debug frequency output |
| Message-ID | <tg5sR-6RT-7@gated-at.bofh.it> |
| In reply to | #1590005 |
From: Len Brown <len.brown@intel.com> Add a digit of precision to the --debug output for frequency range. This is useful when BCLK is not an integer. old: 6 * 83 = 500 MHz max efficiency frequency 26 * 83 = 2166 MHz base frequency new: 6 * 83.3 = 499.8 MHz max efficiency frequency 26 * 83.3 = 2165.8 MHz base frequency Signed-off-by: Len Brown <len.brown@intel.com> --- tools/power/x86/turbostat/turbostat.c | 42 +++++++++++++++++------------------ 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c index 19802be6dc02..762b81497c3b 100644 --- a/tools/power/x86/turbostat/turbostat.c +++ b/tools/power/x86/turbostat/turbostat.c @@ -1581,11 +1581,11 @@ dump_nhm_platform_info(void) fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr); ratio = (msr >> 40) & 0xFF; - fprintf(outf, "%d * %.0f = %.0f MHz max efficiency frequency\n", + fprintf(outf, "%d * %.1f = %.1f MHz max efficiency frequency\n", ratio, bclk, ratio * bclk); ratio = (msr >> 8) & 0xFF; - fprintf(outf, "%d * %.0f = %.0f MHz base frequency\n", + fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", ratio, bclk, ratio * bclk); get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr); @@ -1607,12 +1607,12 @@ dump_hsw_turbo_ratio_limits(void) ratio = (msr >> 8) & 0xFF; if (ratio) - fprintf(outf, "%d * %.0f = %.0f MHz max turbo 18 active cores\n", + fprintf(outf, "%d * %.1f = %.1f MHz max turbo 18 active cores\n", ratio, bclk, ratio * bclk); ratio = (msr >> 0) & 0xFF; if (ratio) - fprintf(outf, "%d * %.0f = %.0f MHz max turbo 17 active cores\n", + fprintf(outf, "%d * %.1f = %.1f MHz max turbo 17 active cores\n", ratio, bclk, ratio * bclk); return; } @@ -1629,42 +1629,42 @@ dump_ivt_turbo_ratio_limits(void) ratio = (msr >> 56) & 0xFF; if (ratio) - fprintf(outf, "%d * %.0f = %.0f MHz max turbo 16 active cores\n", + fprintf(outf, "%d * %.1f = %.1f MHz max turbo 16 active cores\n", ratio, bclk, ratio * bclk); ratio = (msr >> 48) & 0xFF; if (ratio) - fprintf(outf, "%d * %.0f = %.0f MHz max turbo 15 active cores\n", + fprintf(outf, "%d * %.1f = %.1f MHz max turbo 15 active cores\n", ratio, bclk, ratio * bclk); ratio = (msr >> 40) & 0xFF; if (ratio) - fprintf(outf, "%d * %.0f = %.0f MHz max turbo 14 active cores\n", + fprintf(outf, "%d * %.1f = %.1f MHz max turbo 14 active cores\n", ratio, bclk, ratio * bclk); ratio = (msr >> 32) & 0xFF; if (ratio) - fprintf(outf, "%d * %.0f = %.0f MHz max turbo 13 active cores\n", + fprintf(outf, "%d * %.1f = %.1f MHz max turbo 13 active cores\n", ratio, bclk, ratio * bclk); ratio = (msr >> 24) & 0xFF; if (ratio) - fprintf(outf, "%d * %.0f = %.0f MHz max turbo 12 active cores\n", + fprintf(outf, "%d * %.1f = %.1f MHz max turbo 12 active cores\n", ratio, bclk, ratio * bclk); ratio = (msr >> 16) & 0xFF; if (ratio) - fprintf(outf, "%d * %.0f = %.0f MHz max turbo 11 active cores\n", + fprintf(outf, "%d * %.1f = %.1f MHz max turbo 11 active cores\n", ratio, bclk, ratio * bclk); ratio = (msr >> 8) & 0xFF; if (ratio) - fprintf(outf, "%d * %.0f = %.0f MHz max turbo 10 active cores\n", + fprintf(outf, "%d * %.1f = %.1f MHz max turbo 10 active cores\n", ratio, bclk, ratio * bclk); ratio = (msr >> 0) & 0xFF; if (ratio) - fprintf(outf, "%d * %.0f = %.0f MHz max turbo 9 active cores\n", + fprintf(outf, "%d * %.1f = %.1f MHz max turbo 9 active cores\n", ratio, bclk, ratio * bclk); return; } @@ -1681,42 +1681,42 @@ dump_nhm_turbo_ratio_limits(void) ratio = (msr >> 56) & 0xFF; if (ratio) - fprintf(outf, "%d * %.0f = %.0f MHz max turbo 8 active cores\n", + fprintf(outf, "%d * %.1f = %.1f MHz max turbo 8 active cores\n", ratio, bclk, ratio * bclk); ratio = (msr >> 48) & 0xFF; if (ratio) - fprintf(outf, "%d * %.0f = %.0f MHz max turbo 7 active cores\n", + fprintf(outf, "%d * %.1f = %.1f MHz max turbo 7 active cores\n", ratio, bclk, ratio * bclk); ratio = (msr >> 40) & 0xFF; if (ratio) - fprintf(outf, "%d * %.0f = %.0f MHz max turbo 6 active cores\n", + fprintf(outf, "%d * %.1f = %.1f MHz max turbo 6 active cores\n", ratio, bclk, ratio * bclk); ratio = (msr >> 32) & 0xFF; if (ratio) - fprintf(outf, "%d * %.0f = %.0f MHz max turbo 5 active cores\n", + fprintf(outf, "%d * %.1f = %.1f MHz max turbo 5 active cores\n", ratio, bclk, ratio * bclk); ratio = (msr >> 24) & 0xFF; if (ratio) - fprintf(outf, "%d * %.0f = %.0f MHz max turbo 4 active cores\n", + fprintf(outf, "%d * %.1f = %.1f MHz max turbo 4 active cores\n", ratio, bclk, ratio * bclk); ratio = (msr >> 16) & 0xFF; if (ratio) - fprintf(outf, "%d * %.0f = %.0f MHz max turbo 3 active cores\n", + fprintf(outf, "%d * %.1f = %.1f MHz max turbo 3 active cores\n", ratio, bclk, ratio * bclk); ratio = (msr >> 8) & 0xFF; if (ratio) - fprintf(outf, "%d * %.0f = %.0f MHz max turbo 2 active cores\n", + fprintf(outf, "%d * %.1f = %.1f MHz max turbo 2 active cores\n", ratio, bclk, ratio * bclk); ratio = (msr >> 0) & 0xFF; if (ratio) - fprintf(outf, "%d * %.0f = %.0f MHz max turbo 1 active cores\n", + fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active cores\n", ratio, bclk, ratio * bclk); return; } @@ -1776,7 +1776,7 @@ dump_knl_turbo_ratio_limits(void) for (i = buckets_no - 1; i >= 0; i--) if (i > 0 ? ratio[i] != ratio[i - 1] : 1) fprintf(outf, - "%d * %.0f = %.0f MHz max turbo %d active cores\n", + "%d * %.1f = %.1f MHz max turbo %d active cores\n", ratio[i], bclk, ratio[i] * bclk, cores[i]); } -- 2.11.0.161.g6610af872
[toc] | [prev] | [next] | [standalone]
| From | Len Brown <lenb@kernel.org> |
|---|---|
| Date | 2017-03-01 07:00 +0100 |
| Subject | [PATCH 40/44] tools/power turbostat: show package number, even without --debug |
| Message-ID | <tg5sR-6RT-9@gated-at.bofh.it> |
| In reply to | #1590005 |
From: Len Brown <len.brown@intel.com> On multi-package systems, the "Package" column was being displayed only if --debug was used. Show it always. Signed-off-by: Len Brown <len.brown@intel.com> --- tools/power/x86/turbostat/turbostat.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c index 596259f48f50..2c674ad5ab80 100644 --- a/tools/power/x86/turbostat/turbostat.c +++ b/tools/power/x86/turbostat/turbostat.c @@ -4294,7 +4294,7 @@ void topology_probe() if (debug > 1) fprintf(outf, "max_package_id %d, sizing for %d packages\n", max_package_id, topo.num_packages); - if (debug && !summary_only && topo.num_packages > 1) + if (!summary_only && topo.num_packages > 1) BIC_PRESENT(BIC_Package); topo.num_threads_per_core = max_siblings; -- 2.11.0.161.g6610af872
[toc] | [prev] | [next] | [standalone]
| From | Len Brown <lenb@kernel.org> |
|---|---|
| Date | 2017-03-01 07:00 +0100 |
| Subject | [PATCH 08/44] intel_idle: use new name for MSR_PKG_CST_CONFIG_CONTROL |
| Message-ID | <tg5sS-6RT-19@gated-at.bofh.it> |
| In reply to | #1590005 |
From: Len Brown <len.brown@intel.com>
previously known as MSR_NHM_SNB_PKG_CST_CFG_CTL
Signed-off-by: Len Brown <len.brown@intel.com>
---
drivers/idle/intel_idle.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
index 7d8ea3d5fda6..930537da76d4 100644
--- a/drivers/idle/intel_idle.c
+++ b/drivers/idle/intel_idle.c
@@ -961,9 +961,9 @@ static void auto_demotion_disable(void)
{
unsigned long long msr_bits;
- rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
+ rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_bits);
msr_bits &= ~(icpu->auto_demotion_disable_flags);
- wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
+ wrmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_bits);
}
static void c1e_promotion_disable(void)
{
@@ -1273,7 +1273,7 @@ static void sklh_idle_state_table_update(void)
if ((mwait_substates & (0xF << 28)) == 0)
return;
- rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr);
+ rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr);
/* PC10 is not enabled in PKG C-state limit */
if ((msr & 0xF) != 8)
--
2.11.0.161.g6610af872
[toc] | [prev] | [next] | [standalone]
| From | Len Brown <lenb@kernel.org> |
|---|---|
| Date | 2017-03-01 07:00 +0100 |
| Subject | [PATCH 14/44] x86 msr-index.h: Define Atom specific core ratio MSR locations |
| Message-ID | <tg5sS-6RT-21@gated-at.bofh.it> |
| In reply to | #1590005 |
From: Len Brown <len.brown@intel.com> These MSRs are currently used by the intel_pstate driver, using a local definition. Cc: x86@kernel.org Signed-off-by: Len Brown <len.brown@intel.com> --- arch/x86/include/asm/msr-index.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 079db99f6560..83bc672c225c 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -209,6 +209,12 @@ #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 +#define MSR_ATOM_CORE_RATIOS 0x0000066a +#define MSR_ATOM_CORE_VIDS 0x0000066b +#define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c +#define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d + + #define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 #define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 #define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 -- 2.11.0.161.g6610af872
[toc] | [prev] | [next] | [standalone]
| From | Len Brown <lenb@kernel.org> |
|---|---|
| Date | 2017-03-01 07:40 +0100 |
| Subject | [PATCH 10/44] x86: msr-index.h: Remove unused MSR_NHM_SNB_PKG_CST_CFG_CTL |
| Message-ID | <tg65A-7nF-3@gated-at.bofh.it> |
| In reply to | #1590005 |
From: Len Brown <len.brown@intel.com> The two users, intel_idle driver and turbostat utility are using the new name, MSR_PKG_CST_CONFIG_CONTROL Cc: x86@kernel.org Signed-off-by: Len Brown <len.brown@intel.com> --- arch/x86/include/asm/msr-index.h | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 975f23eefe14..12ecc6c1e7f8 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -46,7 +46,6 @@ #define MSR_FSB_FREQ 0x000000cd #define MSR_PLATFORM_INFO 0x000000ce -#define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 #define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 #define NHM_C3_AUTO_DEMOTE (1UL << 25) #define NHM_C1_AUTO_DEMOTE (1UL << 26) -- 2.11.0.161.g6610af872
[toc] | [prev] | [next] | [standalone]
| From | Len Brown <lenb@kernel.org> |
|---|---|
| Date | 2017-03-01 07:50 +0100 |
| Subject | [PATCH 01/44] tools/power turbostat: fix bugs in --add option |
| Message-ID | <tg6ff-7wF-1@gated-at.bofh.it> |
| In reply to | #1590005 |
From: Len Brown <len.brown@intel.com>
When --add was used more than once, overflowed buffers
caused some counters to be stored on top of others,
corrupting the results. Simplify the code by simply
reserving space for up to 16 added counters per each
cpu, core, package.
Per-cpu added counters were being printed only per-core.
Signed-off-by: Len Brown <len.brown@intel.com>
---
tools/power/x86/turbostat/turbostat.c | 88 +++++++++++++++++++++--------------
1 file changed, 52 insertions(+), 36 deletions(-)
diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c
index f13f61b065c6..c7fadf0faa4b 100644
--- a/tools/power/x86/turbostat/turbostat.c
+++ b/tools/power/x86/turbostat/turbostat.c
@@ -154,6 +154,7 @@ char *progname;
cpu_set_t *cpu_present_set, *cpu_affinity_set;
size_t cpu_present_setsize, cpu_affinity_setsize;
+#define MAX_ADDED_COUNTERS 16
struct thread_data {
unsigned long long tsc;
@@ -166,7 +167,7 @@ struct thread_data {
unsigned int flags;
#define CPU_IS_FIRST_THREAD_IN_CORE 0x2
#define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4
- unsigned long long counter[1];
+ unsigned long long counter[MAX_ADDED_COUNTERS];
} *thread_even, *thread_odd;
struct core_data {
@@ -175,7 +176,7 @@ struct core_data {
unsigned long long c7;
unsigned int core_temp_c;
unsigned int core_id;
- unsigned long long counter[1];
+ unsigned long long counter[MAX_ADDED_COUNTERS];
} *core_even, *core_odd;
struct pkg_data {
@@ -200,7 +201,7 @@ struct pkg_data {
unsigned int rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */
unsigned int rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */
unsigned int pkg_temp_c;
- unsigned long long counter[1];
+ unsigned long long counter[MAX_ADDED_COUNTERS];
} *package_even, *package_odd;
#define ODD_COUNTERS thread_odd, core_odd, package_odd
@@ -228,9 +229,9 @@ struct msr_counter {
};
struct sys_counters {
- unsigned int thread_counter_bytes;
- unsigned int core_counter_bytes;
- unsigned int package_counter_bytes;
+ unsigned int added_thread_counters;
+ unsigned int added_core_counters;
+ unsigned int added_package_counters;
struct msr_counter *tp;
struct msr_counter *cp;
struct msr_counter *pp;
@@ -374,12 +375,6 @@ void print_header(void)
if (do_nhm_cstates)
outp += sprintf(outp, "\tCPU%%c1");
- if (do_nhm_cstates && !do_slm_cstates && !do_knl_cstates)
- outp += sprintf(outp, "\tCPU%%c3");
- if (do_nhm_cstates)
- outp += sprintf(outp, "\tCPU%%c6");
- if (do_snb_cstates)
- outp += sprintf(outp, "\tCPU%%c7");
for (mp = sys.tp; mp; mp = mp->next) {
if (mp->format == FORMAT_RAW) {
@@ -392,6 +387,14 @@ void print_header(void)
}
}
+ if (do_nhm_cstates && !do_slm_cstates && !do_knl_cstates)
+ outp += sprintf(outp, "\tCPU%%c3");
+ if (do_nhm_cstates)
+ outp += sprintf(outp, "\tCPU%%c6");
+ if (do_snb_cstates)
+ outp += sprintf(outp, "\tCPU%%c7");
+
+
if (do_dts)
outp += sprintf(outp, "\tCoreTmp");
@@ -635,20 +638,11 @@ int format_counters(struct thread_data *t, struct core_data *c,
if (do_smi)
outp += sprintf(outp, "\t%d", t->smi_count);
+ /* C1 */
if (do_nhm_cstates)
outp += sprintf(outp, "\t%.2f", 100.0 * t->c1/t->tsc);
- /* print per-core data only for 1st thread in core */
- if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
- goto done;
-
- if (do_nhm_cstates && !do_slm_cstates && !do_knl_cstates)
- outp += sprintf(outp, "\t%.2f", 100.0 * c->c3/t->tsc);
- if (do_nhm_cstates)
- outp += sprintf(outp, "\t%.2f", 100.0 * c->c6/t->tsc);
- if (do_snb_cstates)
- outp += sprintf(outp, "\t%.2f", 100.0 * c->c7/t->tsc);
-
+ /* Added counters */
for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
if (mp->format == FORMAT_RAW) {
if (mp->width == 32)
@@ -656,12 +650,23 @@ int format_counters(struct thread_data *t, struct core_data *c,
else
outp += sprintf(outp, "\t0x%016llx", t->counter[i]);
} else if (mp->format == FORMAT_DELTA) {
- outp += sprintf(outp, "\t%8lld", t->counter[i]);
+ outp += sprintf(outp, "\t%lld", t->counter[i]);
} else if (mp->format == FORMAT_PERCENT) {
outp += sprintf(outp, "\t%.2f", 100.0 * t->counter[i]/t->tsc);
}
}
+ /* print per-core data only for 1st thread in core */
+ if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
+ goto done;
+
+ if (do_nhm_cstates && !do_slm_cstates && !do_knl_cstates)
+ outp += sprintf(outp, "\t%.2f", 100.0 * c->c3/t->tsc);
+ if (do_nhm_cstates)
+ outp += sprintf(outp, "\t%.2f", 100.0 * c->c6/t->tsc);
+ if (do_snb_cstates)
+ outp += sprintf(outp, "\t%.2f", 100.0 * c->c7/t->tsc);
+
if (do_dts)
outp += sprintf(outp, "\t%d", c->core_temp_c);
@@ -673,7 +678,7 @@ int format_counters(struct thread_data *t, struct core_data *c,
else
outp += sprintf(outp, "\t0x%016llx", c->counter[i]);
} else if (mp->format == FORMAT_DELTA) {
- outp += sprintf(outp, "\t%8lld", c->counter[i]);
+ outp += sprintf(outp, "\t%lld", c->counter[i]);
} else if (mp->format == FORMAT_PERCENT) {
outp += sprintf(outp, "\t%.2f", 100.0 * c->counter[i]/t->tsc);
}
@@ -770,7 +775,7 @@ int format_counters(struct thread_data *t, struct core_data *c,
else
outp += sprintf(outp, "\t0x%016llx", p->counter[i]);
} else if (mp->format == FORMAT_DELTA) {
- outp += sprintf(outp, "\t%8lld", p->counter[i]);
+ outp += sprintf(outp, "\t%lld", p->counter[i]);
} else if (mp->format == FORMAT_PERCENT) {
outp += sprintf(outp, "\t%.2f", 100.0 * p->counter[i]/t->tsc);
}
@@ -1036,7 +1041,6 @@ void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data
p->gfx_rc6_ms = 0;
p->gfx_mhz = 0;
-
for (i = 0, mp = sys.tp; mp; i++, mp = mp->next)
t->counter[i] = 0;
@@ -3662,7 +3666,7 @@ allocate_counters(struct thread_data **t, struct core_data **c, struct pkg_data
int i;
*t = calloc(topo.num_threads_per_core * topo.num_cores_per_pkg *
- topo.num_packages, sizeof(struct thread_data) + sys.thread_counter_bytes);
+ topo.num_packages, sizeof(struct thread_data));
if (*t == NULL)
goto error;
@@ -3671,14 +3675,14 @@ allocate_counters(struct thread_data **t, struct core_data **c, struct pkg_data
(*t)[i].cpu_id = -1;
*c = calloc(topo.num_cores_per_pkg * topo.num_packages,
- sizeof(struct core_data) + sys.core_counter_bytes);
+ sizeof(struct core_data));
if (*c == NULL)
goto error;
for (i = 0; i < topo.num_cores_per_pkg * topo.num_packages; i++)
(*c)[i].core_id = -1;
- *p = calloc(topo.num_packages, sizeof(struct pkg_data) + sys.package_counter_bytes);
+ *p = calloc(topo.num_packages, sizeof(struct pkg_data));
if (*p == NULL)
goto error;
@@ -3901,24 +3905,36 @@ int add_counter(unsigned int msr_num, char *name, unsigned int width,
switch (scope) {
case SCOPE_CPU:
- sys.thread_counter_bytes += 64;
msrp->next = sys.tp;
sys.tp = msrp;
- sys.thread_counter_bytes += sizeof(unsigned long long);
+ sys.added_thread_counters++;
+ if (sys.added_thread_counters > MAX_ADDED_COUNTERS) {
+ fprintf(stderr, "exceeded max %d added thread counters\n",
+ MAX_ADDED_COUNTERS);
+ exit(-1);
+ }
break;
case SCOPE_CORE:
- sys.core_counter_bytes += 64;
msrp->next = sys.cp;
sys.cp = msrp;
- sys.core_counter_bytes += sizeof(unsigned long long);
+ sys.added_core_counters++;
+ if (sys.added_core_counters > MAX_ADDED_COUNTERS) {
+ fprintf(stderr, "exceeded max %d added core counters\n",
+ MAX_ADDED_COUNTERS);
+ exit(-1);
+ }
break;
case SCOPE_PACKAGE:
- sys.package_counter_bytes += 64;
msrp->next = sys.pp;
sys.pp = msrp;
- sys.package_counter_bytes += sizeof(unsigned long long);
+ sys.added_package_counters++;
+ if (sys.added_package_counters > MAX_ADDED_COUNTERS) {
+ fprintf(stderr, "exceeded max %d added package counters\n",
+ MAX_ADDED_COUNTERS);
+ exit(-1);
+ }
break;
}
--
2.11.0.161.g6610af872
[toc] | [prev] | [next] | [standalone]
| From | Len Brown <lenb@kernel.org> |
|---|---|
| Date | 2017-03-01 08:20 +0100 |
| Subject | [PATCH 16/44] tools/power turbostat: dump Atom P-states correctly |
| Message-ID | <tg6Ih-80f-3@gated-at.bofh.it> |
| In reply to | #1590005 |
From: Len Brown <len.brown@intel.com>
Turbostat dumps MSR_TURBO_RATIO_LIMIT on Core Architecture.
But Atom Architecture uses MSR_ATOM_CORE_RATIOS and
MSR_ATOM_CORE_TURBO_RATIOS.
Signed-off-by: Len Brown <len.brown@intel.com>
---
tools/power/x86/turbostat/turbostat.c | 103 +++++++++++++++++++++++++++-------
1 file changed, 82 insertions(+), 21 deletions(-)
diff --git a/tools/power/x86/turbostat/turbostat.c b/tools/power/x86/turbostat/turbostat.c
index a1ec9d816dfa..da6ec640caf7 100644
--- a/tools/power/x86/turbostat/turbostat.c
+++ b/tools/power/x86/turbostat/turbostat.c
@@ -1722,6 +1722,54 @@ dump_nhm_turbo_ratio_limits(void)
}
static void
+dump_atom_turbo_ratio_limits(void)
+{
+ unsigned long long msr;
+ unsigned int ratio;
+
+ get_msr(base_cpu, MSR_ATOM_CORE_RATIOS, &msr);
+ fprintf(outf, "cpu%d: MSR_ATOM_CORE_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF);
+
+ ratio = (msr >> 0) & 0x3F;
+ if (ratio)
+ fprintf(outf, "%d * %.1f = %.1f MHz minimum operating frequency\n",
+ ratio, bclk, ratio * bclk);
+
+ ratio = (msr >> 8) & 0x3F;
+ if (ratio)
+ fprintf(outf, "%d * %.1f = %.1f MHz low frequency mode (LFM)\n",
+ ratio, bclk, ratio * bclk);
+
+ ratio = (msr >> 16) & 0x3F;
+ if (ratio)
+ fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n",
+ ratio, bclk, ratio * bclk);
+
+ get_msr(base_cpu, MSR_ATOM_CORE_TURBO_RATIOS, &msr);
+ fprintf(outf, "cpu%d: MSR_ATOM_CORE_TURBO_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF);
+
+ ratio = (msr >> 24) & 0x3F;
+ if (ratio)
+ fprintf(outf, "%d * %.1f = %.1f MHz max turbo 4 active cores\n",
+ ratio, bclk, ratio * bclk);
+
+ ratio = (msr >> 16) & 0x3F;
+ if (ratio)
+ fprintf(outf, "%d * %.1f = %.1f MHz max turbo 3 active cores\n",
+ ratio, bclk, ratio * bclk);
+
+ ratio = (msr >> 8) & 0x3F;
+ if (ratio)
+ fprintf(outf, "%d * %.1f = %.1f MHz max turbo 2 active cores\n",
+ ratio, bclk, ratio * bclk);
+
+ ratio = (msr >> 0) & 0x3F;
+ if (ratio)
+ fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active core\n",
+ ratio, bclk, ratio * bclk);
+}
+
+static void
dump_knl_turbo_ratio_limits(void)
{
const unsigned int buckets_no = 7;
@@ -2496,8 +2544,32 @@ int probe_nhm_msrs(unsigned int family, unsigned int model)
has_base_hz = 1;
return 1;
}
+/*
+ * SLV client has supporet for unique MSRs:
+ *
+ * MSR_CC6_DEMOTION_POLICY_CONFIG
+ * MSR_MC6_DEMOTION_POLICY_CONFIG
+ */
+
+int has_slv_msrs(unsigned int family, unsigned int model)
+{
+ if (!genuine_intel)
+ return 0;
+
+ switch (model) {
+ case INTEL_FAM6_ATOM_SILVERMONT1:
+ case INTEL_FAM6_ATOM_MERRIFIELD:
+ case INTEL_FAM6_ATOM_MOOREFIELD:
+ return 1;
+ }
+ return 0;
+}
+
int has_nhm_turbo_ratio_limit(unsigned int family, unsigned int model)
{
+ if (has_slv_msrs(family, model))
+ return 0;
+
switch (model) {
/* Nehalem compatible, but do not include turbo-ratio limit support */
case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */
@@ -2509,6 +2581,13 @@ int has_nhm_turbo_ratio_limit(unsigned int family, unsigned int model)
return 1;
}
}
+int has_atom_turbo_ratio_limit(unsigned int family, unsigned int model)
+{
+ if (has_slv_msrs(family, model))
+ return 1;
+
+ return 0;
+}
int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model)
{
if (!genuine_intel)
@@ -2606,6 +2685,9 @@ dump_cstate_pstate_config_info(unsigned int family, unsigned int model)
if (has_nhm_turbo_ratio_limit(family, model))
dump_nhm_turbo_ratio_limits();
+ if (has_atom_turbo_ratio_limit(family, model))
+ dump_atom_turbo_ratio_limits();
+
if (has_knl_turbo_ratio_limit(family, model))
dump_knl_turbo_ratio_limits();
@@ -3287,27 +3369,6 @@ int has_snb_msrs(unsigned int family, unsigned int model)
}
/*
- * SLV client has supporet for unique MSRs:
- *
- * MSR_CC6_DEMOTION_POLICY_CONFIG
- * MSR_MC6_DEMOTION_POLICY_CONFIG
- */
-
-int has_slv_msrs(unsigned int family, unsigned int model)
-{
- if (!genuine_intel)
- return 0;
-
- switch (model) {
- case INTEL_FAM6_ATOM_SILVERMONT1:
- case INTEL_FAM6_ATOM_MERRIFIELD:
- case INTEL_FAM6_ATOM_MOOREFIELD:
- return 1;
- }
- return 0;
-}
-
-/*
* HSW adds support for additional MSRs:
*
* MSR_PKG_C8_RESIDENCY 0x00000630
--
2.11.0.161.g6610af872
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