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| Started by | Jon Mason <jon.mason@broadcom.com> |
|---|---|
| First post | 2017-02-28 22:50 +0100 |
| Last post | 2017-03-02 20:20 +0100 |
| Articles | 3 — 2 participants |
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[PATCH 1/2] ARM: dts: bcm5301x: Add TWD WD Support to DT Jon Mason <jon.mason@broadcom.com> - 2017-02-28 22:50 +0100
Re: [PATCH 1/2] ARM: dts: bcm5301x: Add TWD WD Support to DT Rafał Miłecki <zajec5@gmail.com> - 2017-03-02 20:10 +0100
Re: [PATCH 1/2] ARM: dts: bcm5301x: Add TWD WD Support to DT Rafał Miłecki <zajec5@gmail.com> - 2017-03-02 20:20 +0100
| From | Jon Mason <jon.mason@broadcom.com> |
|---|---|
| Date | 2017-02-28 22:50 +0100 |
| Subject | [PATCH 1/2] ARM: dts: bcm5301x: Add TWD WD Support to DT |
| Message-ID | <tfWSB-11X-5@gated-at.bofh.it> |
From: Jon Mason <jonmason@broadcom.com>
Add support for the ARM TWD Watchdog to the bcm5301x device tree. The
ARM TWD timer allocated the register space for the WDT, so this patch
necessitated shrinking that. Also, the GIC masks were added for these.
Signed-off-by: Jon Mason <jonmason@broadcom.com>
---
arch/arm/boot/dts/bcm5301x.dtsi | 15 ++++++++++++---
1 file changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index 4fbb089..3fbc450 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -70,10 +70,19 @@
clocks = <&periph_clk>;
};
- local-timer@20600 {
+ timer@20600 {
compatible = "arm,cortex-a9-twd-timer";
- reg = <0x20600 0x100>;
- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x20600 0x20>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ clocks = <&periph_clk>;
+ };
+
+ watchdog@20620 {
+ compatible = "arm,cortex-a9-twd-wdt";
+ reg = <0x20620 0x20>;
+ interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&periph_clk>;
};
--
2.7.4
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| From | Rafał Miłecki <zajec5@gmail.com> |
|---|---|
| Date | 2017-03-02 20:10 +0100 |
| Message-ID | <tgEgV-6Ib-1@gated-at.bofh.it> |
| In reply to | #1589820 |
On 02/28/2017 09:31 PM, Jon Mason wrote:
> From: Jon Mason <jonmason@broadcom.com>
>
> Add support for the ARM TWD Watchdog to the bcm5301x device tree. The
> ARM TWD timer allocated the register space for the WDT, so this patch
> necessitated shrinking that. Also, the GIC masks were added for these.
>
> Signed-off-by: Jon Mason <jonmason@broadcom.com>
> ---
> arch/arm/boot/dts/bcm5301x.dtsi | 15 ++++++++++++---
> 1 file changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
> index 4fbb089..3fbc450 100644
> --- a/arch/arm/boot/dts/bcm5301x.dtsi
> +++ b/arch/arm/boot/dts/bcm5301x.dtsi
> @@ -70,10 +70,19 @@
> clocks = <&periph_clk>;
> };
>
> - local-timer@20600 {
> + timer@20600 {
> compatible = "arm,cortex-a9-twd-timer";
> - reg = <0x20600 0x100>;
> - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x20600 0x20>;
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
> + IRQ_TYPE_LEVEL_HIGH)>;
> + clocks = <&periph_clk>;
> + };
If you follow my recent e-mail thread:
BCM5301X: GIC: PPI11 is secure or misconfigured (same for PPI13)
you'll see IRQ_TYPE_LEVEL_HIGH type isn't correct. It should be
IRQ_TYPE_EDGE_RISING.
I believe patch switching to IRQ_TYPE_EDGE_RISING should be sent with Cc stable
for kernels 4.8+.
The same change is needed for "arm,cortex-a9-global-timer".
Would you find time to revise this patch?
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| From | Rafał Miłecki <zajec5@gmail.com> |
|---|---|
| Date | 2017-03-02 20:20 +0100 |
| Message-ID | <tgEqC-6Lz-3@gated-at.bofh.it> |
| In reply to | #1591399 |
On 2 March 2017 at 20:00, Jon Mason <jon.mason@broadcom.com> wrote:
> On Thu, Mar 2, 2017 at 1:54 PM, Rafał Miłecki <zajec5@gmail.com> wrote:
>>
>> On 02/28/2017 09:31 PM, Jon Mason wrote:
>>>
>>> From: Jon Mason <jonmason@broadcom.com>
>>>
>>> Add support for the ARM TWD Watchdog to the bcm5301x device tree. The
>>> ARM TWD timer allocated the register space for the WDT, so this patch
>>> necessitated shrinking that. Also, the GIC masks were added for these.
>>>
>>> Signed-off-by: Jon Mason <jonmason@broadcom.com>
>>> ---
>>> arch/arm/boot/dts/bcm5301x.dtsi | 15 ++++++++++++---
>>> 1 file changed, 12 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/bcm5301x.dtsi
>>> b/arch/arm/boot/dts/bcm5301x.dtsi
>>> index 4fbb089..3fbc450 100644
>>> --- a/arch/arm/boot/dts/bcm5301x.dtsi
>>> +++ b/arch/arm/boot/dts/bcm5301x.dtsi
>>> @@ -70,10 +70,19 @@
>>> clocks = <&periph_clk>;
>>> };
>>>
>>> - local-timer@20600 {
>>> + timer@20600 {
>>> compatible = "arm,cortex-a9-twd-timer";
>>> - reg = <0x20600 0x100>;
>>> - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
>>> + reg = <0x20600 0x20>;
>>> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2)
>>> |
>>> + IRQ_TYPE_LEVEL_HIGH)>;
>>> + clocks = <&periph_clk>;
>>> + };
>>
>>
>> If you follow my recent e-mail thread:
>> BCM5301X: GIC: PPI11 is secure or misconfigured (same for PPI13)
>> you'll see IRQ_TYPE_LEVEL_HIGH type isn't correct. It should be
>> IRQ_TYPE_EDGE_RISING.
>>
>> I believe patch switching to IRQ_TYPE_EDGE_RISING should be sent with Cc
>> stable
>> for kernels 4.8+.
>>
>> The same change is needed for "arm,cortex-a9-global-timer".
>>
>> Would you find time to revise this patch?
>
>
> I'll do 2 patches. One to revise this one and one to address the issue
> you've discovered. Will that be okay for you?
Sure. Please make sure you switch to IRQ_TYPE_EDGE_RISING before doing
other changes, so it can be applied cleanly to the stable kernels.
--
Rafał
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