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[PATCH v2 00/17] ARM: Initial Actions Semi S500 and S900 enablement

Started byAndreas Färber <afaerber@suse.de>
First post2017-02-24 04:50 +0100
Last post2017-02-25 01:00 +0100
Articles 6 on this page of 26 — 3 participants

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  [PATCH v2 00/17] ARM: Initial Actions Semi S500 and S900 enablement Andreas Färber <afaerber@suse.de> - 2017-02-24 04:50 +0100
    [PATCH v2 06/17] ARM64: Prepare Actions Semi S900 Andreas Färber <afaerber@suse.de> - 2017-02-24 04:50 +0100
    [PATCH v2 17/17] ARM: dts: s500-guitar-bb-rev-b: Add fake uart3 clock Andreas Färber <afaerber@suse.de> - 2017-02-24 04:50 +0100
    [PATCH v2 01/17] dt-bindings: Add vendor prefix for Actions Semi Andreas Färber <afaerber@suse.de> - 2017-02-24 04:50 +0100
      Re: [PATCH v2 01/17] dt-bindings: Add vendor prefix for Actions Semi Andreas Färber <afaerber@suse.de> - 2017-02-27 16:50 +0100
        Re: [PATCH v2 01/17] dt-bindings: Add vendor prefix for Actions Semi Rob Herring <robh@kernel.org> - 2017-02-28 01:50 +0100
    Re: [RFC v2 03/17] dt-bindings: timer: Document Owl timer Andreas Färber <afaerber@suse.de> - 2017-02-24 04:50 +0100
    [RFC v2 13/17] ARM64: dts: Add Actions Semi S900 and Bubblegum-96 Andreas Färber <afaerber@suse.de> - 2017-02-24 04:50 +0100
      Re: [RFC v2 13/17] ARM64: dts: Add Actions Semi S900 and Bubblegum-96 Andreas Färber <afaerber@suse.de> - 2017-02-24 05:00 +0100
    [PATCH v2 08/17] tty: serial: Add Actions Semi Owl UART earlycon Andreas Färber <afaerber@suse.de> - 2017-02-24 04:50 +0100
    [PATCH v2 09/17] Documentation: kernel-parameters: Document owl earlycon Andreas Färber <afaerber@suse.de> - 2017-02-24 04:50 +0100
    [PATCH v2 07/17] dt-bindings: serial: Document Actions Semi Owl UARTs Andreas Färber <afaerber@suse.de> - 2017-02-24 04:50 +0100
      Re: [PATCH v2 07/17] dt-bindings: serial: Document Actions Semi Owl  UARTs Rob Herring <robh@kernel.org> - 2017-02-28 01:20 +0100
    [RFC v2 03/17] dt-bindings: timer: Document Owl timer Andreas Färber <afaerber@suse.de> - 2017-02-24 04:50 +0100
      Re: [RFC v2 03/17] dt-bindings: timer: Document Owl timer Andreas Färber <afaerber@suse.de> - 2017-02-27 15:50 +0100
        Re: [RFC v2 03/17] dt-bindings: timer: Document Owl timer Rob Herring <robh@kernel.org> - 2017-02-28 01:20 +0100
    [PATCH v2 12/17] dt-bindings: arm: Document Actions Semi S900 Andreas Färber <afaerber@suse.de> - 2017-02-24 04:50 +0100
      Re: [PATCH v2 12/17] dt-bindings: arm: Document Actions Semi S900 Rob Herring <robh@kernel.org> - 2017-02-28 01:30 +0100
    [PATCH v2 04/17] clocksource: Add Owl timer Andreas Färber <afaerber@suse.de> - 2017-02-24 04:50 +0100
      Re: [PATCH v2 04/17] clocksource: Add Owl timer Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-02-24 23:30 +0100
        Re: [PATCH v2 04/17] clocksource: Add Owl timer Andreas Färber <afaerber@suse.de> - 2017-02-25 00:30 +0100
          Re: [PATCH v2 04/17] clocksource: Add Owl timer Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-02-25 23:00 +0100
            Re: [PATCH v2 04/17] clocksource: Add Owl timer Andreas Färber <afaerber@suse.de> - 2017-02-26 15:50 +0100
              Re: [PATCH v2 04/17] clocksource: Add Owl timer Daniel Lezcano <daniel.lezcano@linaro.org> - 2017-02-26 16:00 +0100
    [PATCH v2 10/17] ARM: dts: Add Actions Semi S500 and LeMaker Guitar Andreas Färber <afaerber@suse.de> - 2017-02-24 04:50 +0100
      Re: [PATCH v2 10/17] ARM: dts: Add Actions Semi S500 and LeMaker  Guitar Andreas Färber <afaerber@suse.de> - 2017-02-25 01:00 +0100

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#1588001 — Re: [PATCH v2 04/17] clocksource: Add Owl timer

FromAndreas Färber <afaerber@suse.de>
Date2017-02-25 00:30 +0100
SubjectRe: [PATCH v2 04/17] clocksource: Add Owl timer
Message-ID<textf-7sW-9@gated-at.bofh.it>
In reply to#1587982
Am 24.02.2017 um 23:29 schrieb Daniel Lezcano:
> On Fri, Feb 24, 2017 at 04:40:42AM +0100, Andreas Färber wrote:
>> Implement clocksource and clockevents for Actions Semi S500.
>>
>> Based on LeMaker linux-actions tree.
>>
>> Signed-off-by: Andreas Färber <afaerber@suse.de>
> 
> As this is a new driver, please give some technical information about the
> driver itself and a pointer to documentation if it is publicly available.

What technical information would that be? Which of the timers we use as
clock source vs. clock events?

The only public documentation beyond the source tree mentioned is here:

http://www.lemaker.org/product-guitar-download-29.html (section 3.4)

>> +#define OWL_Tx_CTL_INTEN	(1 << 1)
>> +#define OWL_Tx_CTL_EN		(1 << 2)
> 
> s/(1 << 1)/BIT(1)/
> s/(1 << 2)/BIT(2)/

OK

>> +
>> +static void __iomem *owl_timer_base;
>> +
>> +static u64 notrace owl_timer_sched_read(void)
>> +{
>> +	return (u64)readl(owl_timer_base + OWL_T0_VAL);
>> +}
>> +
>> +static int owl_timer_set_state_shutdown(struct clock_event_device *evt)
>> +{
>> +	writel(0, owl_timer_base + OWL_T1_CTL);
>> +
>> +	return 0;
>> +}
>> +
>> +static int owl_timer_set_state_oneshot(struct clock_event_device *evt)
>> +{
>> +	writel(0, owl_timer_base + OWL_T1_CTL);
>> +	writel(0, owl_timer_base + OWL_T1_VAL);
>> +	writel(0, owl_timer_base + OWL_T1_CMP);
>> +
>> +	return 0;
>> +}
>> +
>> +static int owl_timer_tick_resume(struct clock_event_device *evt)
>> +{
>> +	return 0;
>> +}
>> +
>> +static int owl_timer_set_next_event(unsigned long evt,
>> +				    struct clock_event_device *ev)
>> +{
>> +	writel(0, owl_timer_base + OWL_T1_CTL);
>> +
>> +	writel(0, owl_timer_base + OWL_T1_VAL);
>> +	writel(evt, owl_timer_base + OWL_T1_CMP);
>> +
>> +	writel(OWL_Tx_CTL_EN | OWL_Tx_CTL_INTEN, owl_timer_base + OWL_T1_CTL);
>> +
>> +	return 0;
>> +}
>> +
>> +static struct clock_event_device owl_clockevent = {
>> +	.name			= "owl_tick",
>> +	.rating			= 200,
>> +	.features		= CLOCK_EVT_FEAT_ONESHOT,
> 
> Did you consider adding CLOCK_EVT_FEAT_DYNIRQ ?

No, it was not present downstream. Got a good example?

>> +	.set_state_shutdown	= owl_timer_set_state_shutdown,
>> +	.set_state_oneshot	= owl_timer_set_state_oneshot,
>> +	.tick_resume		= owl_timer_tick_resume,
>> +	.set_next_event		= owl_timer_set_next_event,
>> +};
>> +
>> +static irqreturn_t owl_timer_interrupt(int irq, void *dev_id)
>> +{
>> +	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
>> +
>> +	evt->event_handler(evt);
>> +
>> +	return IRQ_HANDLED;
>> +}
>> +
>> +static struct irqaction owl_timer_irq = {
>> +	.name = "owl-timer",
>> +	.flags = IRQF_TIMER,
>> +	.handler = owl_timer_interrupt,
>> +	.dev_id = &owl_clockevent,
>> +};
>> +
>> +static int __init owl_timer_init(struct device_node *node)
>> +{
>> +	const unsigned long rate = 24000000;
> 
> Use DT, either use clock-frequency or a clock ref.

Are clk drivers really available at this point? clock-frequency sounds
more promising.

>> +	int irq1, ret;
>> +
>> +	owl_timer_base = of_io_request_and_map(node, 0, "owl-timer");
>> +	if (IS_ERR(owl_timer_base)) {
>> +		pr_err("Can't map timer registers");
>> +		return -ENXIO;
> 
> Why not PTR_ERR(owl_timer_base) ?

Only one in-tree driver (sun5i) matches such an expression. Will change.

>> +	}
>> +
>> +	irq1 = irq_of_parse_and_map(node, 1);
>> +	if (irq1 <= 0) {
>> +		pr_err("Can't parse timer1 IRQ");
>> +		return -EINVAL;
>> +	}
>> +
>> +	writel(0, owl_timer_base + OWL_T0_CTL);
>> +	writel(0, owl_timer_base + OWL_T0_VAL);
>> +	writel(0, owl_timer_base + OWL_T0_CMP);
>> +	writel(OWL_Tx_CTL_EN, owl_timer_base + OWL_T0_CTL);
> 
> Please factor out these calls into a function.

Do you have something in particular in mind? Maybe ..._reset() for the
first three?

>> +
>> +	sched_clock_register(owl_timer_sched_read, 32, rate);
>> +	clocksource_mmio_init(owl_timer_base + OWL_T0_VAL, node->name,
>> +			      rate, 200, 32, clocksource_mmio_readl_up);
>> +
>> +	writel(0, owl_timer_base + OWL_T1_CTL);
>> +	writel(0, owl_timer_base + OWL_T1_VAL);
>> +	writel(0, owl_timer_base + OWL_T1_CMP);
>> +
>> +	ret = setup_irq(irq1, &owl_timer_irq);
>> +	if (ret) {
>> +		pr_warn("failed to setup irq %d\n", irq1);
>> +		return ret;
>> +	}
> 
> s/setup_irq/request_irq/

Care to explain? setup_irq has 32 hits vs. 28 for request_irq.

>> +
>> +	owl_clockevent.cpumask = cpumask_of(0);
>> +	owl_clockevent.irq = irq1;
>> +
>> +	clockevents_config_and_register(&owl_clockevent, rate,
>> +					0xf, 0xffffffff);
>> +
>> +	return 0;
>> +}
>> +CLOCKSOURCE_OF_DECLARE(owl, "actions,owl-timer", owl_timer_init);

Do you spot anything functionally wrong in this driver? Despite adding
this new driver, I am only getting the following additional earlycon output:

[    0.000029] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps
every 89478484971ns
[    0.007888] clocksource: timer: mask: 0xffffffff max_cycles:
0xffffffff, max_idle_ns: 79635851949 ns
[    0.017748] Console: colour dummy device 80x30
[    0.022243] Calibrating delay loop...
[    0.030895] random: fast init done
[    0.231021] random: crng init done

For S900 I'm using the generic timer instead.

Thanks for your review,

Andreas

-- 
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)

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#1588239 — Re: [PATCH v2 04/17] clocksource: Add Owl timer

FromDaniel Lezcano <daniel.lezcano@linaro.org>
Date2017-02-25 23:00 +0100
SubjectRe: [PATCH v2 04/17] clocksource: Add Owl timer
Message-ID<teSxI-5tz-3@gated-at.bofh.it>
In reply to#1588001
On Sat, Feb 25, 2017 at 12:25:32AM +0100, Andreas Färber wrote:
> Am 24.02.2017 um 23:29 schrieb Daniel Lezcano:
> > On Fri, Feb 24, 2017 at 04:40:42AM +0100, Andreas Färber wrote:
> >> Implement clocksource and clockevents for Actions Semi S500.
> >>
> >> Based on LeMaker linux-actions tree.
> >>
> >> Signed-off-by: Andreas Färber <afaerber@suse.de>
> > 
> > As this is a new driver, please give some technical information about the
> > driver itself and a pointer to documentation if it is publicly available.
> 
> What technical information would that be? Which of the timers we use as
> clock source vs. clock events?

Have a look at commit 07862c1 and e4a6b37 as reference.
 
> The only public documentation beyond the source tree mentioned is here:
> 
> http://www.lemaker.org/product-guitar-download-29.html (section 3.4)
> 
> >> +#define OWL_Tx_CTL_INTEN	(1 << 1)
> >> +#define OWL_Tx_CTL_EN		(1 << 2)
> > 
> > s/(1 << 1)/BIT(1)/
> > s/(1 << 2)/BIT(2)/
> 
> OK
> 

[ ... ]

> >> +static struct clock_event_device owl_clockevent = {
> >> +	.name			= "owl_tick",
> >> +	.rating			= 200,
> >> +	.features		= CLOCK_EVT_FEAT_ONESHOT,
> > 
> > Did you consider adding CLOCK_EVT_FEAT_DYNIRQ ?
> 
> No, it was not present downstream. Got a good example?

https://lwn.net/Articles/541000/

> >> +	.set_state_shutdown	= owl_timer_set_state_shutdown,
> >> +	.set_state_oneshot	= owl_timer_set_state_oneshot,
> >> +	.tick_resume		= owl_timer_tick_resume,
> >> +	.set_next_event		= owl_timer_set_next_event,
> >> +};
> >> +
> >> +static irqreturn_t owl_timer_interrupt(int irq, void *dev_id)
> >> +{
> >> +	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
> >> +
> >> +	evt->event_handler(evt);
> >> +
> >> +	return IRQ_HANDLED;
> >> +}
> >> +
> >> +static struct irqaction owl_timer_irq = {
> >> +	.name = "owl-timer",
> >> +	.flags = IRQF_TIMER,
> >> +	.handler = owl_timer_interrupt,
> >> +	.dev_id = &owl_clockevent,
> >> +};
> >> +
> >> +static int __init owl_timer_init(struct device_node *node)
> >> +{
> >> +	const unsigned long rate = 24000000;
> > 
> > Use DT, either use clock-frequency or a clock ref.
> 
> Are clk drivers really available at this point? clock-frequency sounds
> more promising.

Yes they are. Have a look at the other drivers.
 
> >> +	int irq1, ret;
> >> +
> >> +	owl_timer_base = of_io_request_and_map(node, 0, "owl-timer");
> >> +	if (IS_ERR(owl_timer_base)) {
> >> +		pr_err("Can't map timer registers");
> >> +		return -ENXIO;
> > 
> > Why not PTR_ERR(owl_timer_base) ?
> 
> Only one in-tree driver (sun5i) matches such an expression. Will change.

[ ... ]

> > Please factor out these calls into a function.
> 
> Do you have something in particular in mind? Maybe ..._reset() for the
> first three?

Yes.

> >> +
> >> +	sched_clock_register(owl_timer_sched_read, 32, rate);
> >> +	clocksource_mmio_init(owl_timer_base + OWL_T0_VAL, node->name,
> >> +			      rate, 200, 32, clocksource_mmio_readl_up);
> >> +
> >> +	writel(0, owl_timer_base + OWL_T1_CTL);
> >> +	writel(0, owl_timer_base + OWL_T1_VAL);
> >> +	writel(0, owl_timer_base + OWL_T1_CMP);
> >> +
> >> +	ret = setup_irq(irq1, &owl_timer_irq);
> >> +	if (ret) {
> >> +		pr_warn("failed to setup irq %d\n", irq1);
> >> +		return ret;
> >> +	}
> > 
> > s/setup_irq/request_irq/
> 
> Care to explain? setup_irq has 32 hits vs. 28 for request_irq.

The function setup_irq takes an irqaction as parameter. That forces all the
drivers to declare a structure, so for a multiple platforms support (aka single
kernel image), there are multiple structures declaration for nothing. The
function request_irq allocates the structure and then call setup_irq.

So now, request_irq is used in place of setup_irq.

> >> +
> >> +	owl_clockevent.cpumask = cpumask_of(0);
> >> +	owl_clockevent.irq = irq1;
> >> +
> >> +	clockevents_config_and_register(&owl_clockevent, rate,
> >> +					0xf, 0xffffffff);
> >> +
> >> +	return 0;
> >> +}
> >> +CLOCKSOURCE_OF_DECLARE(owl, "actions,owl-timer", owl_timer_init);
> 
> Do you spot anything functionally wrong in this driver? Despite adding
> this new driver, I am only getting the following additional earlycon output:
>
> [    0.000029] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps
> every 89478484971ns
> [    0.007888] clocksource: timer: mask: 0xffffffff max_cycles:
> 0xffffffff, max_idle_ns: 79635851949 ns
> [    0.017748] Console: colour dummy device 80x30
> [    0.022243] Calibrating delay loop...
> [    0.030895] random: fast init done
> [    0.231021] random: crng init done
> 
> For S900 I'm using the generic timer instead.

I don't get the issue, can you elaborate ?

Thanks

  -- Daniel


-- 

 <http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs

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#1588332 — Re: [PATCH v2 04/17] clocksource: Add Owl timer

FromAndreas Färber <afaerber@suse.de>
Date2017-02-26 15:50 +0100
SubjectRe: [PATCH v2 04/17] clocksource: Add Owl timer
Message-ID<tf8j7-84j-1@gated-at.bofh.it>
In reply to#1588239
Am 25.02.2017 um 22:59 schrieb Daniel Lezcano:
> On Sat, Feb 25, 2017 at 12:25:32AM +0100, Andreas Färber wrote:
>> Am 24.02.2017 um 23:29 schrieb Daniel Lezcano:
>>> On Fri, Feb 24, 2017 at 04:40:42AM +0100, Andreas Färber wrote:
>>>> +static struct clock_event_device owl_clockevent = {
>>>> +	.name			= "owl_tick",
>>>> +	.rating			= 200,
>>>> +	.features		= CLOCK_EVT_FEAT_ONESHOT,
>>>
>>> Did you consider adding CLOCK_EVT_FEAT_DYNIRQ ?
>>
>> No, it was not present downstream. Got a good example?
> 
> https://lwn.net/Articles/541000/

Looking at your current Nomadik code, it seems I can literally should
just add this flag (done), without needing to implement any new hooks.

On a related topic, how do we determine the cpumask? Downstream and some
in-tree drivers use cpumask_of(0), others use cpu_possible_mask.

>> Do you spot anything functionally wrong in this driver? Despite adding
>> this new driver, I am only getting the following additional earlycon output:
>>
>> [    0.000029] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps
>> every 89478484971ns
>> [    0.007888] clocksource: timer: mask: 0xffffffff max_cycles:
>> 0xffffffff, max_idle_ns: 79635851949 ns
>> [    0.017748] Console: colour dummy device 80x30
>> [    0.022243] Calibrating delay loop...
>> [    0.030895] random: fast init done
>> [    0.231021] random: crng init done
>>
>> For S900 I'm using the generic timer instead.
> 
> I don't get the issue, can you elaborate ?

Found it myself: I forgot to clear the interrupt pending bit in the
interrupt handler routine.

+       writel(OWL_Tx_CTL_PD, owl_timer_base + OWL_T1_CTL);

Now it goes past this point, initializes the real serial driver and
boots up to not finding the rootfs:

[    0.000032] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps
every 89478484971ns
[    0.007898] clocksource: timer: mask: 0xffffffff max_cycles:
0xffffffff, max_idle_ns: 79635851949 ns
[    0.017886] Console: colour dummy device 80x30
[    0.022386] Calibrating delay loop... 405.50 BogoMIPS (lpj=2027520)
[    0.083523] pid_max: default: 32768 minimum: 301
...

Regards,
Andreas

-- 
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)

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#1588336 — Re: [PATCH v2 04/17] clocksource: Add Owl timer

FromDaniel Lezcano <daniel.lezcano@linaro.org>
Date2017-02-26 16:00 +0100
SubjectRe: [PATCH v2 04/17] clocksource: Add Owl timer
Message-ID<tf8sN-89F-9@gated-at.bofh.it>
In reply to#1588332
On Sun, Feb 26, 2017 at 03:40:49PM +0100, Andreas Färber wrote:
> Am 25.02.2017 um 22:59 schrieb Daniel Lezcano:
> > On Sat, Feb 25, 2017 at 12:25:32AM +0100, Andreas Färber wrote:
> >> Am 24.02.2017 um 23:29 schrieb Daniel Lezcano:
> >>> On Fri, Feb 24, 2017 at 04:40:42AM +0100, Andreas Färber wrote:
> >>>> +static struct clock_event_device owl_clockevent = {
> >>>> +	.name			= "owl_tick",
> >>>> +	.rating			= 200,
> >>>> +	.features		= CLOCK_EVT_FEAT_ONESHOT,
> >>>
> >>> Did you consider adding CLOCK_EVT_FEAT_DYNIRQ ?
> >>
> >> No, it was not present downstream. Got a good example?
> > 
> > https://lwn.net/Articles/541000/
> 
> Looking at your current Nomadik code, it seems I can literally should
> just add this flag (done), without needing to implement any new hooks.
> 
> On a related topic, how do we determine the cpumask? Downstream and some
> in-tree drivers use cpumask_of(0), others use cpu_possible_mask.

If you specify the CLOCK_EVT_FEAT_DYNIRQ, the cpumask is not important as it
will be changed dynamically.

Otherwise, cpumask_of(0) is often the default because it concentrates the
wakeup on a single cpu, allowing the other cpus to go to deep idle state and if
there are two clusters, it allows to have a cluster idle state. That results on
a better energy saving.

The usage of cpu_possible_mask will randomly wakeup any cpu.
 
> >> Do you spot anything functionally wrong in this driver? Despite adding
> >> this new driver, I am only getting the following additional earlycon output:
> >>
> >> [    0.000029] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps
> >> every 89478484971ns
> >> [    0.007888] clocksource: timer: mask: 0xffffffff max_cycles:
> >> 0xffffffff, max_idle_ns: 79635851949 ns
> >> [    0.017748] Console: colour dummy device 80x30
> >> [    0.022243] Calibrating delay loop...
> >> [    0.030895] random: fast init done
> >> [    0.231021] random: crng init done
> >>
> >> For S900 I'm using the generic timer instead.
> > 
> > I don't get the issue, can you elaborate ?
> 
> Found it myself: I forgot to clear the interrupt pending bit in the
> interrupt handler routine.
> 
> +       writel(OWL_Tx_CTL_PD, owl_timer_base + OWL_T1_CTL);
> 
> Now it goes past this point, initializes the real serial driver and
> boots up to not finding the rootfs:
> 
> [    0.000032] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps
> every 89478484971ns
> [    0.007898] clocksource: timer: mask: 0xffffffff max_cycles:
> 0xffffffff, max_idle_ns: 79635851949 ns
> [    0.017886] Console: colour dummy device 80x30
> [    0.022386] Calibrating delay loop... 405.50 BogoMIPS (lpj=2027520)

May be you should also consider using register_current_timer_delay() instead of
jiffies based delay loops.

> [    0.083523] pid_max: default: 32768 minimum: 301

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#1587273 — [PATCH v2 10/17] ARM: dts: Add Actions Semi S500 and LeMaker Guitar

FromAndreas Färber <afaerber@suse.de>
Date2017-02-24 04:50 +0100
Subject[PATCH v2 10/17] ARM: dts: Add Actions Semi S500 and LeMaker Guitar
Message-ID<tef3l-2Ja-43@gated-at.bofh.it>
In reply to#1587260
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
 v1 -> v2:
 * Reworded subject
 * Updated ARCH_OWL to ARCH_ACTIONS (Arnd)
 * Adopted "actions" vendor prefix
 * Dropped irq.h include
 * Added memory@0 node for Guitar SoM
 * Dropped bogus uart3 clock-frequency
 * Added device_type for CPU nodes
 * Fixed UART reg size
 * Adopted SPDX-License-Identifier (Rob)
 * Added remaining UART nodes
 * Added timer node
 
 arch/arm/boot/dts/Makefile                 |   2 +
 arch/arm/boot/dts/s500-guitar-bb-rev-b.dts |  26 ++++++
 arch/arm/boot/dts/s500-guitar.dtsi         |  20 +++++
 arch/arm/boot/dts/s500.dtsi                | 135 +++++++++++++++++++++++++++++
 4 files changed, 183 insertions(+)
 create mode 100644 arch/arm/boot/dts/s500-guitar-bb-rev-b.dts
 create mode 100644 arch/arm/boot/dts/s500-guitar.dtsi
 create mode 100644 arch/arm/boot/dts/s500.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 0118084..578a20b 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -638,6 +638,8 @@ dtb-$(CONFIG_ARCH_ORION5X) += \
 	orion5x-maxtor-shared-storage-2.dtb \
 	orion5x-netgear-wnr854t.dtb \
 	orion5x-rd88f5182-nas.dtb
+dtb-$(CONFIG_ARCH_ACTIONS) += \
+	s500-guitar-bb-rev-b.dtb
 dtb-$(CONFIG_ARCH_PRIMA2) += \
 	prima2-evb.dtb
 dtb-$(CONFIG_ARCH_OXNAS) += \
diff --git a/arch/arm/boot/dts/s500-guitar-bb-rev-b.dts b/arch/arm/boot/dts/s500-guitar-bb-rev-b.dts
new file mode 100644
index 0000000..834b71d
--- /dev/null
+++ b/arch/arm/boot/dts/s500-guitar-bb-rev-b.dts
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2016-2017 Andreas Färber
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+/dts-v1/;
+
+#include "s500-guitar.dtsi"
+
+/ {
+	compatible = "lemaker,guitar-bb-rev-b", "lemaker,guitar", "actions,s500";
+	model = "LeMaker Guitar Base Board rev. B";
+
+	aliases {
+		serial3 = &uart3;
+	};
+
+	chosen {
+		stdout-path = "serial3:115200n8";
+	};
+};
+
+&uart3 {
+	status = "okay";
+};
diff --git a/arch/arm/boot/dts/s500-guitar.dtsi b/arch/arm/boot/dts/s500-guitar.dtsi
new file mode 100644
index 0000000..ef0e7e3
--- /dev/null
+++ b/arch/arm/boot/dts/s500-guitar.dtsi
@@ -0,0 +1,20 @@
+/*
+ * LeMaker Guitar SoM
+ *
+ * Copyright (c) 2016-2017 Andreas Färber
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#include "s500.dtsi"
+
+/ {
+	compatible = "lemaker,guitar", "actions,s500";
+
+	/delete-node/ memory;
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x40000000>;
+	};
+};
diff --git a/arch/arm/boot/dts/s500.dtsi b/arch/arm/boot/dts/s500.dtsi
new file mode 100644
index 0000000..149bb7a
--- /dev/null
+++ b/arch/arm/boot/dts/s500.dtsi
@@ -0,0 +1,135 @@
+/*
+ * Actions Semi S500 SoC
+ *
+ * Copyright (c) 2016-2017 Andreas Färber
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#include "skeleton.dtsi"
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "actions,s500";
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <0x0>;
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <0x1>;
+		};
+
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <0x2>;
+		};
+
+		cpu3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <0x3>;
+		};
+	};
+
+	arm-pmu {
+		compatible = "arm,cortex-a9-pmu";
+		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+		             <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+		             <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+		             <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		gic: interrupt-controller@b0021000 {
+			compatible = "arm,cortex-a9-gic";
+			reg = <0xb0021000 0x1000>,
+			      <0xb0020100 0x0100>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+		};
+
+		l2: cache-controller@b0022000 {
+			compatible = "arm,pl310-cache";
+			reg = <0xb0022000 0x1000>;
+			cache-unified;
+			cache-level = <2>;
+			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+			arm,tag-latency = <3 3 2>;
+			arm,data-latency = <5 3 3>;
+		};
+
+		uart0: serial@b0120000 {
+			compatible = "actions,s500-uart", "actions,owl-uart";
+			reg = <0xb0120000 0x2000>;
+			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart1: serial@b0122000 {
+			compatible = "actions,s500-uart", "actions,owl-uart";
+			reg = <0xb0122000 0x2000>;
+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart2: serial@b0124000 {
+			compatible = "actions,s500-uart", "actions,owl-uart";
+			reg = <0xb0126000 0x2000>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart3: serial@b0126000 {
+			compatible = "actions,s500-uart", "actions,owl-uart";
+			reg = <0xb0126000 0x2000>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart4: serial@b0128000 {
+			compatible = "actions,s500-uart", "actions,owl-uart";
+			reg = <0xb0128000 0x2000>;
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart5: serial@b012a000 {
+			compatible = "actions,s500-uart", "actions,owl-uart";
+			reg = <0xb012a000 0x2000>;
+			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart6: serial@b012c000 {
+			compatible = "actions,s500-uart", "actions,owl-uart";
+			reg = <0xb012c000 0x2000>;
+			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		timer@b0168000 {
+			compatible = "actions,owl-timer";
+			reg = <0xb0168000 0x100>;
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+			             <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+		};
+	};
+};
-- 
2.10.2

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#1588009 — Re: [PATCH v2 10/17] ARM: dts: Add Actions Semi S500 and LeMaker Guitar

FromAndreas Färber <afaerber@suse.de>
Date2017-02-25 01:00 +0100
SubjectRe: [PATCH v2 10/17] ARM: dts: Add Actions Semi S500 and LeMaker Guitar
Message-ID<texWi-7Hd-1@gated-at.bofh.it>
In reply to#1587273
Am 24.02.2017 um 04:40 schrieb Andreas Färber:
> +		uart2: serial@b0124000 {
> +			compatible = "actions,s500-uart", "actions,owl-uart";
> +			reg = <0xb0126000 0x2000>;

Wrong reg offset.

> +			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> +			status = "disabled";
> +		};
> +
> +		uart3: serial@b0126000 {
> +			compatible = "actions,s500-uart", "actions,owl-uart";
> +			reg = <0xb0126000 0x2000>;
> +			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> +			status = "disabled";
> +		};

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