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[PATCH 3/7] clk: tegra: correct afi parent

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  [PATCH 3/7] clk: tegra: correct afi parent Peter De Schrijver <pdeschrijver@nvidia.com> - 2017-02-22 16:20 +0100
    Re: [PATCH 3/7] clk: tegra: correct afi parent Mikko Perttunen <cyndis@kapsi.fi> - 2017-02-23 10:10 +0100

#1586259 — [PATCH 3/7] clk: tegra: correct afi parent

The parent for afi is actually mselect, not clk_m.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
 drivers/clk/tegra/clk-tegra-periph.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index 19b00b7..c9e795b 100644
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -815,7 +815,7 @@
 	GATE("usb2", "clk_m", 58, 0, tegra_clk_usb2, 0),
 	GATE("usb3", "clk_m", 59, 0, tegra_clk_usb3, 0),
 	GATE("csi", "pll_p_out3", 52, 0, tegra_clk_csi, 0),
-	GATE("afi", "clk_m", 72, 0, tegra_clk_afi, 0),
+	GATE("afi", "mselect", 72, 0, tegra_clk_afi, 0),
 	GATE("csus", "clk_m", 92, TEGRA_PERIPH_NO_RESET, tegra_clk_csus, 0),
 	GATE("dds", "clk_m", 150, TEGRA_PERIPH_ON_APB, tegra_clk_dds, 0),
 	GATE("dp2", "clk_m", 152, TEGRA_PERIPH_ON_APB, tegra_clk_dp2, 0),
-- 
1.9.1

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#1586758

Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>

On 22.02.2017 17:13, Peter De Schrijver wrote:
> The parent for afi is actually mselect, not clk_m.
>
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> ---
>  drivers/clk/tegra/clk-tegra-periph.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
> index 19b00b7..c9e795b 100644
> --- a/drivers/clk/tegra/clk-tegra-periph.c
> +++ b/drivers/clk/tegra/clk-tegra-periph.c
> @@ -815,7 +815,7 @@
>  	GATE("usb2", "clk_m", 58, 0, tegra_clk_usb2, 0),
>  	GATE("usb3", "clk_m", 59, 0, tegra_clk_usb3, 0),
>  	GATE("csi", "pll_p_out3", 52, 0, tegra_clk_csi, 0),
> -	GATE("afi", "clk_m", 72, 0, tegra_clk_afi, 0),
> +	GATE("afi", "mselect", 72, 0, tegra_clk_afi, 0),
>  	GATE("csus", "clk_m", 92, TEGRA_PERIPH_NO_RESET, tegra_clk_csus, 0),
>  	GATE("dds", "clk_m", 150, TEGRA_PERIPH_ON_APB, tegra_clk_dds, 0),
>  	GATE("dp2", "clk_m", 152, TEGRA_PERIPH_ON_APB, tegra_clk_dp2, 0),
>

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