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[PATCH v2 0/8] ARM64: Initial Marvell IAP140 enablement

Started byAndreas Färber <afaerber@suse.de>
First post2017-02-22 03:40 +0100
Last post2017-02-22 20:30 +0100
Articles 5 — 2 participants

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  [PATCH v2 0/8] ARM64: Initial Marvell IAP140 enablement Andreas Färber <afaerber@suse.de> - 2017-02-22 03:40 +0100
    Re: [PATCH v2 0/8] ARM64: Initial Marvell IAP140 enablement Rob Herring <robh@kernel.org> - 2017-02-22 14:40 +0100
      Re: [PATCH v2 0/8] ARM64: Initial Marvell IAP140 enablement Andreas Färber <afaerber@suse.de> - 2017-02-22 17:50 +0100
        Re: [PATCH v2 0/8] ARM64: Initial Marvell IAP140 enablement Andreas Färber <afaerber@suse.de> - 2017-02-22 17:50 +0100
        Re: [PATCH v2 0/8] ARM64: Initial Marvell IAP140 enablement Rob Herring <robh@kernel.org> - 2017-02-22 20:30 +0100

#1585888 — [PATCH v2 0/8] ARM64: Initial Marvell IAP140 enablement

FromAndreas Färber <afaerber@suse.de>
Date2017-02-22 03:40 +0100
Subject[PATCH v2 0/8] ARM64: Initial Marvell IAP140 enablement
Message-ID<tdv0u-2Z7-7@gated-at.bofh.it>
Hello,

This series adds initial support for the Marvell IAP140 SoC (aka PXA1908)
and the Andromeda Box Edge development board.

v2 reuses ARCH_MMP.

Both earlycon and serial are working, but an explicit console=ttyS0,115200n8
is needed; with just "earlycon" and stdout-path the earlycon stops early and
switches to a tty0, long before disabling the bootconsole...

All four CPUs come up, and an initrd can be reached.

However, there are errors about CPUs 1-3 having a zero SYS_CNTFRQ_EL0:

[    0.095812] smp: Bringing up secondary CPUs ...
======pxa1908_pmu_core_pwr_on: mpidr = 0x1
======pxa1908_pmu_core_pwr_on: mpidr = 0x2
======pxa1908_pmu_core_pwr_on: mpidr = 0x3
[    0.133419] Detected VIPT I-cache on CPU1
[    0.133430] CPU features: SANITY CHECK: Unexpected variation in SYS_CNTFRQ_EL0. Boot CPU: 0x000000018cba80, CPU1: 0x00000000000000
[    0.133447] Unsupported CPU feature variation.
...
[    0.133748] CPU1: Booted secondary processor [410fd032]
[    0.165465] Detected VIPT I-cache on CPU2
[    0.165474] CPU features: SANITY CHECK: Unexpected variation in SYS_CNTFRQ_EL0. Boot CPU: 0x000000018cba80, CPU2: 0x00000000000000
[    0.165505] CPU2: Booted secondary processor [410fd032]
[    0.197539] Detected VIPT I-cache on CPU3
[    0.197546] CPU features: SANITY CHECK: Unexpected variation in SYS_CNTFRQ_EL0. Boot CPU: 0x000000018cba80, CPU3: 0x00000000000000
[    0.197573] CPU3: Booted secondary processor [410fd032]
[    0.197625] smp: Brought up 1 node, 4 CPUs
[    0.522514] SMP: Total of 4 processors activated.
[    0.527212] CPU features: detected feature: 32-bit EL0 Support
[    0.533105] CPU: All CPU(s) started at EL2

KVM appears to initialize okay, but was not yet tested with guests.

[    0.865255] kvm [1]: 8-bit VMID
[    0.868401] kvm [1]: IDMAP page: d23000
[    0.872233] kvm [1]: HYP VA range: 800000000000:ffffffffffff
[    0.878262] kvm [1]: Hyp mode initialized successfully
[    0.883429] kvm [1]: vgic-v2@d1dfc000
[    0.887179] kvm [1]: vgic interrupt IRQ1
[    0.891120] kvm [1]: virtual timer IRQ4

One limitation is currently the lack of an IAP140 clk driver. Patch 4/4 works
around that for UART0 with a fixed-clock.

A 3.14 based tree is available on GitHub acorn-marvell/brillo_pxa_kernel.

Booting required changes to the vendor U-Boot,
cf. https://en.opensuse.org/HCL:AndromedaBoxEdge

https://github.com/afaerber/linux/commits/edge-next

Have a lot of fun!

Cheers,
Andreas

v1 -> v2:
* Add non-DT documentation
* Use ARCH_MMP instead of ARCH_PXA
* Split off Kconfig cleanups per subsystem
* Drop "mrvl,pxa-uart" and instead implement mmp earlycon
* Add some more DT nodes

Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Gregory Clement <gregory.clement@free-electrons.com>
Cc: info@andromedabox.org
Cc: devicetree@vger.kernel.org

Andreas Färber (8):
  Documentation: arm: Marvell: Document IAP140
  tty: serial: Suppress deprecated SERIAL_PXA on arm64
  tty: serial: 8250_pxa: Implement mmp earlycon
  sound: soc: pxa: Suppress SND_MMP_SOC for arm64
  ARM64: Prepare Marvell IAP140 aka PXA1908
  Documentation: devicetree: arm: marvell: Document IAP140
  ARM64: dts: marvell: Add IAP140 and Andromeda Box Edge
  ARM64: dts: marvell: iap140-andromeda-box-edge: Add uart0 clock

 Documentation/arm/Marvell/README                   |  12 +-
 .../devicetree/bindings/arm/marvell/iap140.txt     |  11 +
 arch/arm64/Kconfig.platforms                       |   7 +
 arch/arm64/boot/dts/marvell/Makefile               |   3 +
 .../boot/dts/marvell/iap140-andromeda-box-edge.dts |  87 ++++++++
 arch/arm64/boot/dts/marvell/iap140.dtsi            | 241 +++++++++++++++++++++
 drivers/tty/serial/8250/8250_pxa.c                 |   1 +
 drivers/tty/serial/Kconfig                         |   2 +-
 sound/soc/pxa/Kconfig                              |   4 +-
 9 files changed, 364 insertions(+), 4 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/marvell/iap140.txt
 create mode 100644 arch/arm64/boot/dts/marvell/iap140-andromeda-box-edge.dts
 create mode 100644 arch/arm64/boot/dts/marvell/iap140.dtsi

-- 
2.10.2

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#1586147

FromRob Herring <robh@kernel.org>
Date2017-02-22 14:40 +0100
Message-ID<tdFjb-2kS-3@gated-at.bofh.it>
In reply to#1585888
On Tue, Feb 21, 2017 at 8:29 PM, Andreas Färber <afaerber@suse.de> wrote:
> Hello,
>
> This series adds initial support for the Marvell IAP140 SoC (aka PXA1908)
> and the Andromeda Box Edge development board.
>
> v2 reuses ARCH_MMP.
>
> Both earlycon and serial are working, but an explicit console=ttyS0,115200n8
> is needed; with just "earlycon" and stdout-path the earlycon stops early and
> switches to a tty0, long before disabling the bootconsole...
>
> All four CPUs come up, and an initrd can be reached.
>
> However, there are errors about CPUs 1-3 having a zero SYS_CNTFRQ_EL0:
>
> [    0.095812] smp: Bringing up secondary CPUs ...
> ======pxa1908_pmu_core_pwr_on: mpidr = 0x1
> ======pxa1908_pmu_core_pwr_on: mpidr = 0x2
> ======pxa1908_pmu_core_pwr_on: mpidr = 0x3
> [    0.133419] Detected VIPT I-cache on CPU1
> [    0.133430] CPU features: SANITY CHECK: Unexpected variation in SYS_CNTFRQ_EL0. Boot CPU: 0x000000018cba80, CPU1: 0x00000000000000
> [    0.133447] Unsupported CPU feature variation.
> ...
> [    0.133748] CPU1: Booted secondary processor [410fd032]
> [    0.165465] Detected VIPT I-cache on CPU2
> [    0.165474] CPU features: SANITY CHECK: Unexpected variation in SYS_CNTFRQ_EL0. Boot CPU: 0x000000018cba80, CPU2: 0x00000000000000
> [    0.165505] CPU2: Booted secondary processor [410fd032]
> [    0.197539] Detected VIPT I-cache on CPU3
> [    0.197546] CPU features: SANITY CHECK: Unexpected variation in SYS_CNTFRQ_EL0. Boot CPU: 0x000000018cba80, CPU3: 0x00000000000000
> [    0.197573] CPU3: Booted secondary processor [410fd032]
> [    0.197625] smp: Brought up 1 node, 4 CPUs
> [    0.522514] SMP: Total of 4 processors activated.
> [    0.527212] CPU features: detected feature: 32-bit EL0 Support
> [    0.533105] CPU: All CPU(s) started at EL2
>
> KVM appears to initialize okay, but was not yet tested with guests.
>
> [    0.865255] kvm [1]: 8-bit VMID
> [    0.868401] kvm [1]: IDMAP page: d23000
> [    0.872233] kvm [1]: HYP VA range: 800000000000:ffffffffffff
> [    0.878262] kvm [1]: Hyp mode initialized successfully
> [    0.883429] kvm [1]: vgic-v2@d1dfc000
> [    0.887179] kvm [1]: vgic interrupt IRQ1
> [    0.891120] kvm [1]: virtual timer IRQ4
>
> One limitation is currently the lack of an IAP140 clk driver. Patch 4/4 works
> around that for UART0 with a fixed-clock.

The PXA1928 clock driver should be close to what you need. They are
supposed to be very similar.

> A 3.14 based tree is available on GitHub acorn-marvell/brillo_pxa_kernel.
>
> Booting required changes to the vendor U-Boot,
> cf. https://en.opensuse.org/HCL:AndromedaBoxEdge
>
> https://github.com/afaerber/linux/commits/edge-next
>
> Have a lot of fun!
>
> Cheers,
> Andreas
>
> v1 -> v2:
> * Add non-DT documentation
> * Use ARCH_MMP instead of ARCH_PXA
> * Split off Kconfig cleanups per subsystem
> * Drop "mrvl,pxa-uart" and instead implement mmp earlycon
> * Add some more DT nodes
>
> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: Gregory Clement <gregory.clement@free-electrons.com>
> Cc: info@andromedabox.org
> Cc: devicetree@vger.kernel.org
>
> Andreas Färber (8):
>   Documentation: arm: Marvell: Document IAP140
>   tty: serial: Suppress deprecated SERIAL_PXA on arm64
>   tty: serial: 8250_pxa: Implement mmp earlycon

You should not use the pxa serial driver. AFAICT, it was separate to
add DMA support, but now the base 8250 driver supports DMA. The base
8250 driver works with the PXA1928 and should also work with the
PXA1908.

>   sound: soc: pxa: Suppress SND_MMP_SOC for arm64
>   ARM64: Prepare Marvell IAP140 aka PXA1908
>   Documentation: devicetree: arm: marvell: Document IAP140
>   ARM64: dts: marvell: Add IAP140 and Andromeda Box Edge
>   ARM64: dts: marvell: iap140-andromeda-box-edge: Add uart0 clock
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

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#1586306

FromAndreas Färber <afaerber@suse.de>
Date2017-02-22 17:50 +0100
Message-ID<tdIh3-4BG-1@gated-at.bofh.it>
In reply to#1586147
Hi Rob,

Am 22.02.2017 um 14:34 schrieb Rob Herring:
> On Tue, Feb 21, 2017 at 8:29 PM, Andreas Färber <afaerber@suse.de> wrote:
>> One limitation is currently the lack of an IAP140 clk driver. Patch 4/4 works
>> around that for UART0 with a fixed-clock.
> 
> The PXA1928 clock driver should be close to what you need. They are
> supposed to be very similar.

Where do you see that in mainline? Not in drivers/clk/pxa/ at least. I'm
certain the acorn-marvell tree has a PXA1908 clk driver somewhere, too,
I just haven't ported it yet.

>> Andreas Färber (8):
>>   Documentation: arm: Marvell: Document IAP140
>>   tty: serial: Suppress deprecated SERIAL_PXA on arm64
>>   tty: serial: 8250_pxa: Implement mmp earlycon
> 
> You should not use the pxa serial driver. AFAICT, it was separate to
> add DMA support, but now the base 8250 driver supports DMA. The base
> 8250 driver works with the PXA1928 and should also work with the
> PXA1908.

Do you personally have one? I didn't spot a pxa1928 DT in mainline.

So, by my reading both 8250_of.c and 8250_pxa.c list "mrvl,mmp-uart" for
the platform driver. Is that really intentional?

What the early_pxa earlycon does is set the register shift and then
reuse the 8250 core - that looks perfectly valid to me. Are you possibly
mixing that up with the non-8250 pxa serial driver that I am already
suppressing one patch earlier?

While at it, are you aware that we have two drivers, one pxa and one
mmp, that bind to "marvell,pdma-1.0"? That seemed wrong to me, too.

Regards,
Andreas

-- 
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)

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#1586313

FromAndreas Färber <afaerber@suse.de>
Date2017-02-22 17:50 +0100
Message-ID<tdIh5-4BG-31@gated-at.bofh.it>
In reply to#1586306
Am 22.02.2017 um 17:43 schrieb Andreas Färber:
> Hi Rob,
> 
> Am 22.02.2017 um 14:34 schrieb Rob Herring:
>> On Tue, Feb 21, 2017 at 8:29 PM, Andreas Färber <afaerber@suse.de> wrote:
>>> One limitation is currently the lack of an IAP140 clk driver. Patch 4/4 works
>>> around that for UART0 with a fixed-clock.
>>
>> The PXA1928 clock driver should be close to what you need. They are
>> supposed to be very similar.
> 
> Where do you see that in mainline? Not in drivers/clk/pxa/ at least. I'm
> certain the acorn-marvell tree has a PXA1908 clk driver somewhere, too,
> I just haven't ported it yet.
> 
>>> Andreas Färber (8):
>>>   Documentation: arm: Marvell: Document IAP140
>>>   tty: serial: Suppress deprecated SERIAL_PXA on arm64
>>>   tty: serial: 8250_pxa: Implement mmp earlycon
>>
>> You should not use the pxa serial driver. AFAICT, it was separate to
>> add DMA support, but now the base 8250 driver supports DMA. The base
>> 8250 driver works with the PXA1928 and should also work with the
>> PXA1908.
> 
> Do you personally have one? I didn't spot a pxa1928 DT in mainline.
> 
> So, by my reading both 8250_of.c and 8250_pxa.c list "mrvl,mmp-uart" for
> the platform driver. Is that really intentional?
> 
> What the early_pxa earlycon does is set the register shift and then
> reuse the 8250 core - that looks perfectly valid to me. Are you possibly
> mixing that up with the non-8250 pxa serial driver that I am already
> suppressing one patch earlier?

Hit send too early: There's also 8250_early.c, but that does not appear
to use the reg-shift property (which is not mentioned in the
mrvl,mmp-uart binding) and thus omap has a custom earlycon driver there,
similar to what is in 8250_pxa.c.

> 
> While at it, are you aware that we have two drivers, one pxa and one
> mmp, that bind to "marvell,pdma-1.0"? That seemed wrong to me, too.
> 
> Regards,
> Andreas
> 


-- 
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)

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#1586431

FromRob Herring <robh@kernel.org>
Date2017-02-22 20:30 +0100
Message-ID<tdKLU-6vw-7@gated-at.bofh.it>
In reply to#1586306
On Wed, Feb 22, 2017 at 10:43 AM, Andreas Färber <afaerber@suse.de> wrote:
> Hi Rob,
>
> Am 22.02.2017 um 14:34 schrieb Rob Herring:
>> On Tue, Feb 21, 2017 at 8:29 PM, Andreas Färber <afaerber@suse.de> wrote:
>>> One limitation is currently the lack of an IAP140 clk driver. Patch 4/4 works
>>> around that for UART0 with a fixed-clock.
>>
>> The PXA1928 clock driver should be close to what you need. They are
>> supposed to be very similar.
>
> Where do you see that in mainline? Not in drivers/clk/pxa/ at least. I'm
> certain the acorn-marvell tree has a PXA1908 clk driver somewhere, too,
> I just haven't ported it yet.

drivers/clk/mmp/clk-of-pxa1928.c

I ported/rewrote that from Marvell's 3.10 vendor tree.

>>> Andreas Färber (8):
>>>   Documentation: arm: Marvell: Document IAP140
>>>   tty: serial: Suppress deprecated SERIAL_PXA on arm64
>>>   tty: serial: 8250_pxa: Implement mmp earlycon
>>
>> You should not use the pxa serial driver. AFAICT, it was separate to
>> add DMA support, but now the base 8250 driver supports DMA. The base
>> 8250 driver works with the PXA1928 and should also work with the
>> PXA1908.
>
> Do you personally have one? I didn't spot a pxa1928 DT in mainline.

Yes. It never got released and got abandoned. I got several drivers
cleaned up to support it and the clock code in before that happened. I
had a in-progress DRM driver too. I was debugging why some monitors
worked and others didn't when I stopped working on it. I think the
board you are working on has the same ADV7533?

It's all up on my Linaro tree:
https://git.linaro.org/people/rob.herring/linux.git

> So, by my reading both 8250_of.c and 8250_pxa.c list "mrvl,mmp-uart" for
> the platform driver. Is that really intentional?

Humm, well I added support in commit 6ad991b699b4e to of_serial.c and
then it looks like it got copied to 8250_pxa.c recently. Not sure if
that really made sense or not. We should remove one of them.
8250_pxa.c looks fairly pointless to me. Turning a clock on/off in
resume/suspend is already supported by 8250_of.c (which doesn't have
the bug of turning off the console's clock in suspend). The only other
thing is the errata in serial_pxa_dl_write.

> What the early_pxa earlycon does is set the register shift and then
> reuse the 8250 core - that looks perfectly valid to me. Are you possibly
> mixing that up with the non-8250 pxa serial driver that I am already
> suppressing one patch earlier?

The earlycon core already sets up reg-shift for you.

I added earlycon support in commit a4c639b04f301d. I used "ns16650a"
as a fallback compatible string, so there's not an explicit PXA/MMP
compatible string there.

> While at it, are you aware that we have two drivers, one pxa and one
> mmp, that bind to "marvell,pdma-1.0"? That seemed wrong to me, too.

Yeah, it was drivers/tty/serial/pxa.c that I was thinking of. I was
incorrectly thinking 8250_pxa.c was that one.

Rob

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