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| Started by | Pavel Machek <pavel@ucw.cz> |
|---|---|
| First post | 2017-02-14 14:50 +0100 |
| Last post | 2017-02-15 12:50 +0100 |
| Articles | 7 — 4 participants |
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[RFC 08/13] smiapp-pll: Take existing divisor into account in minimum divisor check Pavel Machek <pavel@ucw.cz> - 2017-02-14 14:50 +0100
Re: [RFC 08/13] smiapp-pll: Take existing divisor into account in minimum divisor check Sakari Ailus <sakari.ailus@iki.fi> - 2017-02-14 23:10 +0100
Re: [RFC 08/13] smiapp-pll: Take existing divisor into account in minimum divisor check Laurent Pinchart <laurent.pinchart@ideasonboard.com> - 2017-02-14 23:20 +0100
Re: [RFC 08/13] smiapp-pll: Take existing divisor into account in minimum divisor check Pavel Machek <pavel@ucw.cz> - 2017-02-15 12:30 +0100
Re: [RFC 08/13] smiapp-pll: Take existing divisor into account in minimum divisor check Pavel Machek <pavel@ucw.cz> - 2017-02-28 15:10 +0100
Re: [RFC 08/13] smiapp-pll: Take existing divisor into account in minimum divisor check Sakari Ailus <sakari.ailus@iki.fi> - 2017-02-28 15:30 +0100
Re: [RFC 08/13] smiapp-pll: Take existing divisor into account in minimum divisor check Pali Rohár <pali.rohar@gmail.com> - 2017-02-15 12:50 +0100
| From | Pavel Machek <pavel@ucw.cz> |
|---|---|
| Date | 2017-02-14 14:50 +0100 |
| Subject | [RFC 08/13] smiapp-pll: Take existing divisor into account in minimum divisor check |
| Message-ID | <taLEu-2wc-11@gated-at.bofh.it> |
[Multipart message — attachments visible in raw view] — view raw
From: Sakari Ailus <sakari.ailus@iki.fi>
Required added multiplier (and divisor) calculation did not take into
account the existing divisor when checking the values against the
minimum divisor. Do just that.
Signed-off-by: Sakari Ailus <sakari.ailus@iki.fi>
Signed-off-by: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com>
Signed-off-by: Pavel Machek <pavel@ucw.cz>
---
drivers/media/i2c/smiapp-pll.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/media/i2c/smiapp-pll.c b/drivers/media/i2c/smiapp-pll.c
index 771db56..166bbaf 100644
--- a/drivers/media/i2c/smiapp-pll.c
+++ b/drivers/media/i2c/smiapp-pll.c
@@ -16,6 +16,8 @@
* General Public License for more details.
*/
+#define DEBUG
+
#include <linux/device.h>
#include <linux/gcd.h>
#include <linux/lcm.h>
@@ -227,7 +229,8 @@ static int __smiapp_pll_calculate(
more_mul_factor = lcm(div, pll->pre_pll_clk_div) / div;
dev_dbg(dev, "more_mul_factor: %u\n", more_mul_factor);
- more_mul_factor = lcm(more_mul_factor, op_limits->min_sys_clk_div);
+ more_mul_factor = lcm(more_mul_factor,
+ DIV_ROUND_UP(op_limits->min_sys_clk_div, div));
dev_dbg(dev, "more_mul_factor: min_op_sys_clk_div: %d\n",
more_mul_factor);
i = roundup(more_mul_min, more_mul_factor);
@@ -456,6 +459,10 @@ int smiapp_pll_calculate(struct device *dev,
i = gcd(pll->pll_op_clk_freq_hz, pll->ext_clk_freq_hz);
mul = div_u64(pll->pll_op_clk_freq_hz, i);
div = pll->ext_clk_freq_hz / i;
+ if (!mul) {
+ dev_err(dev, "forcing mul to 1\n");
+ mul = 1;
+ }
dev_dbg(dev, "mul %u / div %u\n", mul, div);
min_pre_pll_clk_div =
--
2.1.4
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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| From | Sakari Ailus <sakari.ailus@iki.fi> |
|---|---|
| Date | 2017-02-14 23:10 +0100 |
| Message-ID | <taTsl-7x0-11@gated-at.bofh.it> |
| In reply to | #1580544 |
Hi Pavel, On Tue, Feb 14, 2017 at 02:40:04PM +0100, Pavel Machek wrote: > From: Sakari Ailus <sakari.ailus@iki.fi> > > Required added multiplier (and divisor) calculation did not take into > account the existing divisor when checking the values against the > minimum divisor. Do just that. > > Signed-off-by: Sakari Ailus <sakari.ailus@iki.fi> > Signed-off-by: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com> > Signed-off-by: Pavel Machek <pavel@ucw.cz> I need to understand again why did I write this patch. :-) Could you send me the smiapp driver output with debug level messages enabled, please? I think the problem was with the secondary sensor. -- Kind regards, Sakari Ailus e-mail: sakari.ailus@iki.fi XMPP: sailus@retiisi.org.uk
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| From | Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
|---|---|
| Date | 2017-02-14 23:20 +0100 |
| Subject | Re: [RFC 08/13] smiapp-pll: Take existing divisor into account in minimum divisor check |
| Message-ID | <taTC2-7Be-17@gated-at.bofh.it> |
| In reply to | #1580898 |
Hi Sakari,
On Wednesday 15 Feb 2017 00:05:03 Sakari Ailus wrote:
> On Tue, Feb 14, 2017 at 02:40:04PM +0100, Pavel Machek wrote:
> > From: Sakari Ailus <sakari.ailus@iki.fi>
> >
> > Required added multiplier (and divisor) calculation did not take into
> > account the existing divisor when checking the values against the
> > minimum divisor. Do just that.
> >
> > Signed-off-by: Sakari Ailus <sakari.ailus@iki.fi>
> > Signed-off-by: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com>
> > Signed-off-by: Pavel Machek <pavel@ucw.cz>
>
> I need to understand again why did I write this patch. :-)
I was about to mention that a more detailed commit message (or possibly event
comments in the source code) would be good :-)
> Could you send me the smiapp driver output with debug level messages
> enabled, please?
>
> I think the problem was with the secondary sensor.
>
> > diff --git a/drivers/media/i2c/smiapp-pll.c
> > b/drivers/media/i2c/smiapp-pll.c
> > index 771db56..166bbaf 100644
> > --- a/drivers/media/i2c/smiapp-pll.c
> > +++ b/drivers/media/i2c/smiapp-pll.c
> > @@ -16,6 +16,8 @@
> > * General Public License for more details.
> > */
> >
> > +#define DEBUG
> > +
This should be removed.
> > #include <linux/device.h>
> > #include <linux/gcd.h>
> > #include <linux/lcm.h>
> > @@ -227,7 +229,8 @@ static int __smiapp_pll_calculate(
> > more_mul_factor = lcm(div, pll->pre_pll_clk_div) / div;
> > dev_dbg(dev, "more_mul_factor: %u\n", more_mul_factor);
> >
> > - more_mul_factor = lcm(more_mul_factor, op_limits->min_sys_clk_div);
> > + more_mul_factor = lcm(more_mul_factor,
> > + DIV_ROUND_UP(op_limits->min_sys_clk_div, div));
> > dev_dbg(dev, "more_mul_factor: min_op_sys_clk_div: %d\n",
> > more_mul_factor);
> > i = roundup(more_mul_min, more_mul_factor);
> > @@ -456,6 +459,10 @@ int smiapp_pll_calculate(struct device *dev,
> > i = gcd(pll->pll_op_clk_freq_hz, pll->ext_clk_freq_hz);
> > mul = div_u64(pll->pll_op_clk_freq_hz, i);
> > div = pll->ext_clk_freq_hz / i;
> > + if (!mul) {
> > + dev_err(dev, "forcing mul to 1\n");
> > + mul = 1;
> > + }
> > dev_dbg(dev, "mul %u / div %u\n", mul, div);
> >
> > min_pre_pll_clk_div =
--
Regards,
Laurent Pinchart
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| From | Pavel Machek <pavel@ucw.cz> |
|---|---|
| Date | 2017-02-15 12:30 +0100 |
| Message-ID | <tb5Wy-7HU-15@gated-at.bofh.it> |
| In reply to | #1580898 |
[Multipart message — attachments visible in raw view] — view raw
On Wed 2017-02-15 00:05:03, Sakari Ailus wrote: > Hi Pavel, > > On Tue, Feb 14, 2017 at 02:40:04PM +0100, Pavel Machek wrote: > > From: Sakari Ailus <sakari.ailus@iki.fi> > > > > Required added multiplier (and divisor) calculation did not take into > > account the existing divisor when checking the values against the > > minimum divisor. Do just that. > > > > Signed-off-by: Sakari Ailus <sakari.ailus@iki.fi> > > Signed-off-by: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com> > > Signed-off-by: Pavel Machek <pavel@ucw.cz> > > I need to understand again why did I write this patch. :-) Can you just trust your former self? > Could you send me the smiapp driver output with debug level messages > enabled, please? > I think the problem was with the secondary sensor. I believe it was with the main sensor, actually. Anyway, here are the messages. [ 0.791290] smiapp 2-0010: could not get clock (-517) [ 2.705352] smiapp 2-0010: GPIO lookup for consumer xshutdown [ 2.705352] smiapp 2-0010: using device tree for GPIO lookup [ 2.705413] smiapp 2-0010: using lookup tables for GPIO lookup [ 2.705413] smiapp 2-0010: lookup for GPIO xshutdown failed [ 2.875244] smiapp 2-0010: lane_op_clock_ratio: 1 [ 2.875274] smiapp 2-0010: binning: 1x1 [ 2.875274] smiapp 2-0010: min / max pre_pll_clk_div: 1 / 4 [ 2.875305] smiapp 2-0010: pre-pll check: min / max pre_pll_clk_div: 1 / 1 [ 2.875305] smiapp 2-0010: mul 25 / div 2 [ 2.875305] smiapp 2-0010: pll_op check: min / max pre_pll_clk_div: 1 / 1 [ 2.875335] smiapp 2-0010: pre_pll_clk_div 1 [ 2.875335] smiapp 2-0010: more_mul_max: max_pll_multiplier check: 1 [ 2.875335] smiapp 2-0010: more_mul_max: max_pll_op_freq_hz check: 1 [ 2.875335] smiapp 2-0010: more_mul_max: max_op_sys_clk_div check: 1 [ 2.875366] smiapp 2-0010: more_mul_max: min_pll_multiplier check: 1 [ 2.875366] smiapp 2-0010: more_mul_min: min_pll_op_freq_hz check: 1 [ 2.875366] smiapp 2-0010: more_mul_min: min_pll_multiplier check: 1 [ 2.875396] smiapp 2-0010: more_mul_factor: 1 [ 2.875396] smiapp 2-0010: more_mul_factor: min_op_sys_clk_div: 1 [ 2.875396] smiapp 2-0010: final more_mul: 1 [ 2.875427] smiapp 2-0010: op_sys_clk_div: 2 [ 2.875427] smiapp 2-0010: op_pix_clk_div: 10 [ 2.875427] smiapp 2-0010: pre_pll_clk_div 1 [ 2.875457] smiapp 2-0010: pll_multiplier 25 [ 2.875457] smiapp 2-0010: vt_sys_clk_div 2 [ 2.875457] smiapp 2-0010: vt_pix_clk_div 10 [ 2.875457] smiapp 2-0010: ext_clk_freq_hz 9600000 [ 2.875488] smiapp 2-0010: pll_ip_clk_freq_hz 9600000 [ 2.875488] smiapp 2-0010: pll_op_clk_freq_hz 240000000 [ 2.875488] smiapp 2-0010: vt_sys_clk_freq_hz 120000000 [ 2.875518] smiapp 2-0010: vt_pix_clk_freq_hz 12000000 [ 2.876068] smiapp 2-0010: lane_op_clock_ratio: 1 [ 2.876068] smiapp 2-0010: binning: 1x1 [ 2.876098] smiapp 2-0010: min / max pre_pll_clk_div: 1 / 4 [ 2.876098] smiapp 2-0010: pre-pll check: min / max pre_pll_clk_div: 1 / 1 [ 2.876098] smiapp 2-0010: mul 25 / div 2 [ 2.876129] smiapp 2-0010: pll_op check: min / max pre_pll_clk_div: 1 / 1 [ 2.876129] smiapp 2-0010: pre_pll_clk_div 1 [ 2.876129] smiapp 2-0010: more_mul_max: max_pll_multiplier check: 1 [ 2.876159] smiapp 2-0010: more_mul_max: max_pll_op_freq_hz check: 1 [ 2.876159] smiapp 2-0010: more_mul_max: max_op_sys_clk_div check: 1 [ 2.876159] smiapp 2-0010: more_mul_max: min_pll_multiplier check: 1 [ 2.876190] smiapp 2-0010: more_mul_min: min_pll_op_freq_hz check: 1 [ 2.876190] smiapp 2-0010: more_mul_min: min_pll_multiplier check: 1 [ 2.876190] smiapp 2-0010: more_mul_factor: 1 [ 2.876190] smiapp 2-0010: more_mul_factor: min_op_sys_clk_div: 1 [ 2.876220] smiapp 2-0010: final more_mul: 1 [ 2.876220] smiapp 2-0010: op_sys_clk_div: 2 [ 2.876220] smiapp 2-0010: op_pix_clk_div: 10 [ 2.876251] smiapp 2-0010: pre_pll_clk_div 1 [ 2.876251] smiapp 2-0010: pll_multiplier 25 [ 2.876251] smiapp 2-0010: vt_sys_clk_div 2 [ 2.876251] smiapp 2-0010: vt_pix_clk_div 10 [ 2.876281] smiapp 2-0010: ext_clk_freq_hz 9600000 [ 2.876281] smiapp 2-0010: pll_ip_clk_freq_hz 9600000 [ 2.876281] smiapp 2-0010: pll_op_clk_freq_hz 240000000 [ 2.876312] smiapp 2-0010: vt_sys_clk_freq_hz 120000000 [ 2.876312] smiapp 2-0010: vt_pix_clk_freq_hz 12000000 ... [ 4.728973] udevd[216]: starting version 175 [ 8.031494] smiapp 2-0010: lane_op_clock_ratio: 1 [ 8.031524] smiapp 2-0010: binning: 1x1 [ 8.031524] smiapp 2-0010: min / max pre_pll_clk_div: 1 / 4 [ 8.031524] smiapp 2-0010: pre-pll check: min / max pre_pll_clk_div: 1 / 1 [ 8.031555] smiapp 2-0010: mul 25 / div 2 [ 8.031555] smiapp 2-0010: pll_op check: min / max pre_pll_clk_div: 1 / 1 [ 8.031555] smiapp 2-0010: pre_pll_clk_div 1 [ 8.031585] smiapp 2-0010: more_mul_max: max_pll_multiplier check: 1 [ 8.031585] smiapp 2-0010: more_mul_max: max_pll_op_freq_hz check: 1 [ 8.031585] smiapp 2-0010: more_mul_max: max_op_sys_clk_div check: 1 [ 8.031616] smiapp 2-0010: more_mul_max: min_pll_multiplier check: 1 [ 8.031616] smiapp 2-0010: more_mul_min: min_pll_op_freq_hz check: 1 [ 8.031616] smiapp 2-0010: more_mul_min: min_pll_multiplier check: 1 [ 8.031616] smiapp 2-0010: more_mul_factor: 1 [ 8.031646] smiapp 2-0010: more_mul_factor: min_op_sys_clk_div: 1 [ 8.031646] smiapp 2-0010: final more_mul: 1 [ 8.031646] smiapp 2-0010: op_sys_clk_div: 2 [ 8.031677] smiapp 2-0010: op_pix_clk_div: 10 [ 8.031677] smiapp 2-0010: pre_pll_clk_div 1 [ 8.031677] smiapp 2-0010: pll_multiplier 25 [ 8.031707] smiapp 2-0010: vt_sys_clk_div 2 [ 8.031707] smiapp 2-0010: vt_pix_clk_div 10 [ 8.031707] smiapp 2-0010: ext_clk_freq_hz 9600000 [ 8.031738] smiapp 2-0010: pll_ip_clk_freq_hz 9600000 [ 8.031738] smiapp 2-0010: pll_op_clk_freq_hz 240000000 [ 8.031738] smiapp 2-0010: vt_sys_clk_freq_hz 120000000 [ 8.031768] smiapp 2-0010: vt_pix_clk_freq_hz 12000000 [ 8.064117] smiapp 2-0010: lane_op_clock_ratio: 1 [ 8.064147] smiapp 2-0010: binning: 1x1 [ 8.064147] smiapp 2-0010: min / max pre_pll_clk_div: 1 / 4 [ 8.064178] smiapp 2-0010: pre-pll check: min / max pre_pll_clk_div: 1 / 1 [ 8.064178] smiapp 2-0010: mul 25 / div 2 [ 8.064178] smiapp 2-0010: pll_op check: min / max pre_pll_clk_div: 1 / 1 [ 8.064208] smiapp 2-0010: pre_pll_clk_div 1 [ 8.064208] smiapp 2-0010: more_mul_max: max_pll_multiplier check: 1 [ 8.064208] smiapp 2-0010: more_mul_max: max_pll_op_freq_hz check: 1 [ 8.064239] smiapp 2-0010: more_mul_max: max_op_sys_clk_div check: 1 [ 8.064239] smiapp 2-0010: more_mul_max: min_pll_multiplier check: 1 [ 8.064239] smiapp 2-0010: more_mul_min: min_pll_op_freq_hz check: 1 [ 8.064239] smiapp 2-0010: more_mul_min: min_pll_multiplier check: 1 [ 8.064270] smiapp 2-0010: more_mul_factor: 1 [ 8.064270] smiapp 2-0010: more_mul_factor: min_op_sys_clk_div: 1 [ 8.064270] smiapp 2-0010: final more_mul: 1 [ 8.064300] smiapp 2-0010: op_sys_clk_div: 2 [ 8.064300] smiapp 2-0010: op_pix_clk_div: 10 [ 8.064300] smiapp 2-0010: pre_pll_clk_div 1 [ 8.064331] smiapp 2-0010: pll_multiplier 25 [ 8.064331] smiapp 2-0010: vt_sys_clk_div 2 [ 8.064331] smiapp 2-0010: vt_pix_clk_div 10 [ 8.064361] smiapp 2-0010: ext_clk_freq_hz 9600000 [ 8.064361] smiapp 2-0010: pll_ip_clk_freq_hz 9600000 [ 8.064361] smiapp 2-0010: pll_op_clk_freq_hz 240000000 [ 8.064392] smiapp 2-0010: vt_sys_clk_freq_hz 120000000 [ 8.064392] smiapp 2-0010: vt_pix_clk_freq_hz 12000000 Best regards, Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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| From | Pavel Machek <pavel@ucw.cz> |
|---|---|
| Date | 2017-02-28 15:10 +0100 |
| Message-ID | <tfQDw-5uI-7@gated-at.bofh.it> |
| In reply to | #1581232 |
[Multipart message — attachments visible in raw view] — view raw
Hi! > > On Tue, Feb 14, 2017 at 02:40:04PM +0100, Pavel Machek wrote: > > > From: Sakari Ailus <sakari.ailus@iki.fi> > > > > > > Required added multiplier (and divisor) calculation did not take into > > > account the existing divisor when checking the values against the > > > minimum divisor. Do just that. > > > > > > Signed-off-by: Sakari Ailus <sakari.ailus@iki.fi> > > > Signed-off-by: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com> > > > Signed-off-by: Pavel Machek <pavel@ucw.cz> > > > > I need to understand again why did I write this patch. :-) > > Can you just trust your former self? > > > Could you send me the smiapp driver output with debug level messages > > enabled, please? > > > I think the problem was with the secondary sensor. > > I believe it was with the main sensor, actually. Anyway, here are the > messages. Can I get you to apply this one? :-). Thanks, Pavel > [ 0.791290] smiapp 2-0010: could not get clock (-517) > [ 2.705352] smiapp 2-0010: GPIO lookup for consumer xshutdown > [ 2.705352] smiapp 2-0010: using device tree for GPIO lookup > [ 2.705413] smiapp 2-0010: using lookup tables for GPIO lookup > [ 2.705413] smiapp 2-0010: lookup for GPIO xshutdown failed > [ 2.875244] smiapp 2-0010: lane_op_clock_ratio: 1 > [ 2.875274] smiapp 2-0010: binning: 1x1 > [ 2.875274] smiapp 2-0010: min / max pre_pll_clk_div: 1 / 4 > [ 2.875305] smiapp 2-0010: pre-pll check: min / max > pre_pll_clk_div: 1 / 1 > [ 2.875305] smiapp 2-0010: mul 25 / div 2 > [ 2.875305] smiapp 2-0010: pll_op check: min / max pre_pll_clk_div: > 1 / 1 > [ 2.875335] smiapp 2-0010: pre_pll_clk_div 1 > [ 2.875335] smiapp 2-0010: more_mul_max: max_pll_multiplier check: > 1 > [ 2.875335] smiapp 2-0010: more_mul_max: max_pll_op_freq_hz check: > 1 > [ 2.875335] smiapp 2-0010: more_mul_max: max_op_sys_clk_div check: > 1 > [ 2.875366] smiapp 2-0010: more_mul_max: min_pll_multiplier check: > 1 > [ 2.875366] smiapp 2-0010: more_mul_min: min_pll_op_freq_hz check: > 1 > [ 2.875366] smiapp 2-0010: more_mul_min: min_pll_multiplier check: > 1 > [ 2.875396] smiapp 2-0010: more_mul_factor: 1 > [ 2.875396] smiapp 2-0010: more_mul_factor: min_op_sys_clk_div: 1 > [ 2.875396] smiapp 2-0010: final more_mul: 1 > [ 2.875427] smiapp 2-0010: op_sys_clk_div: 2 > [ 2.875427] smiapp 2-0010: op_pix_clk_div: 10 > [ 2.875427] smiapp 2-0010: pre_pll_clk_div 1 > [ 2.875457] smiapp 2-0010: pll_multiplier 25 > [ 2.875457] smiapp 2-0010: vt_sys_clk_div 2 > [ 2.875457] smiapp 2-0010: vt_pix_clk_div 10 > [ 2.875457] smiapp 2-0010: ext_clk_freq_hz 9600000 > [ 2.875488] smiapp 2-0010: pll_ip_clk_freq_hz 9600000 > [ 2.875488] smiapp 2-0010: pll_op_clk_freq_hz 240000000 > [ 2.875488] smiapp 2-0010: vt_sys_clk_freq_hz 120000000 > [ 2.875518] smiapp 2-0010: vt_pix_clk_freq_hz 12000000 > [ 2.876068] smiapp 2-0010: lane_op_clock_ratio: 1 > [ 2.876068] smiapp 2-0010: binning: 1x1 > [ 2.876098] smiapp 2-0010: min / max pre_pll_clk_div: 1 / 4 > [ 2.876098] smiapp 2-0010: pre-pll check: min / max > pre_pll_clk_div: 1 / 1 > [ 2.876098] smiapp 2-0010: mul 25 / div 2 > [ 2.876129] smiapp 2-0010: pll_op check: min / max pre_pll_clk_div: > 1 / 1 > [ 2.876129] smiapp 2-0010: pre_pll_clk_div 1 > [ 2.876129] smiapp 2-0010: more_mul_max: max_pll_multiplier check: > 1 > [ 2.876159] smiapp 2-0010: more_mul_max: max_pll_op_freq_hz check: > 1 > [ 2.876159] smiapp 2-0010: more_mul_max: max_op_sys_clk_div check: > 1 > [ 2.876159] smiapp 2-0010: more_mul_max: min_pll_multiplier check: > 1 > [ 2.876190] smiapp 2-0010: more_mul_min: min_pll_op_freq_hz check: > 1 > [ 2.876190] smiapp 2-0010: more_mul_min: min_pll_multiplier check: > 1 > [ 2.876190] smiapp 2-0010: more_mul_factor: 1 > [ 2.876190] smiapp 2-0010: more_mul_factor: min_op_sys_clk_div: 1 > [ 2.876220] smiapp 2-0010: final more_mul: 1 > [ 2.876220] smiapp 2-0010: op_sys_clk_div: 2 > [ 2.876220] smiapp 2-0010: op_pix_clk_div: 10 > [ 2.876251] smiapp 2-0010: pre_pll_clk_div 1 > [ 2.876251] smiapp 2-0010: pll_multiplier 25 > [ 2.876251] smiapp 2-0010: vt_sys_clk_div 2 > [ 2.876251] smiapp 2-0010: vt_pix_clk_div 10 > [ 2.876281] smiapp 2-0010: ext_clk_freq_hz 9600000 > [ 2.876281] smiapp 2-0010: pll_ip_clk_freq_hz 9600000 > [ 2.876281] smiapp 2-0010: pll_op_clk_freq_hz 240000000 > [ 2.876312] smiapp 2-0010: vt_sys_clk_freq_hz 120000000 > [ 2.876312] smiapp 2-0010: vt_pix_clk_freq_hz 12000000 > ... > [ 4.728973] udevd[216]: starting version 175 > [ 8.031494] smiapp 2-0010: lane_op_clock_ratio: 1 > [ 8.031524] smiapp 2-0010: binning: 1x1 > [ 8.031524] smiapp 2-0010: min / max pre_pll_clk_div: 1 / 4 > [ 8.031524] smiapp 2-0010: pre-pll check: min / max > pre_pll_clk_div: 1 / 1 > [ 8.031555] smiapp 2-0010: mul 25 / div 2 > [ 8.031555] smiapp 2-0010: pll_op check: min / max pre_pll_clk_div: > 1 / 1 > [ 8.031555] smiapp 2-0010: pre_pll_clk_div 1 > [ 8.031585] smiapp 2-0010: more_mul_max: max_pll_multiplier check: > 1 > [ 8.031585] smiapp 2-0010: more_mul_max: max_pll_op_freq_hz check: > 1 > [ 8.031585] smiapp 2-0010: more_mul_max: max_op_sys_clk_div check: > 1 > [ 8.031616] smiapp 2-0010: more_mul_max: min_pll_multiplier check: > 1 > [ 8.031616] smiapp 2-0010: more_mul_min: min_pll_op_freq_hz check: > 1 > [ 8.031616] smiapp 2-0010: more_mul_min: min_pll_multiplier check: > 1 > [ 8.031616] smiapp 2-0010: more_mul_factor: 1 > [ 8.031646] smiapp 2-0010: more_mul_factor: min_op_sys_clk_div: 1 > [ 8.031646] smiapp 2-0010: final more_mul: 1 > [ 8.031646] smiapp 2-0010: op_sys_clk_div: 2 > [ 8.031677] smiapp 2-0010: op_pix_clk_div: 10 > [ 8.031677] smiapp 2-0010: pre_pll_clk_div 1 > [ 8.031677] smiapp 2-0010: pll_multiplier 25 > [ 8.031707] smiapp 2-0010: vt_sys_clk_div 2 > [ 8.031707] smiapp 2-0010: vt_pix_clk_div 10 > [ 8.031707] smiapp 2-0010: ext_clk_freq_hz 9600000 > [ 8.031738] smiapp 2-0010: pll_ip_clk_freq_hz 9600000 > [ 8.031738] smiapp 2-0010: pll_op_clk_freq_hz 240000000 > [ 8.031738] smiapp 2-0010: vt_sys_clk_freq_hz 120000000 > [ 8.031768] smiapp 2-0010: vt_pix_clk_freq_hz 12000000 > [ 8.064117] smiapp 2-0010: lane_op_clock_ratio: 1 > [ 8.064147] smiapp 2-0010: binning: 1x1 > [ 8.064147] smiapp 2-0010: min / max pre_pll_clk_div: 1 / 4 > [ 8.064178] smiapp 2-0010: pre-pll check: min / max > pre_pll_clk_div: 1 / 1 > [ 8.064178] smiapp 2-0010: mul 25 / div 2 > [ 8.064178] smiapp 2-0010: pll_op check: min / max pre_pll_clk_div: > 1 / 1 > [ 8.064208] smiapp 2-0010: pre_pll_clk_div 1 > [ 8.064208] smiapp 2-0010: more_mul_max: max_pll_multiplier check: > 1 > [ 8.064208] smiapp 2-0010: more_mul_max: max_pll_op_freq_hz check: > 1 > [ 8.064239] smiapp 2-0010: more_mul_max: max_op_sys_clk_div check: > 1 > [ 8.064239] smiapp 2-0010: more_mul_max: min_pll_multiplier check: > 1 > [ 8.064239] smiapp 2-0010: more_mul_min: min_pll_op_freq_hz check: > 1 > [ 8.064239] smiapp 2-0010: more_mul_min: min_pll_multiplier check: > 1 > [ 8.064270] smiapp 2-0010: more_mul_factor: 1 > [ 8.064270] smiapp 2-0010: more_mul_factor: min_op_sys_clk_div: 1 > [ 8.064270] smiapp 2-0010: final more_mul: 1 > [ 8.064300] smiapp 2-0010: op_sys_clk_div: 2 > [ 8.064300] smiapp 2-0010: op_pix_clk_div: 10 > [ 8.064300] smiapp 2-0010: pre_pll_clk_div 1 > [ 8.064331] smiapp 2-0010: pll_multiplier 25 > [ 8.064331] smiapp 2-0010: vt_sys_clk_div 2 > [ 8.064331] smiapp 2-0010: vt_pix_clk_div 10 > [ 8.064361] smiapp 2-0010: ext_clk_freq_hz 9600000 > [ 8.064361] smiapp 2-0010: pll_ip_clk_freq_hz 9600000 > [ 8.064361] smiapp 2-0010: pll_op_clk_freq_hz 240000000 > [ 8.064392] smiapp 2-0010: vt_sys_clk_freq_hz 120000000 > [ 8.064392] smiapp 2-0010: vt_pix_clk_freq_hz 12000000 > > Best regards, > Pavel > > -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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| From | Sakari Ailus <sakari.ailus@iki.fi> |
|---|---|
| Date | 2017-02-28 15:30 +0100 |
| Message-ID | <tfQWR-5Cn-11@gated-at.bofh.it> |
| In reply to | #1589491 |
On Tue, Feb 28, 2017 at 03:09:21PM +0100, Pavel Machek wrote: > Can I get you to apply this one? :-). Let me try to understand again what does that change actually do. I'll find the time during the rest of this week. I'm starting to think we need a test suite for the PLL calculator... -- Sakari Ailus e-mail: sakari.ailus@iki.fi XMPP: sailus@retiisi.org.uk
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| From | Pali Rohár <pali.rohar@gmail.com> |
|---|---|
| Date | 2017-02-15 12:50 +0100 |
| Message-ID | <tb6fU-7Pm-7@gated-at.bofh.it> |
| In reply to | #1580898 |
On Wednesday 15 February 2017 00:05:03 Sakari Ailus wrote: > Hi Pavel, > > On Tue, Feb 14, 2017 at 02:40:04PM +0100, Pavel Machek wrote: > > From: Sakari Ailus <sakari.ailus@iki.fi> > > > > Required added multiplier (and divisor) calculation did not take into > > account the existing divisor when checking the values against the > > minimum divisor. Do just that. > > > > Signed-off-by: Sakari Ailus <sakari.ailus@iki.fi> > > Signed-off-by: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com> > > Signed-off-by: Pavel Machek <pavel@ucw.cz> > > I need to understand again why did I write this patch. :-) > > Could you send me the smiapp driver output with debug level messages > enabled, please? > > I think the problem was with the secondary sensor. > Hi, search for emails and threads: Message-Id: <1364719448-29894-1-git-send-email-sakari.ailus@iki.fi> Message-ID: <5728ED34.3060402@gmail.com> I think I already resent those information again :-) -- Pali Rohár pali.rohar@gmail.com
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