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[PATCH 1/5] clk: sunxi-ng: mp: Adjust parent rate for pre-dividers

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  [PATCH 1/5] clk: sunxi-ng: mp: Adjust parent rate for pre-dividers Chen-Yu Tsai <wens@csie.org> - 2017-02-14 04:40 +0100
    Re: [PATCH 1/5] clk: sunxi-ng: mp: Adjust parent rate for  pre-dividers Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-02-14 10:40 +0100

#1580253 — [PATCH 1/5] clk: sunxi-ng: mp: Adjust parent rate for pre-dividers

The MP style clocks support an mux with pre-dividers. While the driver
correctly accounted for them in the .determine_rate callback, it did
not in the .recalc_rate and .set_rate callbacks.

This means when calculating the factors in the .set_rate callback, they
would be off by a factor of the active pre-divider. Same goes for
reading back the clock rate after it is set.

Fixes: 2ab836db5097 ("clk: sunxi-ng: Add M-P factor clock support")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---

Maybe we want to Cc stable for this one?

 drivers/clk/sunxi-ng/ccu_mp.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/clk/sunxi-ng/ccu_mp.c b/drivers/clk/sunxi-ng/ccu_mp.c
index 22c2ca7a2a22..b583f186a804 100644
--- a/drivers/clk/sunxi-ng/ccu_mp.c
+++ b/drivers/clk/sunxi-ng/ccu_mp.c
@@ -85,6 +85,10 @@ static unsigned long ccu_mp_recalc_rate(struct clk_hw *hw,
 	unsigned int m, p;
 	u32 reg;
 
+	/* Adjust parent_rate according to pre-dividers */
+	ccu_mux_helper_adjust_parent_for_prediv(&cmp->common, &cmp->mux,
+						-1, &parent_rate);
+
 	reg = readl(cmp->common.base + cmp->common.reg);
 
 	m = reg >> cmp->m.shift;
@@ -117,6 +121,10 @@ static int ccu_mp_set_rate(struct clk_hw *hw, unsigned long rate,
 	unsigned int m, p;
 	u32 reg;
 
+	/* Adjust parent_rate according to pre-dividers */
+	ccu_mux_helper_adjust_parent_for_prediv(&cmp->common, &cmp->mux,
+						-1, &parent_rate);
+
 	max_m = cmp->m.max ?: 1 << cmp->m.width;
 	max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
 
-- 
2.11.0

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#1580430 — Re: [PATCH 1/5] clk: sunxi-ng: mp: Adjust parent rate for pre-dividers

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On Tue, Feb 14, 2017 at 11:35:22AM +0800, Chen-Yu Tsai wrote:
> The MP style clocks support an mux with pre-dividers. While the driver
> correctly accounted for them in the .determine_rate callback, it did
> not in the .recalc_rate and .set_rate callbacks.
> 
> This means when calculating the factors in the .set_rate callback, they
> would be off by a factor of the active pre-divider. Same goes for
> reading back the clock rate after it is set.
> 
> Fixes: 2ab836db5097 ("clk: sunxi-ng: Add M-P factor clock support")
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
> 
> Maybe we want to Cc stable for this one?

I've applied it and added the Cc.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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