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Groups > linux.kernel > #1681159 > unrolled thread
| Started by | Priit Laes <plaes@plaes.org> |
|---|---|
| First post | 2017-07-04 22:10 +0200 |
| Last post | 2017-07-10 10:30 +0200 |
| Articles | 4 — 4 participants |
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[PATCH v5 1/6] clk: sunxi-ng: div: Add support for fixed post-divider Priit Laes <plaes@plaes.org> - 2017-07-04 22:10 +0200
Re: [PATCH v5 1/6] clk: sunxi-ng: div: Add support for fixed post-divider Chen-Yu Tsai <wens@csie.org> - 2017-07-05 06:10 +0200
Re: [PATCH v5 1/6] clk: sunxi-ng: div: Add support for fixed post-divider Maxime Ripard <maxime.ripard@free-electrons.com> - 2017-07-05 09:50 +0200
Re: [linux-sunxi] [PATCH v5 1/6] clk: sunxi-ng: div: Add support for fixed post-divider Olliver Schinagl <oliver@schinagl.nl> - 2017-07-10 10:30 +0200
| From | Priit Laes <plaes@plaes.org> |
|---|---|
| Date | 2017-07-04 22:10 +0200 |
| Subject | [PATCH v5 1/6] clk: sunxi-ng: div: Add support for fixed post-divider |
| Message-ID | <tZCj0-4M6-7@gated-at.bofh.it> |
SATA clock on sun4i/sun7i is of type (parent) / M / 6 where
6 is fixed post-divider.
Signed-off-by: Priit Laes <plaes@plaes.org>
---
drivers/clk/sunxi-ng/ccu_div.c | 18 ++++++++++++++++--
drivers/clk/sunxi-ng/ccu_div.h | 3 ++-
2 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu_div.c b/drivers/clk/sunxi-ng/ccu_div.c
index c0e5c10..054b12a 100644
--- a/drivers/clk/sunxi-ng/ccu_div.c
+++ b/drivers/clk/sunxi-ng/ccu_div.c
@@ -21,6 +21,9 @@ static unsigned long ccu_div_round_rate(struct ccu_mux_internal *mux,
{
struct ccu_div *cd = data;
+ if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
+ rate /= cd->fixed_post_div;
+
return divider_round_rate_parent(&cd->common.hw, parent,
rate, parent_rate,
cd->div.table, cd->div.width,
@@ -62,8 +65,13 @@ static unsigned long ccu_div_recalc_rate(struct clk_hw *hw,
parent_rate = ccu_mux_helper_apply_prediv(&cd->common, &cd->mux, -1,
parent_rate);
- return divider_recalc_rate(hw, parent_rate, val, cd->div.table,
- cd->div.flags);
+ val = divider_recalc_rate(hw, parent_rate, val, cd->div.table,
+ cd->div.flags);
+
+ if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
+ val /= cd->fixed_post_div;
+
+ return val;
}
static int ccu_div_determine_rate(struct clk_hw *hw,
@@ -71,6 +79,9 @@ static int ccu_div_determine_rate(struct clk_hw *hw,
{
struct ccu_div *cd = hw_to_ccu_div(hw);
+ if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
+ req->rate *= cd->fixed_post_div;
+
return ccu_mux_helper_determine_rate(&cd->common, &cd->mux,
req, ccu_div_round_rate, cd);
}
@@ -89,6 +100,9 @@ static int ccu_div_set_rate(struct clk_hw *hw, unsigned long rate,
val = divider_get_val(rate, parent_rate, cd->div.table, cd->div.width,
cd->div.flags);
+ if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
+ val /= cd->fixed_post_div;
+
spin_lock_irqsave(cd->common.lock, flags);
reg = readl(cd->common.base + cd->common.reg);
diff --git a/drivers/clk/sunxi-ng/ccu_div.h b/drivers/clk/sunxi-ng/ccu_div.h
index 08d0744..f3a5028 100644
--- a/drivers/clk/sunxi-ng/ccu_div.h
+++ b/drivers/clk/sunxi-ng/ccu_div.h
@@ -86,9 +86,10 @@ struct ccu_div_internal {
struct ccu_div {
u32 enable;
- struct ccu_div_internal div;
+ struct ccu_div_internal div;
struct ccu_mux_internal mux;
struct ccu_common common;
+ unsigned int fixed_post_div;
};
#define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \
--
git-series 0.9.1
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| From | Chen-Yu Tsai <wens@csie.org> |
|---|---|
| Date | 2017-07-05 06:10 +0200 |
| Message-ID | <tZJNw-1bv-7@gated-at.bofh.it> |
| In reply to | #1681159 |
On Wed, Jul 5, 2017 at 4:04 AM, Priit Laes <plaes@plaes.org> wrote: > SATA clock on sun4i/sun7i is of type (parent) / M / 6 where > 6 is fixed post-divider. > > Signed-off-by: Priit Laes <plaes@plaes.org> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
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| From | Maxime Ripard <maxime.ripard@free-electrons.com> |
|---|---|
| Date | 2017-07-05 09:50 +0200 |
| Subject | Re: [PATCH v5 1/6] clk: sunxi-ng: div: Add support for fixed post-divider |
| Message-ID | <tZNep-3lf-5@gated-at.bofh.it> |
| In reply to | #1681159 |
[Multipart message — attachments visible in raw view] — view raw
On Tue, Jul 04, 2017 at 11:04:56PM +0300, Priit Laes wrote:
> SATA clock on sun4i/sun7i is of type (parent) / M / 6 where
> 6 is fixed post-divider.
>
> Signed-off-by: Priit Laes <plaes@plaes.org>
> ---
> drivers/clk/sunxi-ng/ccu_div.c | 18 ++++++++++++++++--
> drivers/clk/sunxi-ng/ccu_div.h | 3 ++-
> 2 files changed, 18 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu_div.c b/drivers/clk/sunxi-ng/ccu_div.c
> index c0e5c10..054b12a 100644
> --- a/drivers/clk/sunxi-ng/ccu_div.c
> +++ b/drivers/clk/sunxi-ng/ccu_div.c
> @@ -21,6 +21,9 @@ static unsigned long ccu_div_round_rate(struct ccu_mux_internal *mux,
> {
> struct ccu_div *cd = data;
>
> + if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
> + rate /= cd->fixed_post_div;
> +
> return divider_round_rate_parent(&cd->common.hw, parent,
> rate, parent_rate,
> cd->div.table, cd->div.width,
This doesn't work.
The rate formula is
rate = parent / div / 6
Which is equivalent to
div = rate * 6 / parent
You should be multiplying the rate, not dividing it (or dividing the
parent, but then you'll also need to multiply it back after the call
to divider_round_rate_parent).
Consider this, some driver wants to set a rate of 100MHz on this
clock. The parent is 1.2GHz, and you have your postdiv of 6.
The divider we want to compute is 2, obviously.
You're doing here:
rate / 6 = parent / div
Which means that you'll end up trying to find the divider between
1.2GHz and 16.6666MHz, which is going to be 72.
> @@ -62,8 +65,13 @@ static unsigned long ccu_div_recalc_rate(struct clk_hw *hw,
> parent_rate = ccu_mux_helper_apply_prediv(&cd->common, &cd->mux, -1,
> parent_rate);
>
> - return divider_recalc_rate(hw, parent_rate, val, cd->div.table,
> - cd->div.flags);
> + val = divider_recalc_rate(hw, parent_rate, val, cd->div.table,
> + cd->div.flags);
> +
> + if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
> + val /= cd->fixed_post_div;
> +
> + return val;
> }
>
> static int ccu_div_determine_rate(struct clk_hw *hw,
> @@ -71,6 +79,9 @@ static int ccu_div_determine_rate(struct clk_hw *hw,
> {
> struct ccu_div *cd = hw_to_ccu_div(hw);
>
> + if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
> + req->rate *= cd->fixed_post_div;
> +
I guess this is why you never really saw the issue. Combined with your
division in ccu_div_round_rate, it produces the exact rate you were
given as an argument.
> return ccu_mux_helper_determine_rate(&cd->common, &cd->mux,
> req, ccu_div_round_rate, cd);
> }
> @@ -89,6 +100,9 @@ static int ccu_div_set_rate(struct clk_hw *hw, unsigned long rate,
> val = divider_get_val(rate, parent_rate, cd->div.table, cd->div.width,
> cd->div.flags);
>
> + if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
> + val /= cd->fixed_post_div;
> +
If you multiply the rate before calling divider_get_val, you won't
have to do the division of the divider, with all the rounding
weirdness it might create.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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| From | Olliver Schinagl <oliver@schinagl.nl> |
|---|---|
| Date | 2017-07-10 10:30 +0200 |
| Subject | Re: [linux-sunxi] [PATCH v5 1/6] clk: sunxi-ng: div: Add support for fixed post-divider |
| Message-ID | <u1CeR-2AZ-5@gated-at.bofh.it> |
| In reply to | #1681159 |
Hey Plaes,
On 04-07-17 22:04, Priit Laes wrote:
> SATA clock on sun4i/sun7i is of type (parent) / M / 6 where
> 6 is fixed post-divider.
>
> Signed-off-by: Priit Laes <plaes@plaes.org>
> ---
> drivers/clk/sunxi-ng/ccu_div.c | 18 ++++++++++++++++--
> drivers/clk/sunxi-ng/ccu_div.h | 3 ++-
> 2 files changed, 18 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu_div.c b/drivers/clk/sunxi-ng/ccu_div.c
> index c0e5c10..054b12a 100644
> --- a/drivers/clk/sunxi-ng/ccu_div.c
> +++ b/drivers/clk/sunxi-ng/ccu_div.c
> @@ -21,6 +21,9 @@ static unsigned long ccu_div_round_rate(struct ccu_mux_internal *mux,
> {
> struct ccu_div *cd = data;
>
> + if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
> + rate /= cd->fixed_post_div;
> +
> return divider_round_rate_parent(&cd->common.hw, parent,
> rate, parent_rate,
> cd->div.table, cd->div.width,
> @@ -62,8 +65,13 @@ static unsigned long ccu_div_recalc_rate(struct clk_hw *hw,
> parent_rate = ccu_mux_helper_apply_prediv(&cd->common, &cd->mux, -1,
> parent_rate);
>
> - return divider_recalc_rate(hw, parent_rate, val, cd->div.table,
> - cd->div.flags);
> + val = divider_recalc_rate(hw, parent_rate, val, cd->div.table,
> + cd->div.flags);
> +
> + if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
> + val /= cd->fixed_post_div;
> +
> + return val;
> }
>
> static int ccu_div_determine_rate(struct clk_hw *hw,
> @@ -71,6 +79,9 @@ static int ccu_div_determine_rate(struct clk_hw *hw,
> {
> struct ccu_div *cd = hw_to_ccu_div(hw);
>
> + if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
> + req->rate *= cd->fixed_post_div;
> +
> return ccu_mux_helper_determine_rate(&cd->common, &cd->mux,
> req, ccu_div_round_rate, cd);
> }
> @@ -89,6 +100,9 @@ static int ccu_div_set_rate(struct clk_hw *hw, unsigned long rate,
> val = divider_get_val(rate, parent_rate, cd->div.table, cd->div.width,
> cd->div.flags);
>
> + if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
> + val /= cd->fixed_post_div;
> +
> spin_lock_irqsave(cd->common.lock, flags);
>
> reg = readl(cd->common.base + cd->common.reg);
> diff --git a/drivers/clk/sunxi-ng/ccu_div.h b/drivers/clk/sunxi-ng/ccu_div.h
> index 08d0744..f3a5028 100644
> --- a/drivers/clk/sunxi-ng/ccu_div.h
> +++ b/drivers/clk/sunxi-ng/ccu_div.h
> @@ -86,9 +86,10 @@ struct ccu_div_internal {
> struct ccu_div {
> u32 enable;
>
> - struct ccu_div_internal div;
> + struct ccu_div_internal div;
> struct ccu_mux_internal mux;
> struct ccu_common common;
> + unsigned int fixed_post_div;
> };
>
> #define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \
>
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